SU1034188A1 - Versions of threshold element - Google Patents

Abstract

1. Threshold elekuynt, content. The shift register is also distinguished by IC with the fact that, in order to increase speed and reduce the volume of equipment, a pavillo {{ti, connected information influence inputs with outputs of the shift register, I inputs of which are the inputs of the threshold element, is entered into it) , and the outputs of the memory register are its outputs. S / H /

Description

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2. A threshold element containing a shift register, characterized in that, in order to improve speed and reduction; the volume of the equipment, the memory register and the zero control unit are entered into it, and O-liepBNx of the shift register outputs, where a is the threshold. element, are connected to the information inputs of the memory register, and the rest (AND-O) outputs are connected to the inputs of the zero control unit, the reset input of the memory register is connected to the resolution input for; the shift register.

3. The threshold element on PP. 1 and 2, characterized in that the memory register contains O serially connected blocks, and

the first input of each block is connected to the memory register input, and the second is connected to the second output of the previous block, the first output of each block is connected to the register output, each block consists of an installation trigger connected by a direct input to the output of the first And element, the first input to The second is the first input of the block, and the second is connected to the first input of the second element AND of this block and its second input, the second input of the second element AND is connected to the forward output of the trigger, which is the first output of the block, and the output of the second element AND is the second the output of the block, the inverse inputs of all the triggers are connected to the reset input of the memory register

The invention relates to automation and computing and can be used to build various devices for processing discrete information.

The majority logic element is known, which contains weight transducers of two inputs consisting of elements and and OR with inputs connected in parallel, a threshold shaping unit and an output OR element. The threshold formation unit is made in two stages, containing two identical stages of forming a set of weights of the first stage, the complementary weight outputs of which are pairwise connected to the inputs of the elements I of the Cascade forming the second stage tl3.

The disadvantage of this device is its low functionality.

The closest to the proposed technical entity is a threshold element, Jcp generator, scanning multiplexor consisting of a shift register connected by outputs to the first inputs of the AND elements, the second inputs of which are connected to the inputs of the threshold element, and outputs to the inputs of the OR element. The outputs of the multiplexer are connected to the inputs of a counter connected to the outputs of the detector, the output of which is the output of element 2.

The disadvantages of this device are the complexity of the technical implementation and low speed.

The purpose of the invention is to increase the speed and reduce the amount of equipment.

To achieve this goal, a memory register connected by information inputs to the outputs of the shift register, the inputs

5 of which are the inputs of the threshold element and the outputs of the memory register outputs.

In addition, the threshold element containing the shift register is entered

О the memory register and the zero control unit, and the first outputs of the shift register, where O is the threshold of the element, are connected to the information inputs of the memory register, and the rest

5 (And - Q) outputs - with block inputs

control of zeroing, the reset input of the memory register is connected to the enable input G of the shift register.

Register: the memory contains SG serially connected blocks, the first input of each block is connected to the input of the memory register, and the second with the second output of the previous block, the first output of each block is connected 5 to the register output, each block consists of an installation trigger connected by a direct input With the output of the first element And, the first input of which is the first input of the block, and the second is connected to the first input of the second element And of this block and its second input, the second input of the second element And is connected to the direct output trigger a, which is the first output of the block, and the output of the second eleH MeHTai I - the second output of the block; the inverse inputs of all the flip-flops are connected to the reset input of the memory register.

FIG. 1 shows the 0 structure of the proposed element, the first option; in fig. 2 is a diagram of a memory register, in FIG. 3 - the block diagram of the proposed element the second option.

The proposed element (Fig. 1) consists of shift and memory registers 1 and 2. The setup inputs of the shift register 1 are connected to the information inputs of the 3 threshold element, and its shift input is connected to the input 4 of the threshold element. The first O outputs of the shift register 1 (where Q is the threshold) are connected to the inputs of the register 2, whose outputs are connected to the outputs of the 5th threshold element, Ogo 6. reset register is connected to the input of the threshold element.

Register-2 memory (Fig. 2) consists of blocks. The first input of each block is connected to the register input, and the second to the second output of the previous block, the first output of each block is the register output. Each block 7-1; m 7- (3 | consists of an installation trigger 8 connected by a direct input to the output of an AND 9 element, the first input of which is the first input of the block, and the second is connected to the first input of the AND 10 element. The second the input element tl 10 is connected to the direct output of the trigger 8 and the first output of the block.The inverse outputs of all the flip-flops 8 are connected to the input b of the register a.

The proposed element in the second embodiment (Fig. 3) consists of the shift register 11, the memory register 12 and the zeroing control unit 13. The setup inputs of the shift register 11 are connected to the information inputs 14 of the threshold element having input 15. The reset input of the memory register 12 is connected to the write input of the shift register 11 and the input 16 of the register .11. The shift register input 11 is connected to the input 15 of the threshold element, the outputs of which are the output 17 of the zero counter control unit 13 and the output 18 of the last bit of the memory register 12. The first QJs, the outputs of the shift register 11 (the first output, is the output of the rightmost bit of the shift register) are connected to the inputs of the memory register 12, and the remaining 0; Y.-6 () outputs to the inputs of the null control unit 13. The first digit of the 12-bit register is the right-most bit.

The zeroing control unit 13 can be made in the form of an AND element with direct inputs if it is connected to the inverse outputs of the shift register 11, -A as an AND element with inverse inputs if it is connected to the direct outputs of the shift register 11

The operation of the proposed element in the first embodiment is as follows (Fig. 1 and 2).

In the initial state, registers 1 and 2 are reset, their outputs have zero potentials. The input code is applied to the inputs 3 of the threshold element and is written to the shift register 1. Next, clock pulses are sent to input 4. When each clock pulse is applied, there is a right shift for one bit of the code recorded in shift register 1. When a single potential appears in the first order of the first shift register 1, which is the rightmost bit, 6n is written to the second register and the first output appears to be a single unit, allowing the unit potential to write in the second bit of the register. 2 memories. When a single potential appears at the output of the second bit of the shift register 1, it is written to the memory register 2 and a single potential appears at its second output allowing the writing of the single potential for the third time in memory 2. The next job is analogous. A single potential appears at the .th output of the memory register 2, if all previous outputs have a single potential and at the output of the lh-th digit, the shift register 1 also has a single potential, at the same time the i-one is written potential in f 1 +.1) -th register bit of 2 pa- j mti. So in the process; the operation of the input code shift in the shift register is done right to the right, and in full if the memory register 2 is right to left;

Through (Vt -d) clocks, the input signal corresponding to the last section of the input code appears on | on input (Q. shift register 1). The signal at the output of the last, th bit of memory register 2 at this time and later corresponds to the result of the device operation. It is the unit potential if the number of units in the GWBD code was greater than or equal to noporyllH element, and zero potential otherwise.

Thus, to generate an output signal, it is required (AND-O device operation cycles.

The operation of the proposed element in the embodiment (fig.Z) is as follows.

A trigger pulse is applied to the input 16 of register 11, upon arrival of which a memory register 12 is reset and the input code input to the inputs 14 of the threshold element is written to the shift register 11. Further.

clock pulses are supplied to its input 15. When each clock pulse is applied, there is a shift to the right by one bit of code written to shift register 11. The first bit of the shift register 11 is the outermost & bit. As the code shifts in the shift register 11 from left to right, the bits in the memory register 12 are filled with unit potentials in the opposite direction from right to left. The operation occurs in such a way before the occurrence of a single potential at the output of the last: 0-th bit of register 12 memory or zero potentials on all inputs of block zero control | | its output 17 is a single potential. The output signal is removed from the output of the last q.th bit of register 12 memory.

To generate the output signal, .voT до is required prior to (and -0) ticks.

Thus, the proposed element provides an increase in speed, since to obtain a result, it is required from 0 to (AND-O) operation cycles depending on the input code, while in the prototype device, the operation cycle is (AND-2) cycles. In addition, the proposed element has a smaller amount of equipment.

Claims (3)

THRESHOLD ELEMENT (ITS OPTIONS) ^ D. A threshold element containing a shift register is different: in order to increase the speed and reduce the amount of equipment, a memory register is introduced into it, connected by information inputs to the outputs of the shift register, whose inputs are inputs of the threshold element, and the outputs of the memory register - its outputs. U _m 1034188 2. a threshold element containing a shift register, characterized in that, in order to improve performance and reduce: the amount of equipment, a memory register and a zero control unit are introduced into it, with C1 £ _{4 of the} first outputs of the shift register, where a is the threshold 'of the element, connected to the data inputs of the register memory, and the rest (I -0) outputs - to the inputs of _{the second} control unit zeroing memory register reset input is connected to the input of shift register write permission. 3. The threshold element according to paragraphs. 1 and 2, characterized in that the memory register contains O · series-connected blocks, with the first input of each block connected to the input of the memory register, and the second with the second output of the previous block, the first output of each block connected to the output of the register, each block consists from the installation trigger connected by a direct input to the output of the first AND element, the first input of which is the first input of the block, and the second is connected to the first input of the second AND element of this block and its second input, the second input of the second AND element is connected direct access to the trigger, which is the first output unit and the output of second AND - a second output block, inverse inputs of all flip-flops are connected to the reset input of a memory register.