SU1003062A1 - Multichannel device for switching control computing system lines - Google Patents

Description

The device relates to computing technology and, in particular, can be used in control systems.

A multi-channel switching device is known, in which the control of alternately connecting processors to a common trunk is carried out by a dispatcher device analyzing the requests of processors for using common resources such as memory, I / O devices.

Up to eight microcomputers can be combined in the system, seven of which are connected to a common busbar separated from the main bus with common resources. The switching device, in addition to the bus controller containing the switch / includes a resource scheduler 1.

The disadvantage of such a switching device is the presence of fairly complex and therefore insufficiently reliable common elements (in this case, the resource scheduler and the bus controller), the failure of any of which leads to the failure of the entire system.

It is also known a device in which each of a plurality of microcomputers has a local memory, and in addition, a plurality of shared memory devices are provided, each of which is associated with two microcomputers via a control means. Each of a multitude of controls coordinates the microcomputer circuits.

10 to the shared memory and prohibits one of the micro-computers to access the shared memory when a similar treatment is performed by the other micro-computer t 2.

The disadvantage of this system is that it has the common means of controlling the connection to a common storage device for both microcomputers and a small number of micro-computers to be combined;

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The closest technical solution to the invention is a multichannel trunk switching device, in which the main elements are a multiplexer.

25 and timer. The multiplexer is connected to the common mainline of the system and to the local mainlines of the processors. The timer is connected to the multiplexer and processors. Connecting local

A 30-to-common master bus is performed by a multiplexer, in turn, in the time division mode, organized by the phase shift between the sync pulses produced by the timer. This device stands out for its simplicity. 3

A disadvantage of the known device is, firstly, that the failure of any of the switching elements of the lines leads: with the failure of the entire system, secondly, that during failure, any of the processors is not possible by another (healthy) processor maintenance of devices connected to the local line of the failed processor, and, thirdly, the impossibility of switching a large number of local lines.

The aim of the invention is to increase the reliability and throughput of the device.

The goal is achieved by the fact that a multichannel switching device of highways containing n switching blocks, made in the form of a switch, the first inputs-outputs of which are connected to a common highway, and the second inputs-outputs with corresponding local main lines, is inserted into each switching unit element block OR, sensor of the initial value of the counter, control information register, control trigger, first and second OR elements, AND element, blocking trigger and self-off register, with input p The register of control information is connected to the first input-output. switch, the first output is with the first input of the first element OR and with the device processor shutdown output, the second output is with the first input of the second OR element, and the third output is with the first input of the OR element block, the second input of which is connected to the sensor output of the initial counter value, and the output is connected to the parallel recording of the counter, the counting input of which is connected to the output of the I element, and the input of the initial value setting to the first input of the device and the zero input of the lock trigger, the output of the first element OR connected It is connected to a single control trigger input, the zero input of which is connected to the output of the second OR element and a single lock trigger input, the output of which is connected to the first input of the AND element, the second input of which is connected to the second input-output of the device, the second input of the second OR element is connected to the output self-off register, which is connected to the second input-output of the device, the third input of the second element OR is connected

through a switching unit with a device time out input.

Implementing such a structure of a multichannel trunk switching device allows each of the processors to alternately connect to a common trunk, and act as a master, if necessary, disconnect a faulty processor from its local trunk, connect this local. Trunk to a common one, and service devices connected to the local trunk of the failed processor. This device fundamentally does not limit the number of switched local highways. ,

The common trunk of the system and local trunks have the same structure and may, for example, have a three-bus organization, in which the trunk includes: a data bus, an address bus and a control bus. Such an organization is typical for many microprocessor systems built, for example, on the basis of microprocessors such as K580IK80.18080, Mb800, Z80.

One of the assumptions underlying the construction of the proposed switching device is the estimation of the total line's occupancy by the presence of the clock pulses of one of the control bus signals on it.

FIG. Figure 1 shows the general structural scheme of a multichannel trunk switching device as part of a multiprocessor control system; in fig. 2 is a simplified block diagram of one of the possible algorithms for operating a multiprocessor control system built using the proposed multi-channel trunk switching device.

The multichannel trunk switching device contains switch 1, control information register 2, first element OR 3, second element OR 4, block 5 elements OR sensor b of the initial value of the counter, counter 7, element 8, the blocking trigger 9, trigger 10 controlling the register 11 self-shutdown, common trunk 12, local trunk 13, processor 14, watchdog timer

15, common storage devices

16, common input-output devices 17, general auxiliary devices 18 local storage devices 19, local input-output devices 20, loxing auxiliary devices 21.

Claims (3)

A common highway 12 is connected to the switching unit 1 of each switching unit on the one hand, and a local highway 13 is connected to the other side, the input of the control information register 2 is connected to the common highway 12. The first output of the control information register 2 is connected to the input of the first element OR 3 and processor 14. The second output of control information register 2 is connected to the input of the second element OR 4, and the third you} {one register 2 is connected to the input of the block of elements OR 5, the other of the inputs of which is connected to the sensor sensor value channel 6, and the output is connected to the parallel recording input of counter 7. The counting input of counter 7 is connected, to the output of the AND element 8, and the input of the initial value setting is connected to the clock line of the common highway 12 and the zero input of the blocking trigger 9. The output of the OR 3 is connected with a single input of the control trigger 10, the zero input of which is connected to the output of the second element OR 4 and the single input of the locking trigger 9. The output of the blocking trigger 9 is connected to the first input of the AND element 8, the second input of which is connected to the clock line of the local highway 13. The second input of the second element OR 4 is connected to the output of the self-off register 11, the input of which is connected to the local highway 13. The third input of the second element OR 4 through switch 1, it is connected to the output of the watchdog timer 15. In addition to the watchdog timer 15, common storage devices 16, common input-output devices 17, common auxiliary devices 18 are connected to the common trunk 12. In addition to the processor 14, local trunk 13, local storage devices 19, local I / O devices 20, local auxiliary devices 21 are connected. The number of switching units is equal to the number of switched local highways. The device works as follows. In the initial state, the switches 1 of all switching units are in the closed state, and the processors 14 are connected to local backbones 13. On the Bcejc sensors of the switching units 1, the binary numbers are not identical to each other for all processors of the S system of priority. On the capture of the general highway 12. When the system is turned on, the flip-flops 9 and 10 are set to zero, the numbers from the sensors 6 are written into counters 7 via the blocks of the OR elements 5, and sync pulses appear on all local highways 13. The local clock sync signals go to one of the inputs of the And 8 element, to the other input of which a signal is received from the zero output of the blocking trigger 9 and through the And 8 element to the counting input of the counter 7. The counters 7 of all the switching blocks start adding the clock pulses local highway to the initially recorded number. As soon as the counter 7 of any of the switching blocks reaches overflow, a signal is sent from it to the element OR 3, and the control trigger 10 is switched to one state, giving a signal to switch on switch 1. Switch 1 connects the local highway 13 of the corresponding processor with a common highway 12. On the common highway 12, the switching units begin to receive the sync pulses of the common highway, which set in the counters 7 the initial numbers specified on the sensors 6 of the initial value. After executing the entire program requiring communication with devices connected to the common highway 12, the processor 14, the local highway 13 of which is integrated with the common highway 12, is addressed through the highway 12 to the control information register 2 of the switching unit of the processor-successor, i.e. the processor that is next connected to the common trunk. In this case, a number is entered in register 2, which, in addition to the number stored on sensor b, through the block of elements OR 5 is written to counter 7 and informs this switching unit of the highest priority. After that, the processor 14 outputs the control word to the self-off register 11, a single signal from one of the bits of which through the OR 4 element enters the zero input of the trigger 10 and simultaneously triggers the trigger 9. The control trigger 10 removes the control signal from the switch 1; the switch 1 disconnects the local trunk from the common one. The sync pulses no longer flow from the common trunk to the switching blocks and the counters 7 of all the switching blocks, except the newly disconnected lox trunk, begin to count the local clock pulses GOVERNMENTAL highways. The counter 7 of the switching processor unit, which has just been disconnected from the common highway, does not produce a count of clock pulses, since the signal from trigger 9 to the AND element 8 does not arrive. Te-t the first overflow signal is dropping the counter, which is included in the successor processor unit, and as a result, the local highway of this processor is connected to the common highway. If the processor currently connected to the common line receives information that some other processors are faulty (Fig. 2), then it sends the control word to register 5 of this processor such that a single signal from one of the bits arrives to the control input of the faulty procedure 14, turning it off, and through the element OR 3 to the trigger 10, setting it to one state. The trigger 10 turns on the switch 1 which connects to the common trunk 12 the local trunk 13 of the faulty processor. Thereafter, the processor, connected to the common magic, executes a program for maintaining the devices of the failed processor. The watchdog timer 15 is tuned to a time slightly longer than the process time required to operate on a common highway. Each time you change the processor, the local trunk is turned off from the common) the timer is reset. If the processor that captures the-shared trunk is not disconnected from it for longer than the set time, timer 15 is triggered, and the signal from it goes through the switched on switch 1 to the OR 4 element, resets the trigger 10 and turns off switch 1 from the key After that, the common bus enters the processor with the highest priority among the remaining processors. Processors at a time when their local lines are not connected to the common line, their working programs are normally executed. One of the possible algorithms of the processors when connected to the common line is shown in Fig. 2. The system containing N processors starts its operation. switching on. After that, one of the processors (PR K) makes a seizure of the common highway (OM) as described. Then the K-th producer performs his work program and self-test. The self-test ends by inserting the resulting check number into the appropriate cell of the common memory. The processor, which owns a common bus, evaluates the state of other processors and, if necessary, maintains the devices of the faulty processors. This is done in a few steps. First, the control number obtained during the self-test of the processor being tested is compared (nPfiJ with the reference constant. +1 or -1 is added to the content of one of the common RAM cells of the voting cell, the value of the number in the voting cell is evaluated If the processor detects a faulty procesor, the actions indicated in Fig. 2 in the first branch and described when considering the operation of the device (Fig. 1) are taken. After evaluating the state of all pr Processors owning a common bus, the processor checks whether the successor processor specified in its program is related to a faulty one. If the intended processor successor is faulty, then a sequential search will determine the serviceable processor and the first processor that was found to be in good order The processor owning the common trunk (nPfKj) shuts down its local trunk (NM) and goes into operation mode for servicing devices connected to its local trunk. And the successor processor captures the common trunk in the manner described and the system operation cycle is repeated. Approximately the relative economic efficiency of the implementation of the proposed device. It can be estimated by the ratio of the probability of a device to fail (E () t to the probability of a reliable device to be known (Pi) and by an increase in the number of RL-L-0-Pgk processes integrated into the system ) r vnoPvnA where P is the probability of fail-safe operation of the switching unit; x-probability of failure-free operation of the common part of the known device; P is the failure-free operation probability of the part of the known device associated with the individual processor; N is the number of processors in the system. Expression (1) is valid for the cases when a decrease in the polling rate of input channels and issuing control or information signals caused by processor failures does not disrupt the normal operation of the controlled object. Suppose we have the following values of the probability of failure-free operation of the commutation devices: VA 09% o 09 - the reliability indicators and KOMi iyTauHa devices, depending on the number of processors being combined, will be as follows:. The possible number of connected proxies in the proposed device is practically limited only by the electrical characteristics of the highways (permissible length of lines, load capacity, leakage currents) and the size of the meters used. When resolving between set priorities for the capture of a common highway of two pulses for four-bit counters, it is possible to combine up to eight processors into a system. Each additional digit of the counter doubles the possible number of processors to be combined. Thus, with “split” counters, up to 12 processors can be connected to the common bus through the proposed device. In the known device, the number of connected processors is limited by time ratios and cannot exceed several units. Claims of the Invention Multichannel switching device of the control computer systems, containing n switching units, made in the form of a switch, the first inputs / outputs of which are connected to the common highway and the second inputs / outputs - with the corresponding local highways In order to increase its reliability and throughput, a counter, a block of OR elements, a sensor of the initial value of the counter, a control information register, a control trigger are entered into each switching block. , Lane ". the second and second OR elements, the AND element, the blocking trigger and the self-off register, the control information register input connected to the first input-output of the switch, the first output to the first input of the first OR element and the device processor off output, the second output to the first input of the second element OR, and the third output - with the first input of the block of elements OR, the second input of which is connected to the output of the sensor of the initial value of the counter, and the output - to the input of the parallel recording of the counter, the counting input of which is connected to the output And the input of the initial value setting with the first input-output of the device and the zero input of the blocking trigger, the output of the first element OR is connected to the single input of the control trigger, the zero input of which is connected to the output of the second element OR and the single input of the blocking signal whose output connected to the first input of the AND element, the second input of which is connected to the second input-output of the device, the second input of the second element OR is connected to the output of the disconnection register, the input of which is connected to the second input ohm-output device, the third input of the second element OR is connected through the switching unit by the time-out input of the device. Sources of information taken into account in the examination 1. Express Information Computing Engineering, 1977, 24, abstract number 142. 2. US Patent 4065809, cl. 364-200, published. 1979 3. US patent 4,164,787, cl. 364-200, published. 1980 (prototype). /five 18