SK3692000A3 - Method and system for fast routing lookups - Google Patents

Abstract

In a method of IP routing lookup in a routing table, comprising entries of arbitrary length prefixes with associated next-hop information in a next-hop table, to determine where IP datagrams are to be forwarded, a representation of the routing table is stored, in the form of a complete prefix tree (7), defined by the prefixes of all routing table entries. Further, a representation of a bit vector (8) comprising data of a cut through the prefix tree (7) at a current depth (D), and an array of pointers, comprising indices to the next-hop table and to a next-level chunk, are stored. Said bit-vector (8) is divided into bit-masks and a representation of the bit-masks is stored in a maptable. Then, an array of code words, each encoding a row index into the maptable and a pointer offset, and an array of base addresses are stored. Finally, the lookup is performed.

Description

The method of IP directions search in the direction table and the system for IP directions search in the direction table

Technical field

In general, the invention relates to a method and a system of IP directional lookups in a direction table which includes as prefixes of arbitrary length with associated next hop information in the next hop table to determine where the IP datagrams are to be forwarded.

BACKGROUND OF THE INVENTION

The Internet is an interconnected set of networks in which each of the networks that are part of it retains its identity and requires special mechanisms for communication between multiple networks. Networks that are part of the Internet are referred to as subnets.

Each subnet on the Internet supports communication between devices connected to that subnet. Further, subnets are connected by devices referred to as interworking units (IWUs).

A particular IWU is a router that is used to connect two networks that may or may not be similar. This router uses the Internet Protocol (IP) present on each router and on each network host computer.

IP provides a connectionless or datagram service between stations.

Routing is generally accomplished by maintaining a routing table at each station and router that indicates, for each possible destination network, the next router to which the IP datagram is to be sent.

IP routers perform directional lookup in the routing table to determine where IP datagrams are to be forwarded. The result of this operation is as follows

-2 jump to the finish line. The item in the direction table is in principle a prefix of any length with associated information about the next jump. Directional searches must find the routing item with the longest matching prefix.

Because IP routing searches were inherently slow and complex, operations according to prior art solutions have led to the proliferation of techniques that can be avoided. Various link layer switching technologies under IP, methods of bypassing the IP layer (described in Proceedings of the Conference on Computer Communications (IEEE Infocom), San Francisco, California, March 1996; Proceedings of Gigabit NetWork Workshop) on Gigabit networks), Boston, April 1995, and Proceedings of ACM SIGCOMM '95, pp. 49-58, Cambridge, Massachusetts, August 1995) and the development of alternative network layers based on virtual circuit technologies such as ATM To some extent, the results of the desire to avoid IP directional searches.

Using link layer switching and flow or flag switching architecture below the IP level increases network complexity and redundancy.

The latest designs of IP routers use cache techniques, while the routing entries of the currently used destination addresses are kept in the cache. This technique is based on the fact that there is enough space in operation, so that the cache search success rate is high enough and the directional search costs are amortized after a few packets. These cached methods have worked well in the past. However, as the current rapid growth of the Internet increases the required size of address buffers, hardware buffers may become wasteful.

Traditional implementations of turntables use the version of Tree Patients (described in Journal of the ACM 15 (4), 514-534, October 1968), a data structure devised almost thirty years ago, with modifications for the longest prefix match.

-3Direct Implementation The tree belonging for directional search purposes, for example in the NetBSD 1.2 implementation, uses 24 bytes for outputs (blades) and internal nodes. With 40,000 entries, the tree structure itself has almost 2 megabytes, and in a perfectly balanced tree, 15 or 16 nodes must be traversed to find the directional entry.

In some cases, due to the rule of the longest matching prefixes, it is necessary to pass through other nodes in order to find the correct routing information, as it is not guaranteed that the original search will find the correct output. There are optimizations that can reduce the size of the Tree Patient and improve search speeds. Even so, the data structure is large and too many expensive memory links are required to crawl it. The current Internet routing tables are too large to fit in the chip buffers on the chip, and out-of-chip memory references on the DRAMs are too slow to support the required routing speeds.

One of the first works to improve IP routing performance by not using full directional lookups (described in IEEE Infocom, New Orleans, Louisiana, March 1988) found that a small cache of destination addresses can improve directional search performance by at least 65 percent. Less than 10 slots were required to achieve search success rates above 90 percent. Such small caches for destination addresses are not sufficient for the high traffic and number of host computers on the Internet today.

ATM (asynchronous transfer mode) bypasses performing directional searches by having a signaling protocol that transmits addresses to the network while establishing a connection. The send state, as determined by the virtual circuit identifier (VCI), is installed in the switches along the link path during the connection establishment. ATM cells contain VCIs, which can then be used as a direct index to the send status table or as a key to the transformation function. Directional decision making is easier for ATM. However, if the packet sizes are larger than 48 bytes, more ATM directional decisions need to be made.

Symptom Switching and Flow Switching (described in IEEE Infocom, San Francisco, California, March 1996) are two IP bypass methods that are designed to operate over ATM. The basic idea is to let IP control ATM-level hardware at the connection level, which performs real data forwarding. Among the routers, special purpose protocols (described in Request for Comments RFC 1953, Internet Engineering Task Force, May 1996) are required to agree which ATM virtual circuit identifiers to use and which packet should be used by which VCI.

Another approach with the same goal of avoiding IP processing is used in the IP / ΑΤΜ architecture (described in Proceedings of Gigabit NetWork Workshop, Boston, April 1995; and in Proceedings of ACM SIGCOMM '95, pp. 49-58, Cambridge, Massachusetts, August 1995), where an ATM back matrix connects multiple row cards and direction cards. IP processing elements placed in directional cards process IP headers. When a packet stream arrives, only the first IP header is checked and other packets are routed along the same path as the first packet. The main purpose of these abbreviations seems to be the amortization of the cost of IP processing of large numbers of packets.

IP router designs can use specialty hardware to perform IP processing, as is the case with the IBM router (described in Journal of High Speed Networks 1 (4), 281-288, 1993). This may be an inflexible solution. Any changes to the IP format or protocol would render such constructs inoperable. The flexibility of the software and the rapid increase in performance of general-purpose processors make such solutions advantageous.

Another hardware approach is to use CAM to perform directional searches (described in Proceedings of the Conference on Computer Communications (IEEE Infocom), Vol. 3, pp. 1382-1391, San Francisco 1993). This is a quick but expensive solution.

BBN is currently building a pair of multi-gigabit routers that use general-purpose processors as sending means. So far it was about it

-5published little information. However, the idea seems to be to use Alpha processors as the sending means and perform all IP processing in the software. Gigabit networking, Addison-Wesley, Reading, Massachusetts 1993 shows that it is possible to perform IP processing in no more than 200 instructions, assuming directional caching intervention. Alpha's secondary cache is used as a large LRU (least recently used) cache for destination addresses. This diagram assumes sufficient space in the operating patterns. With little space, successful caching searches would decrease too much and performance would decrease.

Therefore, it is an object of the present invention to provide an improved method and system of IP routing for performing full routing for each IP packet up to gigabit speeds, the method and system overcoming the above-mentioned disadvantages.

Another goal is to increase the speed of direction finding with a conventional microprocessor.

Another goal is to minimize search time in the send table.

Another further object of the present invention is to provide a data structure that fits entirely into the cache memory of a conventional microprocessor.

As a result, memory accesses will be of an order of magnitude faster compared to when the data structure must consist of a memory that, for example, consists of a relatively slow DRAM.

SUMMARY OF THE INVENTION

These goals are achieved by the IP directional lookup method in the direction table, containing prefixes of any length with associated jump information to determine where to send IP datagrams, which includes the steps:

-6 memorizing the direction table representation memory means in the form of a complete prefix tree defined by the prefixes of all direction table entries, supplemented so that each node has either no or two successors, all successors added being outputs with the same jump information as it has the next predecessor with information about the next jump, or an undefined jump, if no such predecessor exists, storing in said memory means a representation of the bit vector containing the section data through the prefix tree at the current depth with one bit per possible node at the current depth is set to 1, if there is a node in the prefix tree, memorizing to the above-mentioned memory means the array of first-level pointers for the right heads, including indexes to the following jumps table, and for the root heads, including indexes to the volume in dividing said bit vector into bit masks of a certain length, storing into said memory means a field of code words, each of which encodes a row index to the map table and a relative pointer pointer, storing into said memory means a base address field a location corresponding to the first index portion of an IP address in the codeword field, accessing a map portion of the map table at a location that corresponds to a column index portion of an IP address, and a codeword row index portion of the map table the index portion of the IP address in the base address field, and the access to the pointer at a location that corresponds to the base address plus the relative pointer of the codeword pointer plus the map portion of the map table in the pointer field,

- the principle being that the step of storing into said memory means of representing possible bit masks in the map table comprises the step of storing representations of possible bit masks having the property that any bit interval whose length is equal to two and starts at the bit index, which is a multiple of the same power of two, either contains all zeros or has the lowest bit set to 1.

If the pointer is an index to the next-level bundle, the method of the invention includes the next step of accessing the second-level bundle to find the pointer in the second-level bundle pointers for the right heads, including the index to the next jump table, and for the root heads, including the index k third-level volume.

If the pointer in the second-level bundle directional array is an index to the third-level bundle, the method of the invention includes a further step of accessing the third-level bundle to find the pointer in the third-level bundle directional array, including indexes to the next jump table.

If a bundle contains 1 to 8 heads, the bundle is a thin bundle and is represented by an 8-bit head index field and eight 16-bit pointers, if the bundle contains 9 to 64 heads, the bundle is a dense bundle and is represented analogously to the first level if the bundle it contains 65 to 256 heads, the bundle is a very dense bundle and is represented analogously to the first level.

Further, the invention provides a system for retrieving IP directions in a routing table, including as prefixes of any length with associated next hop information in the next hop table to determine where IP datagrams are to be sent, a routing table in the form of a complete prefix tree defined by prefixes all items in the direction table, with each node having either no or two successors, with all successors added being outputs with the same next jump information as the next predecessor with the next jump information, or an undefined jump if there is no such predecessor,

-8 a representation of the bit vector including the section data through the prefix tree at the current depth with one bit per possible node at the current depth, which bit is set to 1 if there is a node in the prefix tree a table of subsequent jumps, and for root heads, including indexes to the next-level bundle, said bit vector divided into bit masks of a certain length, a map table containing a representation of possible bit masks, codeword fields each coding a row index to the map table; a pointer pointer, and a base address field in which possible bit masks have the property that any bit interval whose length is an even power of two and starts at a bit index that is a multiple of the same power of two, either contains all zeros or has the lowest bit set to 1.

The next-level bundle is the second-level bundle, represented by the second-level bundle pointer field for the right heads, including indexes to the next jump table, and for the root heads, including the indexes to the third-level bundle.

The third-level bundle is represented by the array of third-level bundle pointers, including indexes to the next jump table.

The system is a data structure that can represent large directional tables in a very compact form and that can be searched quickly using a small number of memory links.

The invention is explained in more detail in the drawings and the advantages and features of the preferred embodiments of the invention will be described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic view of a router design, wherein 3 is the sending means, 1 and 2 is the interface, and 4 is the network processor.

Fig. 2 is an illustrative view of a binary tree spanning the entire IP address space,

-9Obr. 3 is an illustrative view of directional items defining ranges of IP addresses,

Fig. 4 is an illustrative view of the step of extending the prefix tree to complete; FIG. 5 is an illustrative view of three levels of data structure according to the present invention;

Fig. 6 is an illustrative view of a section of a prefix tree at depth 16;

Fig. 7 is an illustrative view of first level data structure search,

Fig. 8 is a table illustrating send table data constructed from different directional tables;

Fig. 9 is a table illustrating processor and cache data,

Fig. 10 is a graph showing the distribution of search times for Alpha 21164, and

Fig. 11 is a graph showing the distribution of search times for a Pentium

Pro.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, the router structure comprises a plurality of network-bound interfaces 1, network-outbound interfaces 2, sender means 3, and a network processor 4, all interconnected by the interconnect structure 5. the means 3 in turn determine to which outwardly directed interface 2 the packet is to be sent. This information is sent back to the internal bound interface 1, which sends a packet to the outgoing interface 2. The only task of the sending means 3 is to process the packet headers. All other tasks such as sharing routing protocols, reserving backups (resources), handling packets that require special attention, and other administrative tasks are handled by the network processor 4.

Each transmission means 3 uses a local version of the direction table, the send table, downloaded from the network processor 4 and stored in the memory means of the transmission means 3 to make their directional decisions. It is not necessary to download a new send table for each directional update. Directional updates may be frequent, but as directional protocols require some time to converge, the send tables may become slightly outdated and need no change more than once per second (described in the Stanford University Fast Routing Workshop) and switching), December 1996; http: // tinytera.stanford.edu/Workshop_Dec96/).

The network processor 4 needs a dynamic routing table designed to quickly update and generate the send tables. On the other hand, the send tables can be optimized for search speed and may not be dynamic.

To minimize search time, two parameters, the number of memory accesses required during the search, and the size of the data structure, must be minimized simultaneously in the data structure in the send table.

Reducing the number of memory accesses needed during a search is important because memory accesses are relatively slow and usually form a narrow profile of search procedures. If the data structure can be sufficiently reduced, it can fit entirely into the cache of a conventional microprocessor. This means that memory accesses will be of an order of magnitude faster than if the data structure must consist of a memory consisting of a relatively slow DRAM, as is the case with Tree Patients.

If the send table does not fit all into the cache, it is still advantageous if a large portion of the table can remain in the cache. The layout in the traffic patterns will keep the most frequently used parts of the data structure cached, so most searches will be fast. In addition, a fast SRAM can now be used for a small external device

-11 memory. SRAM is expensive and the more expensive the faster it is. At a given price, SRAM may be faster if less is needed.

As secondary design objectives, the data structure should need little instruction during the search and keep entities as naturally organized as possible, avoiding the use of expensive instructions and cumbersome bit selection operations.

In order to determine the quantitative parameters of the data structure design, several large directional tables have been examined, as will be described below. In these tables, there are around 40,000 different directional items. If the following jumps are the same, the rest of the directional information is also the same, and thus all directional items that specify the same next jump can share the directional information. The number of different successive hops in the router routing table is limited by the number of other routers or host computers that can be reached by one hop, so it is not surprising that these numbers may be small even for large heterogeneous routers. However, if the router is connected to, for example, a large ATM network, the number of subsequent jumps may be much higher.

In this embodiment, the send table data structure is designed to accommodate 2 ¹⁴ or 16K different subsequent jumps, which would be sufficient for most cases. If there are less than 256 different subsequent jumps, so that the index to the following jumps table can be memorized in a single byte, the send tables described herein may be modified in another embodiment to occupy substantially less space.

The send table is basically a tree with three levels. One level scan requires one to four memory accesses. As a result, the maximum number of memory accesses is twelve. However, with conventional routing tables, the vast majority of searches require only one or two levels to be crawled, so the number of memory accesses is likely to be eight or less.

In order to understand the data structure, consider a binary tree 6 that spans the entire IP address space shown in FIG. 2. Its depth is 32 and the number of outputs is ³² , one for each possible IP address. Directional item prefix

The -12 table defines a path in the tree that ends at a node. All IP addresses (outputs) in a subtree that begins at this node should be routed according to this routing entry. In this way, each routing table entry defines a range of IP addresses with the same routing information.

If several routing entries cover the same IP addresses, the longest match rule applies; this indicates that the routing entry with the longest matching prefix should be used for the given IP address. This situation is illustrated in FIG. 3; the directional entry el is covered by e2 for addresses in the range r.

The send table is a representation of the binary tree 6, spanned by all directional items, of the prefix tree 7. The prefix tree is required to be complete, i. j. so that each node in the tree has either two or no successors. Nodes with a single successor must extend to have two successors; the successors added in this way are always outputs and their information about the next jump will be the same as the next jump information of the next predecessor with the next jump information or the "undefined" next jump if there is no such predecessor.

This procedure, illustrated in FIG. 4, increases the number of nodes in the prefix tree 7, but allows a small send table to be constructed. However, it is not necessary to actually construct a prefix tree to construct a send table. The prefix tree is used to simplify the description. The send table can be constructed in a single run across all directional items.

The routing file divides the IP address space into IP address files. The problem of finding the right directional information is similar to the problem of the interval set membership problem (described in SIAM Journal on Computing 17 (1), 1093-1102, December 1988). In this case, each interval is defined by a node in the prefix tree, and therefore has properties that can be used to compress the send table. For example, each range of IP addresses has a length that is a power of two.

As shown in FIG. 5, level one of the data structure covers the prefix tree to a depth of 16, level two covers the depths of 17 to 24, and level three of the depths of 25 to 32.

-13Wherever a part of the prefix tree extends below level 16, the volume at level two describes that part of the tree. Similarly, tier three volumes describe portions of the prefix tree that are deeper than 24. A search of any level of the data structure results in either an index to a table of subsequent jumps or an index to a volume field for the next level.

For example, at level 1 of the data structure of FIG. 5 is a sectional view of a prefix tree 7 in the depth of cut 16 is stored in the bit vector with one bit per possible node at the depth of 16 is required, therefore 2 ¹⁶ bits = 64 kilobits = 8 kilobytes. To find the bit corresponding to the initial portion of the IP address, the upper 16 bits of that address are used as an index to the bit vector.

If there is a node in the prefix tree at depth 16, the corresponding bit in the vector is set to 1. Also, if the tree has an output at a depth less than 16, the lowest bit in the interval covered by that output is set to 1. All other bits are zero. Thus, the bit in the bit vector may be one that represents the fact that the prefix tree continues below the slice; a root head (bits 6, 12 and 13 in Fig. 6), or one that represents an output at a depth of 16 or less; right head (bits 0, 4, 7, 8, 14 and 15 in Fig. 6), or zero, which means that this value is a member of the range covered by the output at a depth of less than 16 (bits 1, 2, 3, 5 9, 10 and 11 in FIG. 6). These members have the same following jump as the highest head, lower than the member.

For the right heads, the index to the following jumps table must be remembered. Members will use the same index as the highest head, lower than the member. For root heads, the level-two index to the corresponding subtree must be remembered. The head information is stored in 16-bit pointers stored in the array. The two bits of the pointer encode what kind of pointer is, and the remaining 14 bits are either indexes to the next hop table or to a field containing two-level bundles.

In order to find the correct pointer, the bit vector is divided into bit masks with a length of 16 and these are 2 ¹² = 4096. Further, the position of the pointer in the array is obtained by adding three

- 14entits: base index, 6-bit relative indicator and 4-bit relative indicator. The base index plus the 6-bit relative pointer determines where the pointers corresponding to a particular bit mask are remembered. The 4-bit relative pointer specifies which pointer to select from. Fig. 7 illustrates how these entities are found. The following paragraphs deal with this procedure.

Because bit masks are generated from a complete prefix tree, not all 16-bit combinations are possible. The non-zero bit mask of length 2n may be any combination of two bit masks of length n or a bit mask of value 1. Let a (n) be the number of possible non-zero bit masks of length 2 ⁿ . and (n) is defined recurrently and (0) = 1, and (n) = 1 + and (n-1) ²

Thus, the number of possible bit masks with a length of 16 is a (4) + 1 = 678, where the unit is added because the bit mask may be zero. Thus, an index to an entry table for each bit mask only needs 10 bits.

Such a table, the map table, is held to map the bit numbers in the bit mask to 4-bit relative pointers. This relative indicator specifies how many pointers to skip to find the one we want, so it equals the number of bits set to 1 less than the bit index. These relative indicators are the same for all dispatch tables, no matter what values the pointers might have. The map table is constant, it is generated once and for all.

Possible bit masks have the property that any bit interval whose length is an even power of two and starts at a bit index that is a multiple of the same power of two, either 1) contains all zeros, or 2) has the lowest bit set to 1.

Mapping from bit mask and bit to relative pointer provided by the map table, along with prefix extensions that make the prefix tree complete and

-15Letting mapping is the key to achieving a small send table size.

True bit masks are not needed and instead of a bit vector we hold an array of 16-bit code words consisting of a 10-bit index to the map table plus a 6-bit relative pointer. The 6-bit relative pointer covers up to 64 pointers, so one base index per four code words is required. There can be a maximum of 64K pointers, so base indexes need to be a maximum of 16 bits (2 ¹⁶ = 64K).

The following steps in the pseudocode of the procedure shown in FIG. 7, are needed to search the first level of the data structure where the codeword field is called "code", the base address field is called "base", ix is the first index part of the IP address in the codeword field, "bit" is the column index part of IP "maptable", "this is the row index part of the codeword into the map table," bix "is the second index part of the IP address into the base address field, and" pix "is the pointer to the field of pointers including indexes to the table following jumps, as well as indexes to the volume at level two.

ix: = top 12 bits of IP address bit: = bottom 4 of the top 16 bits of the IP address codeword: = code [ix] ten: = ten bits of code word six: = six bits of code word bix: = top ten bits of IP pix: = base [bix] + six + maptable [ten] pointer: = levell_pointers [pix]

Thus, only a few bit selections, field references, and additions are needed. No multiplication or division instructions are required except for internal multiplication when fields are indexed.

A total of 7 bytes are needed to search the first level: a two-byte codeword, a two-byte base address, one byte (actually 4 bits) in the map table, and finally a two-byte pointer. size

-16 the first level is 8 kilobytes for the codeword field, 2 kilobytes for the base index field, plus the number of pointers. The 5.3 kilobytes needed for the map table are shared among all three levels.

When the bit mask is zero or has a single bit set to 1, the pointer must be an index to the following jumps table. Such pointers can be encoded directly into the codeword and thus the map table does not need to include entries for bit masks one and zero. The number of map table items is therefore reduced to 676 (indexes 0 to 675). When ten bits in the code word (the "one" above) is greater than 675, the code word represents a direct index to the table of subsequent jumps. Six bits of the codeword are used as the lowest 6 bits in the index and (ten - 676) are the upper bits of the index. This encoding allows a maximum of (1024 - 676) x 2® = 22272 indexes of the following jumps, which is more than 16K for which we are designing. This optimization eliminates three memory references when the directional item is located at a depth of 12 or higher, and substantially reduces the number of pointers in the pointer array. The price is one comparison and one conditional branch.

Mapping is included in the following data and features in C programming language.

An important feature of this code is the mapping that it provides from a single bit mask to a field of relative pointers.

Variations such as permutation of "mtable" (and "mt") will provide the same mapping. Also, other ways of representing an array of relative pointers, such as two 32-bit words instead of four 16-bit words.

/ * map table * / #define MAPVECLEN 4 typedef uint16 MAPVEC [MAPVECLEN];

-17typedef MAPVEC MCOMPACT;

MCOMPACT mt [TMAX];

/ * mt is a map table that is used during searches, initialized from mtable, which is used during construction * / typedef struct mentry {uintl 6 mask; / * 16-bit pattern (LSB is always set to 1! 7 uint16 only; / * 8-bit only (value 1-16) 7

MAPVEC map; / * 16 4-bit relative pointers in groups of four 7} MENTRY, * MP;

void mentomcompact (MENTRY * from, MCOMPACT * to) / * takes part of the map from "from" and inserts it into "to 7 {

int i;

for (i = 0; i <MAPVECLEN; i ++) {(* to) [i] = from-> map [i];

}}

extern void mtable_compact () / * initializes mt from mtable 7 {

register int i;

for (i = 0; i <TMAX; i ++) {ment2mcompact (& mtable [i], & mt [i]);

}}

-18Levels two and three data structures consist of bundles. The bundle covers a subtree with a height of 8 and can contain a maximum of ²⁸ = 256 heads. The root head at level n-1 points to a bundle at level n.

There are three types of bundles depending on how many heads the imaginary bit vector contains. If there are up to 8 heads, the volume is sparse and is represented by an array of 8-bit head indexes plus eight 16-bit pointers; 24 flats in total.

up to 64 heads, the bundle is dense. It is represented analogously to level 1 except for the number of base indexes. The difference is that only one base index is needed for all 16 code words, because 6-bit relative pointers can cover all 64 pointers. A total of 34 bytes are needed, plus 18 to 128 bytes for signposts.

up to 256 heads, the bundle is very dense. It is represented analogously to level 1. 16 code words and 4 base indexes give a total of 40 bytes. In addition, 65 to 256 pointers require 130 to 512 bytes.

Dense and very dense bundles are searched analogously to the first level.

The thin volumes are searched by a specially designed binary search procedure for 8 elements. This is significantly faster than linear search and binary general search. In addition, this search can be implemented without using conditional jumps on processor architectures that have conditional shift instruction.

/ * lookup lookup function * / stand inline uint16 findsparse (SPARSECHUNK * chu, uint32 val) / * chu -> vals is a sorted array of 0 ... 7 8-bit chu values -> rinfo is a matching array of 0 ... The 7 pointers val is the search key

-19 {uint8 * p, * q;

p = q = & (chu → vals [0]);

P ^{+ =} (* (P + 3)> val) 2;

P ⁺ = (* (P + 1)> val) 11;

p + = (* p> val);

return (chu-> rinfo [p-q]);

}

The dense and very dense bundles are optimized analogously to level 1 as described above. In sparse bundles, two successive heads can join and represent the lower one if the subsequent jumps are the same. When deciding whether a bundle is sparse or dense, this joining is considered, so that the bundle is considered sparse when the number of connected heads is 8 or less. Many of the outputs that have been added to make the tree complete will be sorted and will have the same following jumps. The heads corresponding to such outputs are joined together in thin volumes.

This optimization shifts the volume distribution from larger, dense bundles towards smaller, thin bundles. For large tables, the size of the send table is typically reduced by 5 to 15 percent.

The data structure can adapt to a significant increase in the number of directional items. There are two limitations in this proposal.

1. The number of volumes of each species is limited to 2 ¹⁴ = 16384 per level.

Table 1 shows that it is about 16 times more than currently used. If this threshold is ever exceeded at all, the data structure can be modified so that the pointers are encoded differently to provide more space for the indexes, or by increasing the pointer size.

2. The number of pointers at levels two and three is limited by the size of the base indexes.

The current implementation uses 16-bit base indexes and can bear a growth factor of 3 to 5. If this threshold is exceeded, it is easy to increase the size of the base pointers to three bytes. The bundle size is then increased by 3 percent for dense bundles and 10 percent for very dense bundles. Thin volumes are not affected.

It is clear that the data structure can adapt to the large increase in the number of directional items. Its size will grow almost linearly with the number of directional items.

Several IP routing tables were collected to examine the effectiveness of the send tables. Internet routing tables are currently available on the website for the Internet Performance Measurement and Analysis (IPMA) project (http://www.ra.net/statistics/) and were previously made available to the now expired Routing Arbiter ( Directional arbiter) project (http://www.ra.net/statistics/). The collected routing tables are daily snapshots of the routing tables used at various large Internet interconnection points. Some of the directional items in these tables contain several subsequent jumps. In this case, one of them was randomly selected as the next jump that was used in the send table.

Table 1 in FIG. 8 shows data on dispatch tables constructed from different direction tables. For each location, it shows data and results for the routing table that generated the largest send table. The "Directional Items" column means the number of directional items in the Directional Table, and "Subsequent Jumps" is the number of different successive jumps found in the Table. “Outputs” means the number of outputs in the prefix tree after adding outputs to become complete.

The "construction time" in Table 1 is the time required to generate a send table from a direction table representation by a binary tree in memory. These times were measured on 333 MHz Alpha 21164 under the DEC OSF1 operating system. The following columns show the total number of thin, dense and very dense

-21 volumes in the generated table, followed by the number of volumes at the lowest level of the data structure.

From Table 1 it is clear that new send tables can be generated quickly. At a regeneration frequency of one Herz, less than one tenth of Alpha capacity is consumed. As described above, regeneration frequencies higher than 1 Hz are not necessary.

The larger tables in Table 1 do not fit completely into the 96 kilobytes of secondary Alpha cache. However, it is possible to have a small, very fast SRAM in the third-level cache for those portions that do not fit in the secondary cache, thereby reducing the cost of non-intervention in the secondary cache. With enough space in the traffic patterns, most memory references would go to the secondary cache.

An interesting finding is that the size of these tables is comparable to the size that only the prefixes in the array would need to be remembered. For larger tables, no more than 5.6 bytes per prefix are required. More than half of these apartments are consumed by signposts. In the Sprint table there are 33469 pointers that require more than 65 kilobytes of memory. It is clear that further reductions in the size of the send table could be made by reducing the number of pointers.

Measurements with the search subroutine were performed with the C function compiled with the GNU C-compiler gcc compiler (described in Using and porting gnu cc. Manual, Free Software Foundation, November 1995, ISBN 1- The reported times do not include function calls or memory access to the following jumps table, gcc generates code that uses approximately 50 Alpha instructions to search one level of data structure at worst. On Pentium Pro gcc generates code that uses 35 to 45 instructions per level in the worst case.

The following function in the C-code shows the code of the search function used in the measurements.

-22The level 1 codeword field is called "int1" and the base index field is "basel." Level 1 pointers are remembered in the "htabl" field.

The volumes are remembered in the fields "cis", "cid", "cidd", where i is the level.

Base addresses and pointers for dense and very dense volumes are remembered in the "baseid", "baseidd" and "htabid", "htabidd" fields.

/ * search function for sending table * / # include “conf.h” # include “forward.h” # include “mtentry.h” # include “mtable.h # include“ bit2index.h ”#define TABLE_LOOKUP # include“ sparse .h # include “timing.h # include” lookup.h / * these macros only work if ip is a 32-bit unsigned int (uint32) * / #define EXTRACT (start, bits.ip) (((ip) «(Start))» (32 - (bits)) #define GETTEN (m) (((m) «22)» 22) #define GETSIX (m) ((m) »10) #define bit2o (ix, bit ) ((mt [(ix) j [(bit) »2)» (((bit) & 0x3) «2)) & Oxf) / 'lookup (ipaddr) - Direction Table Item Index for ipaddr 7

-23unsigned int lookup {uint32 ipaddr} {

uint32 ix; uint32 code; int32 diff; uint32 ten; uint32 six; int32 nhop; uint32 off; uint32 hbase; uint32 pntr; int32 kind; uint32 chunk; uint8 * p, * q; uint32 key;

/ * index to code field * / / * 16-bit code word 7 / * unlike TMAX 7 / * index to mt 7 / * six “extra” bits from code * / / * pointer to next jump7 / * relative pointer 7 / * base table for transformation table 7 / * input to transformation table7 / * type pntr 7 / * volume index 7 / * pointer to search thin volume 7 / * search key in thin volume 7 / * timed from * HERE * Ix = EXTRACT (0, 12, ipaddr); code = int1 [ix]; ten = GETTEN (code); six = GETSIX;

if ((diff = (ten-TMAX))> = 0) {nhop = (six | (diff «6)); goto end;

} off = bit2o (ten, EXTRACT (12,4 ipaddr));

hbase = base1 [ix »2j;

pntr = htabl [hbase + six + off];

-24if ((kind = (pntr & 0x3))) {chunk = (pntr &2);

if (-kind) {if (-kind) {key = EXTRACT (16,8, ipaddr); p = q = c2s [chunk] .vals [0]);

if (* (p + 3)> key) {p + = 4;

};

while (* p> key) {

P ++;

};

pntr = c2s [chunkj.rinfo [p - q];

} else {ix = EXTRACT (16,4 ipaddr); code = c2dd [chunk] [ix]; ten = GETTEN (code); six = GETSIX;

if ((diff = (ten-TMAX))> = 0) {nhop = (six | (diff «6)); goto end;

} hbase = htab2ddbase [(chunk 2) | (ix 2 2)]; off = bit2o (ten, EXTRACT (20,4 ipaddr));

-25pntr = htab2dd [hbase + six + off];

}} else {ix = EXTRACT (16,4, ipaddr); code = c2d [chunk] [ix]; ten = GETTEN (code); six = GETSIX;

if ((diff = (ten-TMAX))> = 0) {nhop = (six | (diff «6)); goto end;

hbase = htab2dbase [chunk];

off = bit2o (ten, EXTRACT (16, 4, ipaddr));

pntr = htab2d [hbase + six + off];

} if ((kind = (pntr & 0x3))) {chunk = (pntr »2);

if (--kind) {if (—kind) {key = EXTRACT (24,8, ipaddr); p = q = c3s [chunk] .vals [0]); if (* (p + 3)> key) {p + = 4;

};

-26while (* p> key) {p ++;

};

pntr = c3s [chunk] .rinfo [p-q];

} else {ix = EXTRACT (24,4 ipaddr); code = c3dd [chunk] [ix]; ten = GETTEN (code); six = GETSIX;

if ((diff = (ten-TMAX))> = 0) {nhop = (six | (diff «6)); goto end;

} off = bit2o (ten, EXTRACT (28,4 ipaddr)); hbase = htab3ddbase [(chunk 2) | (ix 2 2)]; pntr = htab3dd [hbase + six + off];

}} else {ix = EXTRACT (24,4 ipaddr);

code = c3d [chunk] [ix];

ten = GETTEN (code);

six = GETSIX;

if ((diff = (ten-TMAX))> = 0) {nhop = (six | (diff «6)); goto end;

-27off = bit2o (the one, EXTRACT (28,4 ipaddr)); hbase = htab3dbase [chunk]; pntr = htab3d [hbase + six + ofQ;

}}

} nhop = (pntr »2);

end;

/ * timed after HERE! Return nhop;

}

It is possible to read the current value of the hour cycle counter on Alpha and Pentium Pro. This option was used to measure search time with high accuracy: one clock pulse is 5 nanoseconds at 200 MHz and 3 nanoseconds at 333 MHz.

Ideally, the entire send table would be cached, so searches would be performed with an undisturbed cache. This would emulate the behavior of the associated send resources. However, measurements have only been performed on common general-purpose workstations, and it is difficult to control the contents of the cache on such systems. The cache is disturbed whenever 1/0 is performed, there is an interruption, or when another process is starting. It is not even possible to print measurement data or read a new IP address from a file without disturbing the cache.

The method used performs each search twice and measures the search time for the second search. In this way, the first search is done with the cache cached and the second in the cache,

-28when all the necessary data was forced into the primary cache by the first search. After each pair of searches, the measurement data is printed and a new address is called, a procedure that cancels the cache again.

The second search will be faster than the search resource, because the data and instructions have moved to the primary cache, closest to the processor. In order to obtain an upper limit for the search time, additional time required for memory accesses to the secondary cache must be added to the measured times. To test all paths through the send table, the search time was measured for each item in the direction table, including items added to the complete tree extension.

The average search times cannot be derived from these attempts because a realistic traffic mix is unlikely to have a uniform probability of access to each directional item. In addition, deployment in traffic patterns will keep parts of the data structure that are frequently accessed in the primary cache and thus reduce the average search time. The performance criteria calculated below are conservative, because it is assumed that neither memory access will hit the primary cache and that the worst case execution time will always occur. Realistic search speeds will be higher.

Table 1 shows that there are very few volumes at level three of the data structure. This makes it likely that the vast majority of searches do not need to search more than two levels to find the next jump. Therefore, the additional time for memory accesses to the secondary cache is calculated for eight instead of the worst case of twelve memory accesses. If a significant proportion of the searches were to reach these few volumes, they would move to the primary cache and all twelve hits would become less expensive.

One experiment was performed on Alpha 21164 with a 333 MHz clock frequency; one cycle lasts 3 nanoseconds. Accesses to 8 kilobytes of primary fast

-29 caches are performed in 2 cycles, and accesses to the secondary 96 kilobytes cache require 8 cycles. See Table 2 in FIG.

9th

Fig. 10 shows the clock clock distribution that elapsed during the second Alpha search on the Sprint direction chart of January 1. The fastest observed searches require 17 hour cycles. This is the case when the code word at the first level directly encodes the index to the table of subsequent jumps. There are very few such directional items. However, since each such routing item covers many IP addresses, the actual traffic may contain many such destination addresses. Some searches require 22 cycles, which must be the same as the previous one. The experiments confirmed that when the clock cycle counter is read by two consecutive instructions, the difference is sometimes 5 cycles instead of the expected 0.

The following maximum in FIG. 10 is at 41 clock cycles, which is when the pointer found at the first level is an index to the table of subsequent jumps. Traditional Class B addresses fall into this category. The maxima at 52 to 53, 57, 62, 67 and 72 such correspond to finding a pointer after checking one, two, three, four or five values in a sparse bundle at level 2. Large maxima at 75 and 83 such exist because, for very dense bundles many bars are needed. A few observations above 83 correspond to the guidelines found after the scarcity of Level 3, probably due to changes at the time of implementation. Such changes can cause conflicts in the secondary cache or differences in the state of the concatenated instruction streams and the cache system before the search. The remainder of the observations above 100 clock cycles are caused by either such changes or unsuccessful attempts to hit the cache. 300 nanoseconds per search should suffice if all data is in the primary cache.

The difference between data access in the primary and secondary cache is 8 - 2 = 6 cycles. Thus, two levels of data search

-30 structures in the worst case require 8 x 6 = 48 hour cycles more than indicated in Figs. 10. This means a maximum of 100 + 48 = 148 cycles or 444 nanoseconds for the worst case search when 2 levels are sufficient. Thus, Alpha would be able to do at least 2.2 million directional searches per second with a send table in the secondary cache.

Another attempt was made on a Pentium Pro with a clock frequency of 200 MHz; one cycle lasts 5 nanoseconds. The primary 8 kilobytes cache has a 2-cycle wait time and the secondary 256 kilobytes cache has a 6-cycle wait time. See Table 2.

Fig. 11 shows the clock clock distribution that elapsed during the second search for the Pentium Pro with the same send table as for the Alpha 21164. The instruction sequence that invokes the clock cycle counter requires 33 clock cycles. When two invocations occur immediately in succession, the counter values differ by 33. For this reason, all reported times have been reduced by 33.

The fastest observed searches are at 11 clock cycles, which is approximately the same speed as the Alpha 21164. The maximum, corresponding to the case where the next jump index was found immediately after the first level, occurs at 25 clock cycles. The maxima corresponding to the sparse volume at level 2 are grouped side by side in a range of 36 to 40 hour cycles. The Pentium's different cache structure seems to handle better linear scans than the Alpha 21164's cache structure.

When the second-tier volumes are dense and very dense, the search requires 48 and 50 cycles. There are several other irregular peaks up to 69 above which there are very few observations. Clearly, 69 cycles (345 nanoseconds) are sufficient to perform a search when all data is in the primary cache.

The difference in access time between primary and secondary cache is 20 nanoseconds (4 cycles). Search Time for Pentium Pro,

-31 when two levels need to be examined, then in the worst case is 69 + 8 x 4 = 101 cycles or 505 nanoseconds. Pentium Pro can do at least 2.0 million directions per second searches with a send table in the secondary cache.

It should be understood that the present invention provides an improved method and system of IP directional search that fully meets the above objectives and advantages. Although the invention has been described in connection with specific embodiments thereof, those skilled in the art will appreciate alternatives, modifications and changes thereto.

In the embodiment described above, the search function is implemented in C programming language. It will be clear to a person skilled in the art that other programming languages can be used. Alternatively, the search function can be implemented in hardware using standard methods of digital construction, as will also be apparent to those skilled in the design of hardware.

For example, the invention can be used for computer system configurations other than Alpha 21164 or Pentium Pro systems, other prefix tree cuts, different tree counts, other map table representation methods, and other code word encoding methods.

In addition, the invention can be used for direction finding firewall.

Claims (7)

PATENT CLAIMS A method of IP routing searches in a routing table comprising, as items of any length prefixes, associated with the following jump information, to determine where to send IP datagrams, comprising the steps of: storing in the memory means of the direction table representation in the form of a complete prefix tree (7) defined by the prefixes of all direction table entries, supplemented so that each node has either no or two successors, all successors added being outputs with the same jump information, such as the nearest predecessor having information about the next jump, or an undefined jump, if there is no such predecessor, storing in said memory means a representation of the bit vector (8) containing the section data through the prefix tree (7) at the current depth (D) a bit to a possible node at the current depth, which bit is set to 1 if there is a node in the prefix tree (7), memorizing to said first-level pointer array memory resources, including indexes to the following jumps table, and for the root head, including index in the next level, dividing said bit vector (8) into bit masks of a certain length, storing into said memory means a field of code words, each of which encodes a row index to the map table and a relative pointer pointer, storing into said memory means a base field address access to the codeword in place that corresponds to the first index part (ix) of the IP address in the codeword field, access to the item portion of the map table in place that corresponds to the column index part (bit) of the IP address and the row index part (ten) Codeword in the map table -33 accessing a base address at a location that corresponds to a second index portion (bix) of an IP address in a base address field, and accessing a pointer at a location that corresponds to a base address plus a relative pointer (six) of the codeword pointer plus pointers, characterized in that the step of memorizing said memory means of representing possible bit masks in the map table comprises the step of memorizing a representation of possible bit masks having the property that any bit interval whose length is equal to two and starts at the bit index, which is a multiple of the same power of two, either contains all zeros or has the lowest bit set to 1. The method of claim 1, wherein, if the pointer is an index to the next-level bundle, the next step includes accessing the second-level bundle to find the pointer in the second-level bundle directional array for the right heads, including the index to the following jumps table , and for the root heads, including the index to the third level bundle. 3. The method of claim 2, wherein if the pointer in the second-level bundle directional array is an index to a third-level bundle, it comprises the further step of accessing the third-level bundle to locate the pointer in the bundle directional array. level three, including indexes to the table of the next jumps. Method according to any one of the preceding claims, characterized in that if the bundle contains 1 to 8 heads, the bundle is a thin bundle and is represented by an 8-bit head index field and eight 16-bit pointers if the bundle contains 9 to 64 heads, the bundle is a dense bundle and is represented analogously to the first level, -34a how the bundle contains 65 to 256 heads, the bundle is a very dense bundle and is represented analogously to the first level. 5. An IP routing system in a direction table, comprising as prefixes of any length with associated next hop information in the next hop table to determine where to send the IP datagrams a direction table in the form of a complete prefix tree (7), defined by prefixes of all direction table entries, with each node having either no or two successors, all successors added being outputs with the same next jump information as the next predecessor with the next jump information, or an undefined jump if there is no such predecessor , representing a bit vector (8) including section data through the prefix tree (7) at the current depth (D) with one bit per possible node at the current depth, which bit is set to 1 if there is a node in the prefix tree ( 7), a field of pointers for right heads, including indexes to the table below and for the root heads, including indexes to the next-level bundle, said bit vector (8) divided into bit masks of a certain length, a map table containing a representation of possible bit masks, an array of code words each coding a row index to the map table and a relative pointer pointer, and a base address field, characterized in that the possible bit masks have the property that any bit interval whose length is an even power of two and starts at a bit index that is a multiple of the same power of two, either contains the same or has the lowest bit set to 1. The system of claim 5, wherein the next level bundle is a second level bundle represented by an array of pointers. -35the second-level volume for the right-hand head, including indexes to the following jumps table, and for the root-head, including the indexes to the third-level bundle. The system of claim 6, wherein the third-level bundle is represented by an array of third-level bundle pointers, including indexes to the table of subsequent jumps.