SG134187A1 - Stacked wafer for 3d integration - Google Patents
Stacked wafer for 3d integrationInfo
- Publication number
- SG134187A1 SG134187A1 SG200600330-5A SG2006003305A SG134187A1 SG 134187 A1 SG134187 A1 SG 134187A1 SG 2006003305 A SG2006003305 A SG 2006003305A SG 134187 A1 SG134187 A1 SG 134187A1
- Authority
- SG
- Singapore
- Prior art keywords
- wafer
- copper pads
- forming
- integration
- stacked wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
Abstract
A method of forming a stacked wafer device comprising the steps of : providing a first wafer; forming a plurality of copper pads in a first surface of the first wafer; forming at least one embedded vertical connector in the first wafer in isolation from the copper pads of the first wafer; providing a second wafer; forming a plurality of copper pads in a first surface of the second wafer, the placement of the copper pads to coincide with the location of the copper pads of the first wafer; forming at least one embedded vertical connector in the second wafer in isolation from the copper pads of the second wafer; bringing the first surfaces of the wafers into contact, so as to contact the copper pads; applying a force to the wafers at a pre-determined pressure and at a pre-determined temperature until the copper pads are bonded, and so forming the stacked wafer device from the bonded first and second wafer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG200600330-5A SG134187A1 (en) | 2006-01-13 | 2006-01-13 | Stacked wafer for 3d integration |
| CN2006101018991A CN101000880B (en) | 2006-01-13 | 2006-07-14 | Stacked wafer for 3-D integration |
| TW096101429A TWI441308B (en) | 2006-01-13 | 2007-01-15 | Stacked wafer for 3d integration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG200600330-5A SG134187A1 (en) | 2006-01-13 | 2006-01-13 | Stacked wafer for 3d integration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG134187A1 true SG134187A1 (en) | 2007-08-29 |
Family
ID=38692787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200600330-5A SG134187A1 (en) | 2006-01-13 | 2006-01-13 | Stacked wafer for 3d integration |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN101000880B (en) |
| SG (1) | SG134187A1 (en) |
| TW (1) | TWI441308B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299736B2 (en) | 2014-03-28 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
| KR102352677B1 (en) * | 2014-08-27 | 2022-01-17 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| JP6387850B2 (en) * | 2015-02-10 | 2018-09-12 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| CN106653720A (en) * | 2016-12-30 | 2017-05-10 | 武汉新芯集成电路制造有限公司 | Mixed bonding structure and mixed bonding method |
| CN109384192B (en) * | 2017-08-04 | 2020-11-06 | 上海珏芯光电科技有限公司 | Microsystem packaging module and manufacturing method thereof |
| CN108541131B (en) * | 2018-05-30 | 2020-04-17 | 业成科技（成都）有限公司 | Circuit board connecting structure and display device using same |
| KR102482697B1 (en) | 2018-11-30 | 2022-12-28 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Bonded memory device and manufacturing method thereof |
| KR102618755B1 (en) | 2019-01-30 | 2023-12-27 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Hybrid bonding using dummy bonded contacts and dummy interconnects |
| EP3847698A4 (en) | 2019-01-30 | 2023-07-12 | Yangtze Memory Technologies Co., Ltd. | Hybrid bonding using dummy bonding contacts |
| KR102601225B1 (en) | 2019-04-15 | 2023-11-10 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Integration of 3D NAND memory devices with multiple functional chips |
| CN110854116A (en) * | 2019-10-28 | 2020-02-28 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional heterogeneous integrated chip and preparation method thereof |
| US11599299B2 (en) | 2019-11-19 | 2023-03-07 | Invensas Llc | 3D memory circuit |
| TW202307717A (en) | 2021-08-04 | 2023-02-16 | 義守大學 | Method and electronic device for configuring signal pads between three-dimensional stacked chips |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3646719B2 (en) * | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| JP4263953B2 (en) * | 2003-06-23 | 2009-05-13 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP3990347B2 (en) * | 2003-12-04 | 2007-10-10 | ローム株式会社 | Semiconductor chip, manufacturing method thereof, and semiconductor device |
-
2006
- 2006-01-13 SG SG200600330-5A patent/SG134187A1/en unknown
- 2006-07-14 CN CN2006101018991A patent/CN101000880B/en not_active Expired - Fee Related
-
2007
- 2007-01-15 TW TW096101429A patent/TWI441308B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| CN101000880A (en) | 2007-07-18 |
| CN101000880B (en) | 2010-08-25 |
| TWI441308B (en) | 2014-06-11 |
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