SG11202007146RA - Pack and unpack network and method for variable bit width data formats - Google Patents

Pack and unpack network and method for variable bit width data formats

Info

Publication number
SG11202007146RA
SG11202007146RA SG11202007146RA SG11202007146RA SG11202007146RA SG 11202007146R A SG11202007146R A SG 11202007146RA SG 11202007146R A SG11202007146R A SG 11202007146RA SG 11202007146R A SG11202007146R A SG 11202007146RA SG 11202007146R A SG11202007146R A SG 11202007146RA
Authority
SG
Singapore
Prior art keywords
pack
bit width
data formats
variable bit
width data
Prior art date
Application number
SG11202007146RA
Inventor
Ajay Ingle
Saurabh Kulkarni
Jun Ho Bahn
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11202007146RA publication Critical patent/SG11202007146RA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
SG11202007146RA 2018-03-01 2019-02-11 Pack and unpack network and method for variable bit width data formats SG11202007146RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/909,942 US20190272175A1 (en) 2018-03-01 2018-03-01 Single pack & unpack network and method for variable bit width data formats for computational machines
PCT/US2019/017440 WO2019168657A1 (en) 2018-03-01 2019-02-11 Pack and unpack network and method for variable bit width data formats

Publications (1)

Publication Number Publication Date
SG11202007146RA true SG11202007146RA (en) 2020-09-29

Family

ID=65628819

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202007146RA SG11202007146RA (en) 2018-03-01 2019-02-11 Pack and unpack network and method for variable bit width data formats

Country Status (6)

Country Link
US (1) US20190272175A1 (en)
EP (1) EP3759593B1 (en)
CN (1) CN111788553A (en)
BR (1) BR112020017825A2 (en)
SG (1) SG11202007146RA (en)
WO (1) WO2019168657A1 (en)

Family Cites Families (24)

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GB9509989D0 (en) * 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
US6381690B1 (en) * 1995-08-01 2002-04-30 Hewlett-Packard Company Processor for performing subword permutations and combinations
US6173366B1 (en) * 1996-12-02 2001-01-09 Compaq Computer Corp. Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage
US5933650A (en) * 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
GB2409064B (en) * 2003-12-09 2006-09-13 Advanced Risc Mach Ltd A data processing apparatus and method for performing in parallel a data processing operation on data elements
US9557994B2 (en) * 2004-07-13 2017-01-31 Arm Limited Data processing apparatus and method for performing N-way interleaving and de-interleaving operations where N is an odd plural number
US20070124631A1 (en) * 2005-11-08 2007-05-31 Boggs Darrell D Bit field selection instruction
US20070226469A1 (en) * 2006-03-06 2007-09-27 James Wilson Permutable address processor and method
JP5435241B2 (en) * 2007-04-16 2014-03-05 エスティー‐エリクソン、ソシエテ、アノニム Data storage method, data load method, and signal processor
US7783860B2 (en) * 2007-07-31 2010-08-24 International Business Machines Corporation Load misaligned vector with permute and mask insert
US7877571B2 (en) * 2007-11-20 2011-01-25 Qualcomm, Incorporated System and method of determining an address of an element within a table
US9086872B2 (en) * 2009-06-30 2015-07-21 Intel Corporation Unpacking packed data in multiple lanes
US20130042091A1 (en) * 2011-08-12 2013-02-14 Qualcomm Incorporated BIT Splitting Instruction
US9792117B2 (en) * 2011-12-08 2017-10-17 Oracle International Corporation Loading values from a value vector into subregisters of a single instruction multiple data register
US10061581B2 (en) * 2014-01-31 2018-08-28 Qualcomm Incorporated On-the-fly conversion during load/store operations in a vector processor
JP6253514B2 (en) * 2014-05-27 2017-12-27 ルネサスエレクトロニクス株式会社 Processor
US10489155B2 (en) * 2015-07-21 2019-11-26 Qualcomm Incorporated Mixed-width SIMD operations using even/odd register pairs for wide data elements
US9875214B2 (en) * 2015-07-31 2018-01-23 Arm Limited Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers
US10338920B2 (en) * 2015-12-18 2019-07-02 Intel Corporation Instructions and logic for get-multiple-vector-elements operations
US20170177351A1 (en) * 2015-12-18 2017-06-22 Intel Corporation Instructions and Logic for Even and Odd Vector Get Operations
US20170177359A1 (en) * 2015-12-21 2017-06-22 Intel Corporation Instructions and Logic for Lane-Based Strided Scatter Operations
US20170177362A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Adjoining data element pairwise swap processors, methods, systems, and instructions
US10289416B2 (en) * 2015-12-30 2019-05-14 Intel Corporation Systems, apparatuses, and methods for lane-based strided gather
US10191740B2 (en) * 2017-02-28 2019-01-29 Intel Corporation Deinterleave strided data elements processors, methods, systems, and instructions

Also Published As

Publication number Publication date
CN111788553A (en) 2020-10-16
EP3759593B1 (en) 2023-05-17
US20190272175A1 (en) 2019-09-05
BR112020017825A2 (en) 2020-12-29
EP3759593A1 (en) 2021-01-06
WO2019168657A1 (en) 2019-09-06

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