SG11201805489YA - Memory device, and data processing method based on multi-layer rram crossbar array - Google Patents
Memory device, and data processing method based on multi-layer rram crossbar arrayInfo
- Publication number
- SG11201805489YA SG11201805489YA SG11201805489YA SG11201805489YA SG11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA SG 11201805489Y A SG11201805489Y A SG 11201805489YA
- Authority
- SG
- Singapore
- Prior art keywords
- crossbar array
- memory device
- rram crossbar
- data processing
- processing method
- Prior art date
Links
- 238000003672 processing method Methods 0.000 title abstract 2
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Life Sciences & Earth Sciences (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Fuzzy Systems (AREA)
- Automation & Control Theory (AREA)
- Computer Hardware Design (AREA)
- Artificial Intelligence (AREA)
- Neurology (AREA)
- Computational Linguistics (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
Abstract
MEMORY DEVICE, AND DATA PROCESSING METHOD BASED ON MULTI-LAYER RRAM CROSSBAR ARRAY Embodiments of the present invention provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of 5 resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a Boolean value 1 or 0. Based on the foregoing setting, a Boolean operation is implemented by using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved. Fig. 5 10
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2016/071254 WO2017124237A1 (en) | 2016-01-18 | 2016-01-18 | Memory device and data-processing method based on multi-layer rram crossbar array |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201805489YA true SG11201805489YA (en) | 2018-07-30 |
Family
ID=59361091
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201805489YA SG11201805489YA (en) | 2016-01-18 | 2016-01-18 | Memory device, and data processing method based on multi-layer rram crossbar array |
Country Status (6)
Country | Link |
---|---|
US (1) | US10459724B2 (en) |
EP (1) | EP3389051B1 (en) |
JP (1) | JP6702596B2 (en) |
CN (1) | CN108475522B (en) |
SG (1) | SG11201805489YA (en) |
WO (1) | WO2017124237A1 (en) |
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US10878317B2 (en) * | 2017-09-11 | 2020-12-29 | Samsung Electronics Co., Ltd. | Method and system for performing analog complex vector-matrix multiplication |
IT201700108281A1 (en) * | 2017-09-27 | 2019-03-27 | Milano Politecnico | "RESOLUTION CIRCUIT FOR MATHEMATICAL PROBLEMS INCLUDING RESISTIVE ELEMENTS." |
US11189345B2 (en) * | 2018-01-22 | 2021-11-30 | Institute of Microelectronics, Chinese Academy of Sciences | Method for implementing logic calculation based on a crossbar array structure of resistive switching device |
JP7070190B2 (en) * | 2018-07-18 | 2022-05-18 | 株式会社デンソー | Neural network circuit |
US11170290B2 (en) | 2019-03-28 | 2021-11-09 | Sandisk Technologies Llc | Realization of neural networks with ternary inputs and binary weights in NAND memory arrays |
US11328204B2 (en) | 2018-07-24 | 2022-05-10 | Sandisk Technologies Llc | Realization of binary neural networks in NAND memory arrays |
US10643119B2 (en) * | 2018-07-24 | 2020-05-05 | Sandisk Technologies Llc | Differential non-volatile memory cell for artificial neural network |
US10643705B2 (en) | 2018-07-24 | 2020-05-05 | Sandisk Technologies Llc | Configurable precision neural network with differential binary non-volatile memory cell structure |
CN108763163B (en) * | 2018-08-02 | 2023-10-20 | 北京知存科技有限公司 | Analog vector-matrix multiplication circuit |
US11410025B2 (en) * | 2018-09-07 | 2022-08-09 | Tetramem Inc. | Implementing a multi-layer neural network using crossbar array |
US10489483B1 (en) * | 2018-09-21 | 2019-11-26 | National Technology & Engineering Solutions Of Sandia, Llc | Circuit arrangement and technique for setting matrix values in three-terminal memory cells |
CN109327219B (en) * | 2018-10-18 | 2022-05-03 | 中国科学院微电子研究所 | Memristor RRAM-based logic operation system |
US11636325B2 (en) | 2018-10-24 | 2023-04-25 | Macronix International Co., Ltd. | In-memory data pooling for machine learning |
CN109521995B (en) * | 2018-11-02 | 2023-05-12 | 上海交通大学 | Calculation method of logic operation device embedded in memristor array |
US11562229B2 (en) | 2018-11-30 | 2023-01-24 | Macronix International Co., Ltd. | Convolution accelerator using in-memory computation |
US11074318B2 (en) | 2018-12-14 | 2021-07-27 | Western Digital Technologies, Inc. | Hardware accelerated discretized neural network |
US11934480B2 (en) * | 2018-12-18 | 2024-03-19 | Macronix International Co., Ltd. | NAND block architecture for in-memory multiply-and-accumulate operations |
US11114158B1 (en) * | 2019-01-23 | 2021-09-07 | Tetramem Inc. | Reducing column switch resistance errors in RRAM-based crossbar array circuits |
US20200349217A1 (en) * | 2019-05-03 | 2020-11-05 | Micron Technology, Inc. | Methods and apparatus for performing matrix transformations within a memory array |
IT201900014688A1 (en) * | 2019-08-12 | 2019-11-12 | Univ Degli Studi Di Modena E Reggio Emilia | Reading method for Logic-in-Memory circuits and related circuit architecture |
WO2021034264A1 (en) * | 2019-08-22 | 2021-02-25 | Quantumciel Pte. Ltd. | Device, system and method for providing information security |
US10726331B1 (en) | 2019-08-26 | 2020-07-28 | International Business Machines Corporation | Neural network circuits providing early integration before analog-to-digital conversion |
US11568200B2 (en) | 2019-10-15 | 2023-01-31 | Sandisk Technologies Llc | Accelerating sparse matrix multiplication in storage class memory-based convolutional neural network inference |
US11625586B2 (en) | 2019-10-15 | 2023-04-11 | Sandisk Technologies Llc | Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays |
JP6818116B1 (en) * | 2019-11-22 | 2021-01-20 | ウィンボンド エレクトロニクス コーポレーション | Electronic devices and data processing methods using crossbar arrays |
US11657259B2 (en) | 2019-12-20 | 2023-05-23 | Sandisk Technologies Llc | Kernel transformation techniques to reduce power consumption of binary input, binary weight in-memory convolutional neural network inference engine |
CN111478703B (en) * | 2020-04-14 | 2023-08-22 | 中国人民解放军国防科技大学 | Memristor cross array-based processing circuit and output current compensation method |
US11397885B2 (en) | 2020-04-29 | 2022-07-26 | Sandisk Technologies Llc | Vertical mapping and computing for deep neural networks in non-volatile memory |
US11544547B2 (en) | 2020-06-22 | 2023-01-03 | Western Digital Technologies, Inc. | Accelerating binary neural networks within latch structure of non-volatile memory devices |
US11568228B2 (en) | 2020-06-23 | 2023-01-31 | Sandisk Technologies Llc | Recurrent neural network inference engine with gated recurrent unit cell and non-volatile memory arrays |
US11663471B2 (en) | 2020-06-26 | 2023-05-30 | Sandisk Technologies Llc | Compute-in-memory deep neural network inference engine using low-rank approximation technique |
US11544061B2 (en) * | 2020-12-22 | 2023-01-03 | International Business Machines Corporation | Analog hardware matrix computation |
CN114594819B (en) * | 2022-01-19 | 2023-12-05 | 之江实验室 | Circuit and method for adaptively adjusting operating voltage for tracking ferroelectric capacitor process |
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CN104124960B (en) * | 2014-06-20 | 2018-02-23 | 华中科技大学 | A kind of non-volatile boolean calculation circuit and its operating method |
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-
2016
- 2016-01-18 JP JP2018537499A patent/JP6702596B2/en active Active
- 2016-01-18 WO PCT/CN2016/071254 patent/WO2017124237A1/en active Application Filing
- 2016-01-18 CN CN201680058624.6A patent/CN108475522B/en active Active
- 2016-01-18 EP EP16885510.4A patent/EP3389051B1/en active Active
- 2016-01-18 SG SG11201805489YA patent/SG11201805489YA/en unknown
-
2018
- 2018-07-17 US US16/037,767 patent/US10459724B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20180321942A1 (en) | 2018-11-08 |
JP2019502225A (en) | 2019-01-24 |
EP3389051A4 (en) | 2019-01-09 |
CN108475522B (en) | 2020-12-15 |
US10459724B2 (en) | 2019-10-29 |
JP6702596B2 (en) | 2020-06-03 |
CN108475522A (en) | 2018-08-31 |
EP3389051A1 (en) | 2018-10-17 |
WO2017124237A1 (en) | 2017-07-27 |
EP3389051B1 (en) | 2020-09-09 |
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