SG10202005977TA - Integrated circuit device and method of manufacturing the same - Google Patents

Integrated circuit device and method of manufacturing the same

Info

Publication number
SG10202005977TA
SG10202005977TA SG10202005977TA SG10202005977TA SG10202005977TA SG 10202005977T A SG10202005977T A SG 10202005977TA SG 10202005977T A SG10202005977T A SG 10202005977TA SG 10202005977T A SG10202005977T A SG 10202005977TA SG 10202005977T A SG10202005977T A SG 10202005977TA
Authority
SG
Singapore
Prior art keywords
manufacturing
same
integrated circuit
circuit device
integrated
Prior art date
Application number
SG10202005977TA
Inventor
Choi Eunyeoung
Lee Suhyeong
Lee Yohan
Cho Yongseok
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202005977TA publication Critical patent/SG10202005977TA/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234Gate electrodes for transistors with charge trapping gate insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
SG10202005977TA 2019-08-27 2020-06-23 Integrated circuit device and method of manufacturing the same SG10202005977TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190104983A KR20210025244A (en) 2019-08-27 2019-08-27 Integrated circuit device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
SG10202005977TA true SG10202005977TA (en) 2021-03-30

Family

ID=74564703

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202005977TA SG10202005977TA (en) 2019-08-27 2020-06-23 Integrated circuit device and method of manufacturing the same

Country Status (6)

Country Link
US (1) US11502097B2 (en)
JP (1) JP2021034734A (en)
KR (1) KR20210025244A (en)
CN (1) CN112447758A (en)
DE (1) DE102020109802A1 (en)
SG (1) SG10202005977TA (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210028759A (en) * 2019-09-03 2021-03-15 삼성전자주식회사 Semiconductor devices
KR20210141239A (en) * 2020-05-15 2021-11-23 에스케이하이닉스 주식회사 Semiconductor memory device and manufacturing method thereof
KR20220042652A (en) * 2020-09-28 2022-04-05 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
JP2022139973A (en) * 2021-03-12 2022-09-26 キオクシア株式会社 Semiconductor device and method for manufacturing the same
CN113629059B (en) * 2021-05-21 2024-05-10 长江存储科技有限责任公司 Manufacturing method of 3D memory device and 3D memory device
KR20230026875A (en) * 2021-08-18 2023-02-27 에스케이하이닉스 주식회사 Memory device, manufacturing method of the memory device and operating method of the memory device
TW202337014A (en) * 2021-11-22 2023-09-16 美商應用材料股份有限公司 Nand cell structure with charge trap cut
KR20240010237A (en) * 2022-07-15 2024-01-23 삼성전자주식회사 Integrated circuit device and electronic system having the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130341701A1 (en) 2010-10-18 2013-12-26 Imec Vertical Semiconductor Memory Device and Manufacturing Method Thereof
KR20130123165A (en) 2012-05-02 2013-11-12 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
KR20130139602A (en) 2012-06-13 2013-12-23 에스케이하이닉스 주식회사 Semiconductor device, memory system comprising the same and method of manufacturing the same
KR20150130103A (en) * 2014-05-13 2015-11-23 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
US9368509B2 (en) 2014-10-15 2016-06-14 Sandisk Technologies Inc. Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
KR102577145B1 (en) 2016-01-25 2023-09-12 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
KR102551350B1 (en) 2016-01-28 2023-07-04 삼성전자 주식회사 Integrated circuit device including vertical memory device and method of manufacturing the same
US9865616B2 (en) 2016-02-09 2018-01-09 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
KR20180012640A (en) * 2016-07-27 2018-02-06 삼성전자주식회사 Vertical memory device and method of manufacturing the same
US10453855B2 (en) 2017-08-11 2019-10-22 Micron Technology, Inc. Void formation in charge trap structures
US11081497B2 (en) * 2019-08-22 2021-08-03 Micron Technology, Inc. Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies

Also Published As

Publication number Publication date
DE102020109802A1 (en) 2021-03-04
US11502097B2 (en) 2022-11-15
US20210066343A1 (en) 2021-03-04
KR20210025244A (en) 2021-03-09
CN112447758A (en) 2021-03-05
JP2021034734A (en) 2021-03-01

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