SG10202001145RA - Substrate patch reconstitution options - Google Patents

Substrate patch reconstitution options

Info

Publication number
SG10202001145RA
SG10202001145RA SG10202001145RA SG10202001145RA SG10202001145RA SG 10202001145R A SG10202001145R A SG 10202001145RA SG 10202001145R A SG10202001145R A SG 10202001145RA SG 10202001145R A SG10202001145R A SG 10202001145RA SG 10202001145R A SG10202001145R A SG 10202001145RA
Authority
SG
Singapore
Prior art keywords
reconstitution
options
substrate patch
patch
substrate
Prior art date
Application number
SG10202001145RA
Inventor
Hariri Haifa
P Alur Amruthavalli
K Jen Wei-Lun
A Salama Islam
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG10202001145RA publication Critical patent/SG10202001145RA/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381Crossover interconnections, e.g. bridge stepovers
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    • H01L23/3178Coating or filling in grooves made in the semiconductor body
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/732Location after the connecting process
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
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    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
SG10202001145RA 2019-03-12 2020-02-07 Substrate patch reconstitution options SG10202001145RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16/299,415 US11552019B2 (en) 2019-03-12 2019-03-12 Substrate patch reconstitution options

Publications (1)

Publication Number Publication Date
SG10202001145RA true SG10202001145RA (en) 2020-10-29

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Application Number Title Priority Date Filing Date
SG10202001145RA SG10202001145RA (en) 2019-03-12 2020-02-07 Substrate patch reconstitution options

Country Status (5)

Country Link
US (1) US11552019B2 (en)
KR (1) KR20200109244A (en)
CN (1) CN111696978A (en)
DE (1) DE102020103364A1 (en)
SG (1) SG10202001145RA (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) * 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11664315B2 (en) * 2021-03-11 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure with interconnection die and method of making same
US20230014450A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US20230063304A1 (en) * 2021-08-31 2023-03-02 Taiwan Semiconductor Manufacturing Company Limited Hybrid organic and non-organic interposer with embedded component and methods for forming the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6456502B1 (en) * 1998-09-21 2002-09-24 Compaq Computer Corporation Integrated circuit device/circuit board connection apparatus
US8389337B2 (en) * 2009-12-31 2013-03-05 Intel Corporation Patch on interposer assembly and structures formed thereby
US9275955B2 (en) * 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge

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Publication number Publication date
DE102020103364A1 (en) 2020-09-17
US20200294920A1 (en) 2020-09-17
CN111696978A (en) 2020-09-22
US11552019B2 (en) 2023-01-10
TW202101702A (en) 2021-01-01
KR20200109244A (en) 2020-09-22

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