SE516280C2 - Signal monitoring method and apparatus based on a sliding window - Google Patents

Abstract

The invention is generally directed towards monitoring of a signal (m), such as a clock signal or a data signal, by sampling the signal to obtain a discrete sample representation of the signal and analyzing the sample representation. The idea according to the invention is to slide a sample window (sw) over the sampled signal and determine whether the samples currently within the window include a valid transition sequence. in the general case, the existence of a valid signal is confirmed as long as a valid transition sequence is present in at least one of a predetermined number of consecutive sample windows. in order to reduce the need for oversampling in high-frequency applications, the invention furthermore proposes a multi-phase sampling technique according to which a number of phase-shifted sample clocks (s1 to sn) are generated for the purpose of sampling the signal to be monitored. Higher-frequency oversampling is thus replaced by a higher resolution in the time domain.

Description

516 280 ---- ~ ~ n u o uu 2 “Conventional signal monitoring units are often specialized, interoperable circuit solutions that require in-depth knowledge of the particular systems in which the monitoring units are arranged. This generally means that the signal monitoring units are tailored for signals with certain characteristics, which thus makes it difficult to adapt the signal monitoring units to system or adaptation changes that involve monitoring signals with other characteristics.

General detection mechanisms that can handle different types of signals under different conditions are usually very complex and require extensive data processing.

Current general detection mechanisms have worked quite well for monitoring low or moderate frequency signals. In high frequency applications, however, the detection time delay is generally far too high to be accepted. In many applications, the time from the actual signal error until the alarm is activated can be fl your clock cycles. For high frequency signals, there is simply not enough time for a complex detection mechanism to detect a signal error within just a few clock cycles. Of course, it would be advantageous if the reaction time was less than one cycle and close to ideal pulse width detection even for high performance and high frequency applications.

In high frequency applications, the monitored signal must generally be matched with a much higher frequency sample clock, so-called oversampling. However, when the frequency of the monitored signal reaches higher and higher levels, it may not be certain that it is possible to generate a high frequency sample clock for oversampling purposes, at least not at a reasonable cost.

For this reason, most general purpose loss detectors or signal monitoring devices operate in a fairly moderate frequency range where oversampling and complex state machines are still alternatives. Related Art The U.S. Patent 5,719,508 relates to a digital detector for dropped locking which is specially designed for a phase locking circuit in which the prescribed phase relationship between the locked signal and the reference signal during phase locking is 90 °. The detector comprises a number of locking flip-flops which are used to provide error signals for a number of possible erroneous relations between the locked signal and the reference signal.

U.S. Patent 4,852,124 relates to a clock signal extracting circuit based on a shift register, a transition detector and a frequency divider for deriving the extracted clock signal. A bipolar input signal is sampled to the shift register by a sampling signal having a frequency that is a multiple of the frequency of the input signal. The first outputs of the shift register are combined in the transition detector which detects the presence or absence of a simple transition from 0 to 1 and generates a corresponding transition detection signal. A correction logic circuit in the frequency divider compares the logic state of the frequency divider with the transition detection signal and orders a phase correction of the extracted clock signal based on the phase error thus detected.

U.S. Patent 5,926,047 relates to a signal loss detector specially designed for a delay lock circuit (DLL) of the type which produces a plurality of outputs in response to a clock signal. The dropout detector comprises a first monitoring unit and a second monitoring unit. The first monitoring unit receives a first output signal from the DLL circuit and the second monitoring unit receives a second output signal from the DLL circuit, each monitoring unit being clocked by the clock signal and the inverse of the clock signal. The first output signal and the second output signal have a predetermined phase relationship which prevents the occurrence of a racing condition at the monitoring units. The output signals of the monitoring units are processed by a number of logic gates to generate an alarm when the first output signal from the DLL circuit stops pulsing at the frequency which the clock signal has.

U.S. Patent 5,138,636 discloses a signal loss detection circuit for a digital signal receiver of the type which includes a clock recovery circuit for reconstructing the received clock. A signal loss is manifested by a lack of pulses in the reconstructed clock. The circuit for detecting loss or recovery of the received signal comprises a counter for counting pulses in the reconstructed clock which is located within a counting window. If the counter reaches a predetermined counting state during a counting window, signal recovery is indicated. In American cases, signal loss is indicated.

BRIEF SUMMARY OF THE INVENTION The invention overcomes these and other disadvantages of the prior art aITAIlgCIníiIlgCH.

It is a general purpose of the call to provide a general and robust signal monitoring mechanism.

In particular, it is desirable to provide a general monitoring mechanism that is exceptionally adaptable to a wide variety of applications, where the characteristics of the monitored signal may vary from application to application.

In addition, optimized high-performance implementations of the monitoring mechanism should require only a minimum of knowledge of the specific characteristics of the monitored signal. It is another object of the invention to provide a monitoring mechanism which offers an exceptional degree of error correction redundancy for handling possible metastability situations. Yet another object of the invention is to provide a monitoring mechanism which can be designed as a distributed detection algorithm and parallelized to reduce the overall complexity as well as the detection time delay.

It is further advantageous if the signal monitoring mechanism reduces the need for oversampling, which thus significantly increases the operating frequency range.

These and other objects are achieved by the invention as defined by the appended claims.

The recording is generally focused on sample-based signal monitoring where a signal is sampled to obtain a discrete sample representation which is analyzed to monitor the status and behavior of the sampled signal.

For monitoring a sampled signal, the general idea of the invention is to slide a sample window over the sampled signal and determine whether the samples currently located within the window represent a valid transition sequence. In the general case, the presence of a valid signal is confirmed as long as a valid transition sequence occurs in at least one of a predetermined number of consecutive windows.

The sample window is formed by M samples, where M is an integer equal to or greater than 3. Naturally, the actual length of the sample window depends on the number of M samples forming the window as well as the distance between the samples. The length of the window must be longer than the valid transition sequence to allow detection of the 516 6 'sequence within the window. For pulse width detection, the window is adapted to the length of the signal's pulse width or pause width, and for period time detection, the window is adapted to the period time of the signal. Preferably, the distance between successive samples in the window is less than the shortest of the pulse width and pause width of the signal to ensure sufficient detector resolution for general applications.

The sliding window technique of the invention allows pulse width detection down to variations in the duty cycle without the use of an explicit control algorithm to align the detection window and the anchor of the reference sample clock with the monitored signal transitions.

Preferably, each window of the predetermined number of consecutive windows is associated with an individual sub-monitoring mechanism for determining whether the samples within the current window represent a valid transition sequence. By arranging the partial monitoring mechanisms for both parallel and pipeline smelling function, rapid detection of each valid transition sequence in the monitored signal is obtained.

Depending on the particular settings of the application in question, for example when the monitored signal and the sample clock signal are synchronous with a given phase relationship and the sliding sample window is designed with a minimum of samples, the validity of the signal may be confirmed only as long as a a valid transition sequence occurs in each subsequent window. However, in the most practical cases, where the monitored signal and the reference sample clock are normally asynchronous, the condition for confirming validity is satisfied as long as a valid transition sequence is detected in at least one window in a whole set of successive windows. The number of consecutive windows in the ensemble of windows generally corresponds to the number of M samples forming the sliding window. 20 25 516 7 .To solve metastability problems for samples in the sample clock that occur in the vicinity of the transitions in an asynchronous monitored signal, extra redundant error correction is introduced by including a larger number of M samples with shorter distances in between and viewing samples symmetrically around all indeterminate states . In this way, detection of all fl anchor transitions in the monitored signal is ensured. By controlling the number of M samples in the sliding window, a flexible degree of error correction can be introduced. Of course, higher order corrections require a larger number of M window samples than lower order corrections.

The actual number of M samples in the window depends to a large extent on the particular application and can vary from M equal to 3 in cases where the monitored signal and the sample clock signal are synchronous and there is an inverted phase relationship between the two signals, to M equal to or greater 6 for asynchronous signals with large deviations in frequency and duty cycle as well as poor jitter properties.

The invention thus offers an extremely adaptable monitoring mechanism, which, by simply setting the number of M samples in the sliding window and the distance between successive samples, can be adapted to handle both different applications and possible metastability situations that may arise for asynchronous signals.

To reduce the need for oversampling in high frequency applications, the invention further proposes a multiphase sampling technique according to which a number of phase shifted sample clocks of the same frequency are generated for sampling the signal to be monitored. Various delay elements can be used to create the phase-shifted sample clocks without the use of a high frequency clock that would otherwise be introduced during oversampling. Higher frequency oversampling is thus replaced by a higher resolution in the time domain. 20 25 o o u o nu n n o a n u ø a o v no 8 In a further refinement of the multi-phase sampling technique, there is no need for a separate set of sample clocks, but instead the phase-shifted sample clocks are synthesized directly from the monitored clock by delay elements.

The invention offers the following advantages: - A general and flexible adaptable monitoring mechanism; - Fast detection speed; - No need for complex targeting algorithms; - User-controlled and scalable accuracy and detector resolution; - An ibel exible degree of error correction for metastability situations; - Reduced need for oversarpling with high frequency sainpel clocks; - Improved working frequency range; - Parallelism; and - Self-monitoring.

Other advantages offered by the invention will be understood upon reading the following description of the embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS The invention together with further objects and advantages thereof will be best understood by reference to the following description when read in conjunction with the drawings, in which: Fig. 1 is a schematic of a block diagram signal monitoring unit / failure detector according to a basic embodiment; of the invention; Figs. 2A-B are schematic time diagrams illustrating the basic principles of a sliding window technique according to the invention; 5 Fig. 3 is a schematic timing diagram illustrating the monitoring of an asynchronous signal by a detection mechanism involving first order metastability correction; Fig. 4 is a circuit diagram of a signal monitoring unit / dropout detector according to a preferred embodiment of the invention; Fig. 5A is a schematic timing diagram illustrating an example of a monitored signal M, sample clocks S, to SN and sample values ul to uN for case N = 8; Fig. 5B is a timing diagram illustrating an example of individual indications LOS (i) and the composite alarm signal LOS for the monitored signal and sample clocks of Fig. 5A; Fig. 6 is a schematic time and sample point diagram illustrating the sample window formed for a given sample phase di, including a sub-window for an expected secondary transition; Fig. 7 is a schematic time and sample point diagram illustrating a continuous stream of primary and secondary transitions triggering a chain of overlapping so-called adaptive mustard window; Fig. 8 is a schematic circuit diagram of a signal monitoring unit / dropout detector similar to that of Fig. 4 except for a time-out mechanism when a primary transition is detected but no secondary transition occurs; Fig. 9 is a schematic diagram of a mechanism for detecting "glitches" which can be incorporated into the dropout detectors according to the invention; 20 25 u o c c oo 516 280 v a c ø - ø n ~. Fig. 10 is a schematic circuit diagram of a basic self-monitoring clock drop detector according to a preferred embodiment of the invention, illustrated for case n = 3; Fig. 11 is a timing diagram of a dropout detector using sample phases extracted from the monitored clock with two connected, possibly slightly overlapping pulse width sub-windows; and Fig. 12 is a schematic diagram illustrating the basic divided sample window hierarchy together with the underlying time-discrete base of sample points.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The same reference numerals will be used throughout the drawings for corresponding or similar elements.

The general idea of the invention is to monitor a sampled signal by incrementally letting a window with a predetermined number of M samples play over the sampled signal and determining whether the samples currently in the window include a valid transition sequence. In general, the presence of a valid signal is acknowledged as long as a valid transition sequence occurs in at least one of a predetermined number of consecutive windows. If the validity of the signal cannot be confirmed, there is generally a signal error, for example due to the signal being stuck low or high.

As the name implies, a transition sequence is a sequence of at least two transitions.

Consequently, a valid transition sequence may be, for example, a low-to-high "up-transition". | Onan Q - n »11 transition" followed by a high-to-low "down-transition", or any other predefined sequence of transitions. Preferably, for pulse width detection, a valid transition sequence comprises a first transition and a later opposite transition in a position corresponding to the expected pulse / pause width of the signal (taking into account any variations in the monitored signal). Thus, in the case of a pulsating clock signal, the valid transition sequence may alternate between a first sequence defined by an up-transition followed by a down-transition, and a second sequence defined by a down-transition followed by an up-transition, where the two the transition sequences are seamlessly interconnected.

The minimum number of M samples in the sliding sample window is normally equal to 3, and such a minimum window is applicable, for example, in situations where the monitored signal and the sample clocks are synchronous and the phase relationship between the two signals is well defined. For a general and possibly asynchronous signal with an arbitrary phase relation to the sample clock, the number of M sarnples in the sliding window must be larger to ensure reliable monitoring of the signal. In the most practical cases where the monitored signal is asynchronous in relation to the sample clock, M is chosen to be equal to or greater than 6, although a smaller number is possible in some circumstances also in the asynchronous case.

For a better understanding of the invention, a schematic system overview will be given as an introduction, and then the monitoring mechanism according to the invention will be described with reference to a number of simple examples of well-behaved synchronous signals with given phase relations to a sample clock signal. Later, the inventive mechanism will be described in a more general context, in particular with reference to the preferred multiphase sampling technique proposed according to the invention. Fig. 1 is a schematic block diagram of a signal monitoring unit / dropout detector according to a basic embodiment of the invention.

The signal monitoring unit 10 essentially comprises a sampling unit 20 and an analysis unit 30. The sampling unit 20 is a general circuit for sampling a signal M to be monitored to a memory buffer 21. For example, the sampling unit 20 may be a shift register-based circuit using a higher frequency sample clock S for oversampling of the monitored signal. Alternatively, according to a multiphase sampling technique proposed by the invention, the monitored signal M is sampled to an array of rigantriggered memory elements through a number of phase shifted sample clocks S, to SN. For the time being, however, it is sufficient to consider the sampling unit 20 as a general circuit for sampling the monitored signal to obtain a discrete sample representation U of the signal. The discrete sample representation U is analyzed by the analysis unit 30 to assess the validity of the signal, and the analysis unit 30 provides learning alarm (LOS) or other messages depending on the result of the analysis. The analysis unit 30 can be implemented in hardware logic or as software in a computer system based on, for example, a digital signal processor (DSP) or the like. The analysis unit 30 essentially comprises a unit 31 for realizing a sliding window, a unit 32 for searching for a transition sequence and a unit 33 for validation check. In a computerized implementation, the units 31 to 33 are preferably realized as software functions, procedures or modules. In a hardware implementation, the unit 31 for realizing a sliding window and the search unit 32 are preferably integrated in the same hardware logic, as will be explained later with reference to Fig. 4.

Figs. 2A-B are schematic timing diagrams illustrating the basic principles of the sliding window technique of the invention. Fig. 2A illustrates a signal M to be monitored, a sample clock signal S for sampling the signal M, and a resulting discrete sample representation U of the monitored signal. For simplicity, the monitored signal and the signal clock signal are illustrated as synchronous, the phase relationship between the two signals being optimal for signaling purposes. The monitored signal M has a duty cycle of 50% with a pulse width equal to the pause width.

For pulse width detection, a valid transition sequence is defined as a first transition followed by an opposite transition in a position that corresponds to the expected pulse or pause width. To allow pulse width detection, the sliding window must be large enough to capture a pulse or pause. The minimum window length requirement in this case is three samples, and the distance between successive samples in the window must generally be equal to or less than the pulse width to ensure sufficient resolution. In this example, the distance between successive samples is set to be equal to the pause width. This works well for the optimal phase relationship between the monitored signal and the sample clock illustrated in Fig. 2A. In general, however, a distance between successive snarls is recommended which is much smaller than the shorter of the pulse and pause widths.

Fig. 2A illustrates a number of successive and overlapping windows W1 to W4 formed by sliding a window with at least 3 samples over the sampled signal. For each subsequent window, it is determined whether the window includes a valid transition sequence. When looking at window W1, it can be seen that the signal M includes a first transition as well as a second opposite transition within the window.

The so-called valid transition sequence is detected in the sample representation U of the signal by comparing the logical levels of adjacent samples in the current window. A transition is normally detected as a change in logic levels between adjacent samples. In window W1, a first transition is detected as a change from 0 to 1 between the first and second samples, and a second opposite transition is detected as a change from 1 to 0 between the second sample and the third sample of the sample representation. U. A sufficient transition condition has generally been found to be: uiæui + 1 = 1ß where ui is the i: th sample and EB indicates an XOR operation. In window W2, a first transition is detected as a change from 1 to 0, and a second opposite transition is detected as a change from 0 to 1. A valid transition sequence is also found in window W3. However, in window W4, only a single transition from 1 to 0 is detected, and this transition cannot be paired with an expected opposite transition (the actual signal is indicated by a solid line, while the expected normal signal is indicated by dashed lines). In the example above, which represents a special case of the general monitoring mechanism when applied to a synchronous signal, the validity of the monitored signal is confirmed only as long as a valid transition sequence occurs in each subsequent window. Thus, one can already at the end of window W4 conclude that the signal M is no longer valid. This is really a correct assessment because the signal M has actually disappeared in the low state. Obviously, the sliding window technique of the invention can provide rapid dropout detection.

Fig. 2B is similar to Fig. 2A, but now the monitored signal M is illustrated with another duty cycle so that the pulse width is twice the length of the pause width. The resolution is normally adjusted to the shorter of the pulse width and pause width. In the example illustrated in Fig. 2B, the distance between successive samples is selected to be equal to the pause width. The sliding window is naturally adapted to the longer pulse width, even though it is possible to adapt the window to the shorter pause width. 20 25 516 280 f; n v v o u ~ -. . | ,. However, with the required resolution, the number of M samples in the sliding window is selected to be equal to 4. This actually allows detection of individual pulses as well as individual pauses in the signal. By analyzing the sample representation U of the monitored signal M using the sliding window and using the above transition condition, any valid transition sequence in the monitored signal can be detected securely. In the first window W1, a valid transition sequence is detected as a positive pulse with a transition from 0 to 1 and a subsequent transition from 1 to 0. In window W2, a valid transition sequence is detected as a pause or a negative pulse with a transition from 1 to 0 and a subsequent transition from 0 to 1. Valid transition sequences are also found in windows W3 and W4. However, in window WS, only a single transition is detected. Since the arrangement according to Fig. 1B requires that a valid transition sequence occurs in each subsequent window to confirm the validity of the signal, it can be concluded at the end of window WS that the monitored signal M is no longer valid.

Fig. 3 is a schematic timing diagram illustrating the monitoring of an asynchronous signal by a detection mechanism that includes first order metastability correction. For a signal M which is asynchronous with respect to the sample clock signal S, metastability situations may occur when transitions in the sample clock occur in the vicinity of transitions in the monitored signal; a well-known fact on the subject. When the monitored signal is sampled by the sampling clock of the sample clock near a transition in the monitored signal, it may not be possible to obtain a well-denominated sample value. In such a situation, it is not clear whether the monitored signal has really had its transition and thus the sample value may be indeterminate. In Fig. 2, indeterminate sample values are indicated by X in the sample representation U. The minimum distance between transitions in the sample clock and monitored transitions required for safe sampling may vary depending on the particular implementation of the monitoring unit. 5 25 zso 16 Increasing the number of M samples in the sliding window to include a number of so-called redundant samples allows error correction. In the event of a metastability situation that affects a certain sample, ui, samples in the vicinity, primarily uH and um, are probably not affected and exhibit well-defined logical values. Consequently, by considering not only adjacent samples u, and um but also samples separated by one or fl your intermediate samples, preferably placed symmetrically around any sample u, being examined, detection of all fl anchor transitions in the monitored signal is ensured. This results in the following transition conditions: ui æ ui + 1 = Ûch 111-153 Ui + 1 = 1- Accordingly, in the example illustrated in Fig. 2, the sliding window comprises a total of 5 samples, two more than what is required for a synchronous signal . When you let the window slide over the sample representation, a series of successive windows is formed, of which only windows W1 to W4 are shown explicitly. In the first window W1 it is obvious that the monitored signal M comprises a pulse, but in the sample representation “O X 1 1 O” in window W1 a sarpel has been destroyed (X) due to metastability. However, by successively viewing adjacent sarnpel u, and um as well as sampler um and um, separated by a sampler, all pulse transitions of the pulse can be detected. In window W1, the positive pulse is detected as a first transition from 0 to 1, determined from the first and third samples of the window, and the second transition from 1 to 0 is determined from both the third and fifth samples of the window and the fourth and fifth samples. In the next subsequent window W2, the positive pulse cannot be detected, but since the pulse has already been detected by the first window W1, this has no significance. Here, the general condition for validation is based on an ensemble of successive windows since 20 516 280 o o o. now -. v n a o q a o Q. o v ø n. . . p; 17 the sliding sample window includes redundant samples. Validity is generally confirmed as long as at least one window in the ensemble of consecutive windows includes a valid transition sequence. The number of windows in the considered ensemble of windows is at least partly dependent on the level of sample redundancy.

The next valid transition sequence is the coupled negative pulse and this transition sequence is captured by both the third subsequent window W3 and the fourth window W4. Metastability situations are effectively managed by using the transition conditions given in expression (2) above to capture the transition sequences of the monitored signal.

Higher order extensions are realized by inserting additional redundant samples in the window and comparing samples separated by more than one sample. There is, of course, a compromise between reliability and complexity in this regard.

It is obvious that metastability correction requires a larger number of M samples within the sliding window compared to a monitoring mechanism without any correction possibilities. Thus, it may seem necessary to increase the frequency of the sample clock to clamp an additional number of samples into a sliding window adapted for a given pulse width. For high frequency applications, this would be a serious limitation. However, the invention substantially reduces this problem by a multiphase sampling technique, which will be described in detail below in connection with a preferred embodiment of the invention.

As a general principle, and above all to reduce the need for oversampling in high frequency applications, the invention proposes a multiphase sampling technique, according to which a set of N phase shifted sample clocks S, to SN with the same frequency is generated in order to sample the signal to be monitored. There are different ways of generating the phase-shifted clock signals, for example by delaying 20 5 516 280 n v ø Q ø n> n. Q o o »18 a main clock using a number of delay elements in a conventional manner, or from division and decoding of a higher Clock Frequency, if such a fi mis available. In the previous case, oversampling is replaced by a much higher sample clock frequency compared to the monitored signal of resolution in the time domain, which places strict demands on phase accuracy. In the latter case, however, the problems of oversampling remain.

In the following, the invention will be described in connection with a special implementation, adapted for pulse width detection of a clock signal.

Fig. 4 is a circuit diagram of a signal monitoring unit / dropout detector according to a preferred embodiment of the invention. The signal monitoring unit 40 is implemented as a parallelized hardware structure, which comprises a number of kt anchor-triggered memory elements, such as digital flip-flops 41-1 to 41-N, one for each individual sample clock, a corresponding number of sub-monitoring units 42-1 to 42-N (of which only two are shown ) for generating individual validity indications LOS (1) to LOS (N), and a logic element 43 for generating a composite alarm signal (LOS) from all the individual validity indications.

During a sample cycle, each phase-shifted sample clock Si samples the monitored signal M as a data signal to a respective digital flip-flop register 41 to generate a corresponding sample value ui. See also the time diagram in Fig. 5A which illustrates an example of a monitored signal M, sample clocks S1 to SN and sample values ul to uN for the case N = 8. The example in Fig. 5A illustrates an initialization period, an error where the signal has stuck high and a subsequent error where the signal has stuck low.

The sample values u, to uN in registers 41-1 to 41-N are fed to the sub-monitoring units 42-1 to 42-N in the manner illustrated in Fig. 4 and processed therein. Essentially, the logic circuit in each sub-monitoring unit implements a search method for determining whether a sample window associated with the corresponding sample phase includes a valid transition sequence. In this case, a valid transition sequence is found if a primary transition and an expected secondary opposite transition in a position corresponding to the expected pulse / pause width of the monitored clock signal are encountered. If such a valid sequence is found, a corresponding individual validity indication LOS (i) is set high. The main alarm LOS is a composite alarm formed by all the individual indications. See also the time diagram in Fig. SB, which illustrates an example of individual indications LOS (i) and the composite alan signal LOS of the monitored signal M and the sample clocks S, to S8 according to Fig. 5A. The composite LOS signal is active low. The LOS signal is high and inactive as long as at least one individual LOS (i) signal is high. The LOS signal usually becomes low only when all individual LOS (i) signals are low, due to an anonymous behavior of the monitored signal.

To correctly describe the sampled clock signal M, a whole set of phases must be obtained with a reasonable distribution over the sample clock period TS. Ideally, the clock signals S1 to SN are evenly distributed, Ad> = d> föj = 21tlN if i <> j, with phases dal to 41,., Which in a sample period TS fills a window suitable for a selected transition sequence in the monitored signal . In fact, the phase-shifted sample clocks form a complete base vector system for describing the monitored signal M in the discrete time domain of the sample clock, as illustrated in the time diagram of Fig. 5A.

The phase resolution or distribution Ad) (or ATS in the time domain) with associated tolerances will ultimately determine how narrow clock pulses öTM (or pauses [1-ö] TM) can be detected depending on the set-up (tSU) and hold times (tH) requirements. for the registers used to sample the monitored signal. The monitored 20 25 | ø 0 | oo 516 280 n n n v s I I I a | v o n u n n n co 20 'The duty cycle of the clock signal is assumed to vary in the interval 5M <ö <1-öM. The following definitions and requirements are set: ts = SuPÜsu = tu) Ad> = öftbi + l Vi G {1, ..., N} ATs = Ad> / (21r) -Ts min (ATS)> 2ts max (ATS) < 5MTM + 2ts, where min (ATS) and max (ATS) are determined taking into account the associated tolerances.

Strict requirements for the sample phase distribution (Aömn) ensure that two consecutive sample clocks are mutually delayed (phase-shifted) more than the set-up and holding times of the registers.

A sample period that is wide enough to accommodate the longest pulse is defined. of a simple XOR gate, which has a non-negative output signal only if the input signals are not equal. As already mentioned earlier, it has been shown that a sufficient transition condition between two arbitrary sample points (i, i + 1) is: uiGBui + 1 = l Vi e {1, ..., N} 20 25 516 280 i 21 where EB denotes an XOR operation.

Cyclic conditions imposed on the phase-shifted clocks can be expressed as: uN + l = ul Obviously this is the case in a causal system with a whole set of non-overlapping sample phases covering the whole sample period TS so that a new sample period is initiated seamlessly with the update of the last register 41-N. For a specific sample event or sample point (i) associated with a positive fl of the sample clock Si, the detection of a primary clock transition (TR1) in the vicinity preferably includes previous and subsequent sample phases: ui æ ui_1 + ui æ ui + l where the plus sign denotes a OR operation.

In the case of a metastability state that occurs in the register 41-i that is currently being updated, other registers in the vicinity are usually not affected and contain correct data. Preferably, redundant logical expressions are used, uM GB which include solving any additional sample points to ui + lß metastability problems and secure any transition that occurs in the vicinity of a clock phase Si.

As mentioned earlier, higher order extensions, which compare register contents separated by more than one sample phase, introduce a higher degree of error coverage at the expense of an increased logic depth, which includes fl your sample phases in each 20 25 516 280 u - u ø o | . | u o ø o n ø wo 22 .and one of the N equal decision intervals merged into the overall alarm. It should be noted that additional correction elements reduce the effect of metastability duration over many sample cycles, which can prove troublesome if too many registers are affected simultaneously with a rotational phase relationship between the asynchronous sample clocks and the monitored clock. Increased fault tolerance also requires a refined phase distribution to fit in the detection window (W).

In the implementation according to Fig. 4, the search for a primary transition around the sample phase is initiated with the first order error correction of: TRNÜ: 11159 Ui-r + ua G9 Ui + 1 + 111-159 Um where EB denotes an XOR operation and the plus sign denotes an OR -Operation. In each sub-monitoring unit 42, the search for a primary transition as above is realized by three XOR gates followed by an OR gate.

The expected secondary transition (TR2) must occur in a secondary transition sub-window, which is defined by the lower limit wl and the upper limit wu which are offset from the sampled point being examined, in order to ensure that the secondary transition is found in a position corresponding to the monitored signal pulse / pause width: TR2 (i) = 111 + w1 ('19 How., This is realized by an additional XOR gate. Preferably, the window [wl, wu] for the secondary transition is wide enough to accommodate deviations in Clock Frequency Only valid transitions are of interest and since the detection window is wide enough to handle all variations, there is generally no need for Depending on the level r of redundant sample information from previous sample points (il, i-2, ..., ir) required, the following applies: wu + r + ls N 15 wl s wu-1 For v In each sample phase, the two transition expressions TR1 (i) and TR2 (i) are combined by an AND operation realized by the AND gate in the corresponding sub-monitoring unit 42, to generate an individual validity indication LOS (i): LOS (i) = TR1 (i) 0 TR2 (i), where 0 denotes an AN D operation.

Further for fi ning allows a separation of the two transitions high-to-low and low-to-high, which enables detection of harmonic frequencies. More than one up-transition (TRU) or down-transition (TRD) in a row is then not allowed. Error correction is not included in the example below: LOS (i) = TRU1 (i) 0 TRD2 (i) + TRD1 (i) 0 TRU2 (i) TRU1 = out -EHTi-uin TRD1 (i) = 0 uH + ui 0 u i + l TRU2 (i) = u i + wl. ui + wu TRD2 (i) = uHw, 0 u- H-WU 7 20 25 516 280 n ø n | ø o n | o n u c n a u .o 24 where u denotes a logical inverse of u. In the implementation according to Fig. 4, the LOS signal is an alarm that is active low. The composite alarm signal LOS is formed as an overlay of all individual indications from the different intervals around each sample phase (Si), and at least one interval or sample window must include a valid transition sequence to confirm the presence of a valid clock signal. This is realized by the OR gate 43 in the monitoring unit 40 according to Fig. 4: LOS = LOS (1) + LOS (2) + + LOS (N), where the plus sign denotes an OR operation.

To summarize the implementation in hardware according to Fig. 4 so far, the clock monitoring according to the above preferred embodiment comprises a basic search procedure which is denined by TR1 (i) 0 TR2 (i) and housed in an individual sample window SWi. Simply put, this basic search procedure is repeatedly performed in a cyclic / pipeline-like manner for all sample phases (cbi / S1), which in practice realizes a procedure with a sliding window.

Fig. 6 is a schematic time and sample point diagram illustrating the sample window formed for a given sample phase di, including a sub-window for an expected secondary transition. For each sample phase di, a sample window SWi is stretched starting from the corresponding sample point i or the previous sample point i-1, depending on the particular realization of the primary transition expression TR (i), and extending substantially an entire sample period TS. In each sample window SWi, a possible primary transition is monitored at the beginning of the sample window, and if one is found, a subsequent subwindow STW [i + wl, i + wu] is formed for the expected secondary transition. 20 25 516 2ßaß = 25 .The sample information (associated registers) for a given sample window SWi is updated only once during a sample cycle triggered by positive (or negative) transitions in the sample clocks that form part of the particular sample window. Causality is preserved if the results of both fl duck detection and time-out control for the secondary transition are processed and stored in a register only once during a sample cycle, at the first subsequent clock phase (mare) outside the respective window (STW) for the expected secondary transition. For this purpose, each sub-monitoring unit 42 (see Fig. 4) has a register (DFF) for regular storage / updating of the individual validity indication LOS (i). No registers may be reloaded with new information before the end of the storage cycle, which requires that the entire search procedure be contained in a single sample period. Note the cover from phase <1> N associated with sample clock SN to phase beer associated with sample clock S1.

Basically, the clock monitoring is handled by a technique based on division into smaller problems (English divide and conquer) which allows the problem to be discretized in the time domain using a number of phase-shifted sample clocks to form overlapping sub-intervals, referred to here as sample windows (SW) , where a sample window is formed around each sample point (see Fig. 6). Each sample phase is scanned together with the necessary phases in the associated sample detection window using a distributed algorithm, which is reproduced for all other sample phases and then forms a set of N overlapping sample windows (SW). At least one of the sample windows must generally include a valid transition sequence during a sample clock cycle (TS); amiars, the monitored signal is declared invalid.

It is clear that each individual sample window (SW¿) within a sample cycle (TS) is associated with an individual sub-monitoring mechanism, which determines whether the samples within the sample window (SW¿) include a valid transition sequence. For optimized performance, these sub-monitoring mechanisms are provided for both parallel and pipeline-like operation. In the example of Fig. 4, the parallelism originates from the hardware structure of the overall monitoring unit 40, and the pipeline-like function, which is an inherent feature of the sliding search procedure, is manifested through the phase-shifted sample clocks.

Fig. 7 is a schematic time and sample point diagram illustrating a continuous stream of primary and secondary transitions that trigger a chain of overlapping so-called adaptive sample windows. If a primary transition (Pk) is actually detected in a sample window and an opposite transition (Sk) occurs in the associated secondary transition window, then the alarm indication LOS (k) is valid for a sample clock period (to rel) and an adaptive sample window (ASWk) extending from the primary transition to the storage pulse (mare) is formed. The secondary transition (Sk) in this window becomes a primary transition (PkH) in the next coupled and overlapping adaptive sample window (ASWkH) derived from the same (when the sample clocks and the monitored clock are synchronous) or an amiat (asynchronous) individual sample window in the next sample cycle. Compared with known techniques, the alarm handling according to the invention is reversed so that the monitored clock must prove its existence (in any sub-interval within a sample cycle) in order to avoid an indication of clock loss.

To take full advantage of the performance potential of the monitoring unit / failure detector, an error condition is introduced with respect to the fact that each individual sample window indicates FAIL when a primary transition is not followed by a secondary transition within the prescribed secondary transition window. As described above, a valid transition sequence in a sample window deletes the alarm for substantially one sample clock period (TS). Since the adaptive sample windows overlap, a high drop-out indication signal (no alarm) generated by the last valid secondary transition is released for a certain time or a detection of an erroneous error. n u n o. o n. a | o u oo 27 transition sequence. The alarm is thus delayed unnecessarily long. True pulse width detection within the current adaptive window is realized if the dropout detection signal also takes into account that no fault conditions are allowed at any window fl ank in a manner similar to the previously described dropout generation.

Fig. 8 is a schematic circuit diagram of a signal monitoring unit / dropout detector similar to that of Fig. 4 except for a time-out mechanism when a primary transition is detected but no secondary transition occurs. Like the monitoring unit 40 according to Fig. 4, the monitoring unit 50 according to Fig. 8 comprises a number of fl anchored trigger elements 51-1 to 51-N and a number of sub-monitoring units 52-1 to 52-N (of which only two are shown). In this realization, however, at least one valid and no erroneous transition sequences are required at each time to give an output signal free from alarm (logic high). Because of this, each sub-monitoring unit 52 is adapted to generate both an individual LOS (i) signal and an individual error signal FAIL (i). Each individual error signal FAIL (i) is formed in a manner similar to the individual LOS (i) signal, with the exception of an inverter arranged in the path from the XOR gate, which performs the control of the secondary transition, to an additional AND gate that generates the individual error signal. The main alarm signal ALARM is obtained from an AN D gate 55 which sums the composite LOS signal from the OR gate 54 and the composite FAIL signal from the inverter 57, which follows the OR gate 56. The composite FAIL signal is formed from all individual fault indications FAIL (in). In this connection, reference is again made to Figs. 5A-B where the improvement in detection time of the resulting alarm signal ALARM (LOS in Fig. SB) for a failure detector which detects fault conditions is indicated by dotted lines.

Fig. 9 is a schematic diagram of a mechanism for detecting "glitches" which can be incorporated in the dropout detectors according to the invention. Detection of glitches that cover irregular clock behavior other than pure clock loss requires a more 25. . . . .. - - s o o ~. a o. 28 'sophisticated decision algorithm. Exactly a valid transition sequence is allowed in a complete sample cycle (TS) including the contribution from all individual sample windows.

According to a preferred embodiment, glitch detection is performed through a branched tree topology, which consists of successive XOR comparisons of two values in each level. Such a topology ensures that only one individual LOS signal at a time can suppress the overall failure alarm.

If no oversampling is used, sample periods and monitored clock periods must be of approximately the same order of magnitude (but still cope with pulse width variations) and thus include two sets of transition sequences in each sample cycle. For the glitch-sensitive detector, the OK condition is now exactly two transition sequences in each sample period, maintaining an adaptive detection window with a response time of a bit-wide procedure.

Finally, in a specialized and refined embodiment, there is no need for a separate set of sample clocks. Instead, the phase-shifted sample clocks are created or synthesized directly from the monitored clock. In a synchronous system based on normal fl anchor-triggered memory elements, such as DFF elements, it seems impossible to monitor a clock signal and form an infinitely held alarm signal without using any means other than the clock itself, which by the very nature of the monitoring problem disappears unexpectedly (high or low, etc.).

The introduction of delay elements enables processing of the current input signal or monitored clock using previous time information (transitions), somewhat similar to the mathematical autocorrelation concept of a stationary signal, which in this case corresponds to a benign clock signal without glitches. Cascading explicit or delay networks implicitly formed in logic networks (AT1, ..., ATn) provide a way to create a set of n phase shifted or delayed clocks, hereinafter referred to as M1, M2, ..., Mn, more or less directly from 25 516 2180 a. . . . -. . «- - ~ ø ø ~ H 29 the monitored clock signal M itself. The basic topology of the self-monitoring detector is preferably adapted to reduce complexity and thus takes full advantage of all the additional information acquired from the specific synchronous sample clock generation algorithm which will be explained below.

Fig. 10 is a schematic circuit diagram of a basic self-monitoring clock drop detector according to a preferred embodiment of the invention, illustrated for case n = 3. The self-monitoring dropout detector 60 mainly comprises a number of delay elements 61-1 to 61-3 in cascade to form a corresponding number of delayed clocks M, to M3, two registers 62-1 and 62-2, two XOR gates 63-1 and 63 -2, two additional registers 64-1 and 64-2 for storing / updating individual signals LOS_H and LOS_L as well as a logic element 65 for forming a composite LOS signal.

The design of a signal monitoring circuit without any other means than the signal itself, i.e. without an independent sample clock, gives rise to a particular problem if the detector must react and change state within a signal period, i.e. pulse width detection rate. A new concept that differs slightly from the parallel processing previously used in the main algorithms is introduced to address this problem. Each sample window is now divided into a series of connected, or slightly overlapped, sub-windows (PSW). Each pane is updated only once during a sample period, but the cascade structure enables much faster detection. Most important is the ability to achieve pulse width detection speed even in a period-based detector without having to return to oversampling.

For a better understanding of the concept of self-monitoring, reference is also made to Fig. 11, which is a timing diagram of a dropout detector using sample phases extracted from the monitored clock with two connected, possibly slightly 25. . . . .-. | | o ø o n ~ o ~ I U I I I '' 30 overlapping, pulse width panes. First, the monitored clock M appears and the failure detector requires approximately an additional sample period to drop the alarm signal for initiating the self-monitoring. Two error situations are described, namely when the monitored clock gets stuck low and high.

In each sample cycle, a specific valid transition must occur in each of the split panes, PSW_H and PSW_L. Each sample cycle is initiated by a positive transition in the monitored clock M. All delay and phase relationships are referenced to a zero plane in time and phase associated with this triggering initial transition. In particular, it is important to understand that state information, hard-coded HIGH, is obtained based on this implicit initial transition and is used in assessing whether the first panel, PSW_H, includes a valid transition. This is possible because the monitored clock always shows a positive transition at least one period before the clock is lost. This also eliminates the first sample phase that is otherwise needed in the main algorithm, and is realized by hard coding one of the inputs to the first XOR gate 63-1 HIGH. Without any error correction in an elementary implementation of the lowest order, the valid transition conditions for the split panes are: 1 G3 ul = 1 (PSW_H) u] GB H2 = 1 (PSW_L) Two associated independent indications for dropout detection are generated as follows: Los_H = 1G ; ul Los_L = ul c +> 112 20 25. . . . .. o ø. ~ q o ~. I v O 'I O' ° '31 and stored in the associated registers 64-1 and 64-2 in response to M2 and M3, respectively.

More specifically, the transitions in the second (synergism with the sample function) and third storage pulses for and LOS_L, the sample clock, act as an update of the two dropout detection signals, LOS_H outside the respective transition windows.

According to the splitting algorithm used here, both LOS_H and LOS_L must include a valid transition, which gives the composite short-fall detection signal LOS as follows: Los = Los_H - LOS_L = (1 o ul) - (u, es 112) Delay accuracy and variations in the monitored the signal due to irregularities in the work cycle as well as time jets must be carefully considered. Although not required in the simplest implementation of the self-monitoring failure detector, the previously described techniques for providing felexable error correction can also be applied in self-monitoring applications.

In-depth exploitation of the sub-window splitting technology proposed above also increases the för flexibility for the main algorithm and introduces a new degree of freedom that makes the concept more general and easy to adapt to a wider range of monitoring problems with fewer constraints. The basic structure of the detectors shown in Figs. 4 and 8 does not require any significant modifications. In particular, one can preserve the fundamental idea based on division into smaller problems that is repeated in the formation of a set of parallel sample windows and those with the simple combinatorial phase-shifted sample clocks together the alarm generation that is repeated at both micro and macro level. In general, 20 25 ø ø e ø oc 516 280 o I ',. . ,,,,. . . ~ | | ø ou 32 each slam window (SW ,, ..., SWn) in a sample cycle is divided or split into a series of divided sub-windows (PSW fl, PSWQW., PSWim i = l ... n): Pswn Pswlm Pswn, Pswnm Fig 12 is a schematic diagram illustrating the basic divided sample window hierarchy together with the underlying time-discrete base of sample points. In each split pane, a specific transition, or alternatively a valid transition sequence, is defined and compared with observed transitions. A valid transition or transition sequence must occur in each pane related to a particular sample window to allow a positive individual LOS (i) signal: LOS (i) = LOS (PSW, -1) 0 LOS (PSW¿2) v LOS (PSWi ,,) In the same manner as described above, the composite LOS signal is usually formed as an overlay of all individual LOS (i) signals.

Extending the scope to cover a wider range of signals than pure stationary and cyclic clock signals requires only a small change in the detector implementations described. For example, different line codes and other means that limit the signal frequency spectrum ensure both a high transition density and a defined limit for the longest sequence of data bits with the same polarity, given a fundamental bit rate (width). The distance between the sample clock phases must be chosen narrowly enough so that a single data bit is reliably detected in analogy with previous analysis. The overall detection window must be wide enough to handle the longest pulse which here appears as the longest constant 20 ~ a o o nu u 516 280 n. . . | o n o Q u | u v u v o now 33 'bit sequence without data transition. Since data signals are aperiodic, there is no way to predict a transition and thus a division of the (sample) detection window into an equivalent set of bit width detection windows is preferred, which is the most reliable solution. In contrast to the partitioning procedure described in connection with the self-monitoring detector, a valid transition / transition sequence must appear in at least one of the linked subwindows (PSW) formed by the partitioning process. Here, single or multiple data transitions make no difference; simply replace the AND condition with an OR condition.

Even in a simple sample window without any division, it is still possible to implement a general signal monitoring circuit if ytterligare your additional transition conditions and error correction extensions are introduced in the larger window to handle all possible transition sequences.

The embodiments described above are given by way of example only and it should be understood that the present invention is not limited thereto. Further modifications, alterations and improvements which maintain the basic principles shown and claimed herein are within the scope and spirit of the invention.

Claims (33)

1. 20 25 n o o »no 516 280 o I. o n ø v o n. o. A method for monitoring a sampled signal, characterized in that the method comprises the steps of: sliding a window of M samples, where M is an integer equal to or greater than 3, over the sampled signal. ; determining whether the samples currently in the window include a valid transition sequence; and confirming the validity of the signal as long as the valid transition sequence is present in at least one of a predetermined number of consecutive windows. The monitoring method according to claim 1, characterized in that each of the predetermined number of successive windows is associated with an individual sub-monitoring mechanism for determining whether the samples within the current window comprise a valid transition sequence, the sub-monitoring mechanisms being arranged for both parallel and parallel pipes. feature. The monitoring method according to claim 1, characterized in that the valid transition sequence comprises a first transition and a later opposite transition in a position corresponding to the expected pulse / pause width of the signal. The monitoring method according to claim 1, characterized in that the predetermined number of successive windows generally corresponds to the number of M samples forming the window. 20 _ '. . . . .- n o n n o nu 35 15. The monitoring method according to claim 3, characterized in that the determining step comprises the steps of: searching for the first transition as a first change of logic levels between samples in the window; and searching for the complementary opposite transition as an opposite change of logic levels between later samples in the window located within a sub-window of samples corresponding to the expected pulse / pause width of the signal. The monitoring method according to claim 5, characterized in that the sample window is wide enough to accommodate deviations in frequency and duty cycle to a predetermined degree. The monitoring method according to claim 3, characterized in that the distance between successive samples in the window is less than the shortest of the pulse width and pause width of the signal, and that the window of M samples is longer than the pulse width or pause width of the signal. The monitoring method according to claim 1, characterized in that the valid transition sequence comprises at least two transitions and that the determining step comprises searching for each transition as a change of logical levels between samples in the window. The monitoring method according to claim 8, characterized in that the step of searching for each transition as a change of logical levels between samples in the window comprises comparing adjacent samples as well as comparing samples separated by one or andra your other samples, thereby improving error correction capability. obtained. 20 25 516 280 36 The monitoring method according to claim 1, characterized in that the sampled signal is obtained by sampling a signal with N phase-shifted sample clocks of the same frequency, where N is an integer equal to or greater than M so that the window fits within a single sample clock cycle. The monitoring method according to claim 1, characterized in that the method further comprises the steps of: indicating a valid transition sequence if such a sequence is found in the current window; and signaling errors if no valid transition sequence is indicated below the predetermined number of consecutive windows. The monitoring method according to claim 1, characterized in that the sliding window is divided into a series of sub-windows, and that the step of determining whether the samples currently in the window comprise a valid transition sequence comprises the steps of: the split panes determine whether the pane includes a valid transition or sub-sequence of transitions; and determining that the samples currently in the window include a valid transition sequence provided that at least one sub-window includes the corresponding valid transition or sub-sequence of transitions. The monitoring method according to claim 1, characterized in that the monitored signal is a clock signal or a data signal, the data signal having a given bit width and a predetermined limit for the longest sequence of data bits of the same polarity. 20 25 516 37 l 14. l4. The monitoring method according to claim 1, characterized in that the validity of the signal is confirmed as long as the valid transition sequence is present in each subsequent window. The monitoring method according to claim 1, characterized in that one of the M samples in the window is an implicit sample. A method of monitoring a clock signal, characterized in that the method comprises the steps of: sampling the clock signal with a set of delayed clock signals formed from the monitored clock signal itself, each sample cycle being initiated by a transition, of a given polarity, in the monitored polarity. the clock signal, and all delay and phase relationships are referenced to a zero plane in time and phase associated with the initial transition; sliding a sample window over the sampled signal; determining whether the samples currently in the window together with an implicit sample extracted from the initial transition in the current sample cycle include a valid transition sequence; and confirming the validity of the signal as long as the sample in the window together with the implicit sample includes the valid transition sequence. A device for monitoring a sampled signal, characterized in that the device comprises: means for allowing a window of M samples, where M is an integer equal to or greater than 3, to slide over the sampled signal; means for determining whether the samples currently in the window include a valid transition sequence; and 516 "38 means for confirming the validity of the signal as long as the valid transition sequence is present in at least one of a predetermined number of consecutive windows. The monitoring device according to claim 17, characterized in that each of the predetermined number of successive windows is associated with an individual sub-monitoring mechanism for determining whether the samples within the current window comprise a valid transition sequence, the sub-monitoring mechanisms being arranged for both parallel and parallel beeps. feature. The monitoring device according to claim 17, characterized in that the determining means operates on the basis that the valid transition sequence comprises a first transition and a later opposite transition in a position corresponding to the expected pulse / pause width of the signal. The monitoring device according to claim 17, characterized in that the predetermined number of successive windows generally corresponds to the number of M samples forming the window. The monitoring device according to claim 19, characterized in that the determining means comprises: means for searching for the first transition as a first change of logic levels between samples in the window; and means for searching for the complementary opposite transition as an opposite change of logic levels between later samples in the window located within a sub-window of samples corresponding to the expected pulse / pause width of the signal. 20 25 '516 39 The monitoring device according to claim 21, characterized in that the sample window is wide enough to accommodate deviations in frequency and duty cycle to a predetermined degree. The monitoring device according to claim 19, characterized in that the means for the sliding window operates on the basis that the distance between successive samples in the window is less than the shortest of the pulse width and pause width of the signal, and that the M sample window is longer than the pulse width of the signal or break width. The monitoring device according to claim 17, characterized in that the valid transition sequence comprises at least two transitions and that the determining means comprises means for searching for each transition as a change of logic levels between samples in the window. The monitoring device according to claim 24, characterized in that the means for searching for each transition as a change of logic levels between samples in the window comprises comparing adjacent samples as well as comparing samples separated by one or andra your other samples, thereby improving error correction capability. obtained. The monitoring device according to claim 17, characterized in that the sampled signal is obtained by a circuit device for sampling a signal with N phase-shifted sample clocks of the same frequency, where N is equal to or greater than M so that the window fits within a single sample clock cycle. The monitoring device according to claim 26, characterized in that the means for the sliding window and the determining means are realized as a parallel monitoring structure comprising, for each 25 o o v n. n. o n oo 40 .individual sample clock, a sub-monitoring unit for determining whether the samples within a window associated with the individual sample clock include a valid transition sequence and for selectively indicating a valid transition sequence for a predetermined period of time. The monitoring device according to claim 17, characterized in that the device further comprises: means for indicating a valid transition sequence if such a sequence is found in the current window; and means for indicating signal errors if no valid transition sequence has been indicated below the predetermined number of consecutive windows. The monitoring device according to claim 17, characterized in that the sliding window is divided into a series of sub-windows, and that the means for determining whether the samples currently in the window comprise a valid transition sequence comprises: means for determining, for each and every one of the divided panes, whether the pane comprises a valid transition or subsequence of transitions; and means for determining that the samples currently in the window comprise a valid transition sequence provided that at least one sub-window comprises the corresponding valid transition or sub-sequence of transitions. The monitoring device according to claim 17, characterized in that the monitored signal is a clock signal or a data signal, the data signal having a given bit width and a predetermined limit for the longest sequence of data bits of the same polarity. 10 20 25 '516 41' One device for monitoring a sampled signal, characterized in that the device comprises: a parallelized monitoring structure for allowing a predetermined window to slide over the sampled signal, the monitoring structure comprising a number of sub-monitoring units, one for each of a predetermined number in succession the following window formed by sliding the window over the sampled signal, and each sub-monitoring unit having: means for determining whether the sample in the corresponding window comprises a valid transition sequence; and means for indicating a valid transition sequence for a predetermined period of time provided that such a sequence is found within the window; and means for confirming the presence of a valid signal as long as at least one of the sub-monitoring units indicates a valid transition sequence. The monitoring device according to claim 31, characterized in that the device further comprises means for generating a plurality of phase-shifted sample clocks of the same frequency, the sampled signal being obtained by sampling a signal with the phase-shifted sample clocks; wherein the number of sub-monitoring units corresponds to the number of successive windows formed by sliding the predetermined window over the sampled signal during a sample clock period. An apparatus for monitoring a clock signal, characterized by: means for sampling the clock signal with a set of delayed clock signals formed from the monitored clock signal itself, each sample cycle being initiated by a transition, of a given polarity, in the monitored clock signal, and all delay and phase relations are referred to a zero plane in time and phase associated with the initial transition; 'Means for allowing a sample window to slide over the sampled signal; means for determining whether the samples currently in the window together with an implicit sample extracted from the initial transition in the current sample cycle comprise a valid transition sequence; and means for confirming the validity of the signal as long as the sample in the window together with the implicit sample comprises the valid transition sequence.