RU99115826A - MEMORY ARCHITECTURE FOR MULTI-FORMAT VIDEO PROCESSOR - Google Patents

MEMORY ARCHITECTURE FOR MULTI-FORMAT VIDEO PROCESSOR

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Publication number
RU99115826A
RU99115826A RU99115826/09A RU99115826A RU99115826A RU 99115826 A RU99115826 A RU 99115826A RU 99115826/09 A RU99115826/09 A RU 99115826/09A RU 99115826 A RU99115826 A RU 99115826A RU 99115826 A RU99115826 A RU 99115826A
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data
format
resolution
processor
standard
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RU99115826/09A
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Russian (ru)
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RU2214066C2 (en
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Тодд КРИСТОФЕР
Барт Алан КЭНФИЛД
Стивен Вейн ПАТТОН
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Томсон Конзьюмер Электроникс, Инк.
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Claims (14)

1. Цифровой процессор, имеющий общую архитектуру, для обработки многоформатных видеосигналов, содержащий входную цепь (2, 4, 6) для приема отформатированных видео данных высокого разрешения и отформатированных видео данных стандартного разрешения, декодер (16), соединенный с упомянутой входной цепью, для создания декодированных и распакованных данных высокого разрешения, преобразователь (22), соединенный с упомянутой входной цепью, для преобразования отформатированных данных стандартного разрешения в формат, совместимый с отформатированными данными высокого разрешения, общую память (20) для запоминания отформатированных данных высокого разрешения и стандартного разрешения во время обработки упомянутым процессором, и процессор (40) отображения для обработки упомянутых отформатированных данных высокого разрешения и упомянутых преобразованных отформатированных данных стандартного разрешения для отображения.1. A digital processor having a common architecture for processing multi-format video signals containing an input circuit (2, 4, 6) for receiving formatted high-resolution video data and formatted standard-resolution video data, a decoder (16) connected to the input circuit for creating decoded and decompressed high-resolution data, a converter (22) connected to the input circuit for converting formatted standard-resolution data to a format compatible with formatted high-resolution data, a common memory (20) for storing formatted high-resolution and standard-resolution data during processing by said processor, and a display processor (40) for processing said high-resolution formatted data and said converted standard-formatted formatted data for display. 2. Процессор по п.1, в котором упомянутые декодированные и распакованные данные высокого разрешения представлены в блочном формате, упомянутые данные высокого разрешения являются совместимыми со стандартом экспертной группы по кинематографии MPEG2, упомянутый процессор отображения принимает видео данные в блочном формате, и упомянутый преобразователь преобразует упомянутые данные стандартного разрешения в блочный формат. 2. The processor according to claim 1, wherein said decoded and decompressed high-resolution data is presented in block format, said high-resolution data is compatible with the MPEG2 cinematography expert group standard, said display processor receives video data in block format, and said converter converts mentioned standard definition data in block format. 3. Процессор по п.1, в котором упомянутая входная цепь принимает пакетные сжатые данные. 3. The processor of claim 1, wherein said input circuit receives packet compressed data. 4. Процессор по п.1, в котором упомянутая память принимает данные на основе блоков и данные поля и кадра в формате растра. 4. The processor according to claim 1, wherein said memory receives block-based data and field and frame data in a raster format. 5. Процессор по п.2, дополнительно содержащий устройство (28) повторного сжатия для повторного сжатия упомянутых декодированных и распакованных в соответствии со стандартом MPEG2 данных перед запоминанием в упомянутой памяти. 5. The processor according to claim 2, further comprising a re-compression device (28) for re-compressing said data decoded and decompressed in accordance with the MPEG2 standard before storing in said memory. 6. Процессор по п.1, в котором упомянутый процессор отображения является программируемым для обеспечения выходного формата видео данных, совместимого с устройством отображения, соединенным с упомянутым процессором отображения. 6. The processor according to claim 1, wherein said display processor is programmable to provide an output video data format compatible with a display device coupled to said display processor. 7. Процессор по п.1, в котором упомянутая входная цепь включает вход (2) для приема данных формата стандарта MPEG2 и вход (4) для приема данных формата, отличного от стандарта MPEG2, упомянутый процессор (40) отображения включает преобразователь (56) блоков в строки для обработки данных блочного формата стандарта MPEG2 и преобразованных из строк в блоки данных не формата стандарта MPEG2, и упомянутая общая память (20) запоминает упомянутые данные формата стандарта MPEG2 и упомянутые данные, отличные от стандарта формата MPEG2, во время обработки упомянутой системой. 7. The processor according to claim 1, wherein said input circuit includes an input (2) for receiving data of the MPEG2 format and an input (4) for receiving data of a format other than the MPEG2 standard, said display processor (40) includes a converter (56) blocks into rows for processing data of block format of the MPEG2 standard and converted from rows to data blocks of non-MPEG2 format, and the said shared memory (20) stores the mentioned data of the MPEG2 format and the data other than the MPEG2 format during processing of the said systems Oh. 8. Процессор по п. 7, в котором упомянутая память принимает данные на основе блоков и данные поля и кадра в формате растра. 8. The processor of claim 7, wherein said memory receives block-based data and field and frame data in a raster format. 9. Процессор по п.1, содержащий первый маршрут обработки, связанный с упомянутой первой цепью (2) для приема информации формата стандарта MPEG2 декодер (16), соответствующий упомянутому декодеру, и упомянутый процессор (40) отображения, имеющий выход для передачи информации изображения в устройство отображения, второй маршрут обработки, связанный с упомянутой входной цепью, содержащей вход (4) для приема информации формата стандартного разрешения, преобразователь (22) строк в блоки и упомянутый процессор отображения, средство переключения для выборочной передачи информации отображения в упомянутый выход отображения через упомянутый первый и упомянутый второй маршруты обработки, и в котором упомянутая общая память (20) основана на блоках и соединяется с упомянутым первым и упомянутым вторым маршрутами обработки, упомянутый процессор отображения включает средство для изменения разрешения информации формата стандартного разрешения, и упомянутое средство переключения запоминает упомянутую информацию формата стандартного разрешения в упомянутой памяти во время обработки. 9. The processor according to claim 1, comprising a first processing route associated with said first circuit (2) for receiving MPEG2 format information, a decoder (16) corresponding to said decoder, and said display processor (40) having an output for transmitting image information to a display device, a second processing route associated with said input circuit comprising an input (4) for receiving standard resolution format information, a string to block converter (22) and said display processor, switching means for selecting transferring the display information to said output of the display through said first and said second processing routes, and in which said shared memory (20) is block based and connected to said first and said second processing routes, said display processor includes means for changing the resolution of the format information standard resolution, and said switching means stores said standard resolution format information in said memory during processing. 10. Процессор по п.9, в котором упомянутая память принимает данные на основе блоков и данные поля и кадра в растровом формате. 10. The processor of claim 9, wherein said memory receives block-based data and field and frame data in a raster format. 11. Способ обработки многоформатных видеосигналов, содержащий шаги приема сигнала, содержащего данные, подлежащие обработке (120), идентификации упомянутого принимаемого сигнала как одного из сигнала формата стандарта MPEG2 и сигнала формата стандартного разрешения (122), декодирования входного сигнала формата стандарта MPEG2 для создания данных блочного формата при приеме (124), предварительной обработки входного сигнала формата стандартного разрешения для создания данных блочного формата при приеме (126), приведения упомянутых передаваемых данных к формату, подходящему для отображения (128), запоминания упомянутых данных формата MPEG2 и упомянутых данных формата стандартного разрешения в общей памяти во время обработки, и передачи приведенных в соответствие с отображением данных в устройство (130) отображения. 11. A method for processing multi-format video signals, comprising the steps of receiving a signal containing data to be processed (120), identifying said received signal as one of a signal in MPEG2 format and a standard definition format signal (122), decoding an input signal in MPEG2 format to create data block format when receiving (124), preprocessing an input signal of standard definition format to create block format data when receiving (126), casting said transmitted data s to a format suitable for display (128), storing said MPEG2 format data and standard definition format of said data in the shared memory in the processing time and the transmission aligned with the data display device (130) display. 12. Способ по п.11, в котором упомянутый шаг предварительной обработки преобразует данные строчного формата или данные блочного формата. 12. The method of claim 11, wherein said preprocessing step converts row format data or block format data. 13. Способ по п.11, в котором упомянутый шаг приведения в соответствие преобразует данные блочного формата в данные строчного формата. 13. The method according to claim 11, in which said step of bringing into conformity converts the data of the block format into the data of the line format. 14. Способ по п. 11, в котором упомянутая память принимает данные на основе блоков и данные поля и кадра в формате растра. 14. The method of claim 11, wherein said memory receives block-based data and field and frame data in a raster format.
RU99115826/09A 1996-12-18 1997-12-15 Memory architecture for multiple-format video- signal processor unit RU2214066C2 (en)

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RU99115826/09A RU2214066C2 (en) 1996-12-18 1997-12-15 Memory architecture for multiple-format video- signal processor unit
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