RU96123900A - SPECIALIZED PROCESSOR AND METHOD OF ITS DESIGN - Google Patents
SPECIALIZED PROCESSOR AND METHOD OF ITS DESIGNInfo
- Publication number
- RU96123900A RU96123900A RU96123900/09A RU96123900A RU96123900A RU 96123900 A RU96123900 A RU 96123900A RU 96123900/09 A RU96123900/09 A RU 96123900/09A RU 96123900 A RU96123900 A RU 96123900A RU 96123900 A RU96123900 A RU 96123900A
- Authority
- RU
- Russia
- Prior art keywords
- application
- architecture
- command
- elements
- application elements
- Prior art date
Links
- 230000000875 corresponding Effects 0.000 claims 10
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000005755 formation reaction Methods 0.000 claims 2
- 230000011664 signaling Effects 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 1
Claims (27)
множество физических прикладных элементов, взаимно соединенных для совместного выполнения определенного задания,
набор прикладных команд, каждая из которых относится к соответствующему прикладному элементу, в котором по меньшей мере одна прикладная команда имеет в качестве аргументов время вызова, посредством чего эта команда вызывает свой соответствующий прикладной элемент в определенное время.1. The programmable architecture of a specialized processor, containing:
many physical application elements interconnected to jointly perform a specific task,
a set of application commands, each of which refers to a corresponding application element, in which at least one application command has a call time as arguments, whereby this command calls its corresponding application element at a specific time.
каждый прикладной элемент включает программируемый функциональный блок и
команда, имеющая время вызова в качестве аргумента, вызывает программируемый функциональный блок своего соответствующего прикладного элемента в определенное время.3. The architecture of claim 1, wherein
each application element includes a programmable function block and
a command having a call time as an argument calls the programmable function block of its corresponding application element at a specific time.
каждый функциональный блок имеет рабочее состояние и выключенное состояние, а
каждый прикладной элемент также содержит блок приведения в действие генератора тактовых импульсов для переключения своего функционального блока в рабочее состояние и выключенное состояние.13. The architecture of claim 3, wherein
each function block has an operating state and an off state, and
Each application element also contains a clock pulse generator driving unit for switching its functional block to the operating state and the off state.
интегральную схему, имеющую множество физических прикладных элементов, взаимосвязанных на шине команд (данных) хронирования для выполнения функций связи, применяемых в системе связи;
при этом некоторые прикладные элементы имеют:
логический блок прикладного элемента для выполнения заданной функции связи,
логический блок приведения в действие генератора тактовых импульсов для обеспечения соответствующего прикладного элемента сигналами хронирования и включения логического блока прикладного элемента в то время, когда он нужен, и
логический блок выборки интерфейса, позволяющий логическому блоку прикладного элемента принимать команды и данные от других прикладных элементов и отправлять их другим прикладным элементам по шине команд /данных/ хронирования,
и реагирующий на команду, относящуюся к соответствующему прикладному элементу,
причем каждая команда имеет:
аргумент команды для установки параметров управления прикладного элемента и
аргумент времени для определения времени вызова этого прикладного элемента.27. A programmable processor architecture for executing instructions in a communication system, comprising:
an integrated circuit having a plurality of physical application elements interconnected on the timing command (data) bus to perform communication functions used in a communication system;
however, some application elements have:
the logical unit of the application element to perform a given communication function,
the logic block of the actuation of the clock generator to provide the corresponding application element with timing signals and enable the logical unit of the application element at the time when it is needed, and
an interface fetch logical unit that allows the application unit logic unit to receive commands and data from other application elements and send them to other application elements via the command / data / timing bus,
and responding to a command related to the corresponding application element,
and each team has:
a command argument to set the control parameters of the application element and
a time argument to determine the time of invocation of this application element.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/243,963 | 1994-05-17 | ||
US08/243,963 US5623684A (en) | 1994-05-17 | 1994-05-17 | Application specific processor architecture comprising pre-designed reconfigurable application elements interconnected via a bus with high-level statements controlling configuration and data routing |
PCT/US1995/005964 WO1995031778A1 (en) | 1994-05-17 | 1995-05-17 | Application specific processor and design method for same |
Publications (2)
Publication Number | Publication Date |
---|---|
RU96123900A true RU96123900A (en) | 1999-02-10 |
RU2147378C1 RU2147378C1 (en) | 2000-04-10 |
Family
ID=22920817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU96123900A RU2147378C1 (en) | 1994-05-17 | 1995-05-17 | Special-purpose processor |
Country Status (8)
Country | Link |
---|---|
US (1) | US5623684A (en) |
EP (1) | EP0760128A4 (en) |
JP (1) | JP3202750B2 (en) |
KR (1) | KR100358631B1 (en) |
CN (1) | CN1099636C (en) |
AU (1) | AU2636895A (en) |
RU (1) | RU2147378C1 (en) |
WO (1) | WO1995031778A1 (en) |
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US6138229A (en) * | 1998-05-29 | 2000-10-24 | Motorola, Inc. | Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units |
US6968514B2 (en) | 1998-09-30 | 2005-11-22 | Cadence Design Systems, Inc. | Block based design methodology with programmable components |
JP2002526908A (en) * | 1998-09-30 | 2002-08-20 | ケイデンス デザイン システムズ インコーポレイテッド | Block-based design method |
JP2000315222A (en) | 1999-04-30 | 2000-11-14 | Matsushita Electric Ind Co Ltd | Database for designing integrated circuit device and designing method for integrated circuit device |
JP4077578B2 (en) | 1999-04-30 | 2008-04-16 | 松下電器産業株式会社 | Integrated circuit device design method |
US7062769B1 (en) | 1999-07-07 | 2006-06-13 | National Semiconductor Corporation | Object-oriented processor design and design methodologies |
JP3974300B2 (en) | 1999-11-18 | 2007-09-12 | 松下電器産業株式会社 | IP-based LSI design system and design method |
US7080183B1 (en) * | 2000-08-16 | 2006-07-18 | Koninklijke Philips Electronics N.V. | Reprogrammable apparatus supporting the processing of a digital signal stream and method |
US6630964B2 (en) * | 2000-12-28 | 2003-10-07 | Koninklijke Philips Electronics N.V. | Multi-standard channel decoder for real-time digital broadcast reception |
US20020112219A1 (en) * | 2001-01-19 | 2002-08-15 | El-Ghoroury Hussein S. | Matched instruction set processor systems and efficient design and implementation methods thereof |
US20020116166A1 (en) * | 2001-02-13 | 2002-08-22 | El-Ghoroury Hussein S. | Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set process systems using interconnected design components |
US7055019B2 (en) | 2001-02-13 | 2006-05-30 | Ellipsis Digital Systems, Inc. | Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms |
US6938237B1 (en) | 2001-06-29 | 2005-08-30 | Ellipsis Digital Systems, Inc. | Method, apparatus, and system for hardware design and synthesis |
EP1286279A1 (en) * | 2001-08-21 | 2003-02-26 | Alcatel | Configuration tool |
US7266487B1 (en) | 2001-08-29 | 2007-09-04 | Ellipsis Digital Systems, Inc. | Matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs |
JP2003316838A (en) * | 2002-04-19 | 2003-11-07 | Nec Electronics Corp | Design method for system lsi and storage medium with the method stored therein |
JP4202673B2 (en) * | 2002-04-26 | 2008-12-24 | 株式会社東芝 | System LSI development environment generation method and program thereof |
US7131097B1 (en) * | 2002-09-24 | 2006-10-31 | Altera Corporation | Logic generation for multiple memory functions |
WO2004040445A1 (en) * | 2002-10-29 | 2004-05-13 | Freescale Semiconductor, Inc. | Method and apparatus for selectively optimizing interpreted language code |
US7380151B1 (en) | 2002-12-11 | 2008-05-27 | National Semiconductor Corporation | Apparatus and method for asynchronously clocking the processing of a wireless communication signal by multiple processors |
US7016695B1 (en) | 2002-12-11 | 2006-03-21 | National Semiconductor Corporation | Apparatus and method for processing a deterministic data flow associated with a wireless communication signal |
CN1315037C (en) * | 2002-12-27 | 2007-05-09 | 联想(北京)有限公司 | Virtual information flow bus interface and its data processing method |
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US7193553B1 (en) | 2004-12-07 | 2007-03-20 | National Semiconductor Corporation | Analog to digital converter with power-saving adjustable resolution |
US7205923B1 (en) | 2004-12-07 | 2007-04-17 | National Semiconductor Corporation | Pipelined analog to digital converter that is configurable based on mode and strength of received signal |
US6980148B1 (en) | 2004-12-07 | 2005-12-27 | National Semiconductor Corporation | Pipelined analog to digital converter that is configurable based on wireless communication protocol |
US9075623B2 (en) * | 2012-01-18 | 2015-07-07 | International Business Machines Corporation | External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit |
WO2013147830A1 (en) * | 2012-03-30 | 2013-10-03 | Intel Corporation | Decoding wireless in-band on-channel signals |
JP6480953B2 (en) * | 2014-05-16 | 2019-03-13 | リニアー テクノロジー エルエルシー | Configuration of signal processing system |
US9747197B2 (en) | 2014-05-20 | 2017-08-29 | Honeywell International Inc. | Methods and apparatus to use an access triggered computer architecture |
US10353681B2 (en) | 2014-05-20 | 2019-07-16 | Honeywell International Inc. | Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture |
CN105435455A (en) * | 2016-01-26 | 2016-03-30 | 青岛大学 | Adjustable counting seesaw |
CN111988417B (en) * | 2020-08-28 | 2022-07-19 | 电子科技大学 | Communication control method of terminal of Internet of things |
CN112463723A (en) * | 2020-12-17 | 2021-03-09 | 王志平 | Method for realizing microkernel array |
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JPS62189739A (en) * | 1986-02-17 | 1987-08-19 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS63308343A (en) * | 1987-06-10 | 1988-12-15 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
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CN1016815B (en) * | 1988-05-20 | 1992-05-27 | 武汉市半导体器件厂 | Universal test, control module |
US5173864A (en) * | 1988-08-20 | 1992-12-22 | Kabushiki Kaisha Toshiba | Standard cell and standard-cell-type integrated circuit |
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JP2791243B2 (en) | 1992-03-13 | 1998-08-27 | 株式会社東芝 | Hierarchical synchronization system and large scale integrated circuit using the same |
-
1994
- 1994-05-17 US US08/243,963 patent/US5623684A/en not_active Expired - Fee Related
-
1995
- 1995-05-17 KR KR1019960706511A patent/KR100358631B1/en not_active IP Right Cessation
- 1995-05-17 CN CN95194008A patent/CN1099636C/en not_active Expired - Fee Related
- 1995-05-17 AU AU26368/95A patent/AU2636895A/en not_active Abandoned
- 1995-05-17 EP EP95921243A patent/EP0760128A4/en not_active Withdrawn
- 1995-05-17 RU RU96123900A patent/RU2147378C1/en active
- 1995-05-17 WO PCT/US1995/005964 patent/WO1995031778A1/en active Application Filing
- 1995-05-17 JP JP52979295A patent/JP3202750B2/en not_active Expired - Fee Related
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