RU96107418A - PERFORMING THE DATA PROCESSING INSTRUCTIONS - Google Patents

Claims (9)

1. A data processing device (100, 110, 120), in which serial data processing instructions are executed in a pipelined manner, comprising a memory access device (110) for accessing a data memory in response to one or more of these instructions, called an access device to the memory contains a device for detecting whether each memory access is valid, and a condition checking device (200) sensitive to the operating state of the data processing device that was created by the previous executed instructions, and valid during the execution of each instruction, to detect whether this instruction can be executed, characterized in that it contains a condition monitoring device (230, 240) sensitive to said memory access device (110) and to said condition checking device (200) , to prevent the full execution of the current instruction, if either the named memory access device (110) determines that the memory access initialized by the current instruction is invalid, or the said condition checking device (200) redelyaet that the said current instruction can not be executed.  2. The device according to claim 1, characterized in that it contains one or more valid flags (NZCV) for storing data indicating the current operating state of the data processing device, each instruction includes a condition code (bits 28 to 31) that defines the state of the named active flags required for this instruction to be executed, the named condition checking device (200) is able to compare the required state of the active flags specified with the named condition code in each instruction with the actual state iem said processing flags. 3. The device according to claim 2, characterized in that the four named flags respectively indicate:
(i) whether the previous data processing operation generated by said data processing device a negative result (N);
(ii) whether the previous data processing operation by the named device generated a null result (Z);
(iii) whether the carry bit was set by a previous operation of the named data processing device (C); and
(iv) whether arithmetic overload occurred during a previous operation of the named data processing device (y).  4. A device according to any one of claims 1 to 3, characterized in that said memory access device (110) comprises a device for transmitting a memory address to said data memory (120) and a device for subsequent data transmission to said data memory or for receiving data from the named data memory.  5. Device according to any one of the preceding paragraphs, characterized in that said memory access device (110) is capable of generating a control interrupt signal (150) to indicate that memory access is invalid, said condition checking device (200) is capable of generating a control signal unsuccessful condition (220) to indicate that the named current instruction cannot be executed, and the named data processing device comprises a device for combining said control interrupt signal and said control a signal of an unsuccessful condition for supplying to said condition monitoring device (240).  6. The device according to claim 5, characterized in that the said device (230) for combining contains a logical element OR.  7. The device according to any one of the preceding paragraphs, characterized in that the data processing operations are controlled by a timer signal.  8. An integrated circuit containing a data processing device according to any one of the preceding paragraphs.  9. A data processing method in which sequential data processing instructions are executed in a pipelined manner, the method comprises the following steps: access (110) to the data memory in response to one or more of these instructions, detecting (110) how much each memory access is possible and detecting (200), during the execution of each instruction, whether the execution of this instruction is possible depending on the operating state of the named data processing device specified by the previous executed instructions, and different I am at the stage of preventing (230, 240) the complete execution of the current instruction if it is determined that either this memory access, initialized by the previous instruction, is not possible, or that this named current instruction cannot be executed.