RU58825U1 - ANALOG-DIGITAL CONVERTER - Google Patents

Abstract

The utility model relates to electrical measurement and computer technology and can be used in control systems, information collection and processing. The essence of the utility model is that to expand the functionality, increase accuracy or speed or reduce complexity, the analog-to-digital converter, in comparison with the prototype, additionally contains a sampling-storage circuit, a delay element, a unit for determining the sign and inverting negative voltages. 4 ill. 2 P. f-ly.

Description

The technical field to which the utility model relates.

The utility model relates to electrical measurement and computer technology and can be used in control systems, information collection and processing.

State of the art

A known analog-to-digital converter (ADC) with pulse-modulation time, comprising a serially connected input device, a sawtooth voltage generator, generating a linearly decreasing voltage pulse with an amplitude equal to the measured one, a voltage comparison unit comparing the voltage from the output of the sawtooth voltage generator with a certain threshold voltage , trigger, key and counter, as well as a control unit and a reference frequency generator; the trigger controls the key, through which the pulses from the pulse generator of the reference frequency are fed to the counter, and the control circuit is designed to generate signals for the start of conversion and reset the counters; information at the output of the counter at the end of the conversion cycle is the digital equivalent of the measured voltage. (Bogdanov V.V. et al. Digital electrical measuring devices. / Under the editorship of Bakhtiarov GD M: Sov. Radio, 1980).

The disadvantage of this device is the inability to perform analog-to-digital conversion of bipolar signals, low speed.

The closest in technical essence and the achieved positive effect and adopted by the authors for the prototype is an analog-to-digital Converter, containing sequentially

included input device, sawtooth generator and comparison unit, as well as a control unit, a reference frequency generator, an arithmetic adder and a battery; information input of the battery is connected to the output of the adder, the input of the first operand of the adder is connected to the output of the comparison unit, the input of the second operand of the adder is connected to the output of the battery, one of the outputs of the control unit is connected to a sawtooth generator, the other to the reference frequency generator, the output of which is connected to the control battery input, and the third to the battery installation input; the comparison unit is designed as a multi-threshold device, and the battery output is the output of the device. (RF patent, No. 2110886 from 10/06/93).

The disadvantage of this device is the inability to perform analog-to-digital conversion of bipolar signals and signals of negative polarity.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to expand the functionality, increase the accuracy or speed, or reduce the complexity of the analog-to-digital converter.

The expansion of functionality consists in providing the possibility of analog-to-digital conversion of not only unipolar positive, but also unipolar negative and bipolar signals.

The technical result is achieved by the fact that in a known analog-to-digital Converter, containing serially connected sawtooth voltage generator and a comparison unit, as well as a control unit, a reference frequency generator, an arithmetic adder and a battery, the information input of which is connected to the output of the arithmetic adder, the input of the first arithmetic operand

the adder is connected to the output of the comparison unit, the input of the second operand of the arithmetic adder is connected to the output of the battery, the second output of the control unit is connected to a reference frequency generator, the output of which is connected to the control input of the battery, and the third to the installation input of the battery; the comparison unit is designed as a multi-threshold device, and the battery output is a group of (m-1) (bits of the converted signal module code) device outputs, a sampling-storage scheme, a unit for determining the sign and inversion of negative voltages, a delay element, and the analog input of the device are connected with the first input of the sample-storage circuit, the second input of which is connected to the first output of the control unit and the input of the delay element, the output of which is connected to the control input of the sawtooth generator, the output of the sample-storage circuit is connected to the input of the negative sign sign-in and negative-inversion unit, the first output of which is the m-th output (the sign bit of the output codogram) of the device, and the second output through the sawtooth generator is connected to the signal input of the comparison unit, to the first and second the inputs of the reference voltage of which is supplied, respectively, the reference voltage of high and low levels.

The unit for determining the sign and inverting negative voltages contains two analog switches, an inverting DC amplifier, a voltage comparator, an inverter; the input of the unit for determining the sign and inverting negative voltages is connected to the inputs of the second analog switch, the inverting DC amplifier and the non-inverting input of the voltage comparator, the output of the latter is connected to the inverter input, the control input of the second analog switch and the first output of the unit for determining the sign and inverting negative voltages, the output of the inverting a DC amplifier is connected to the input of the first analog switch, the output of which, together with the output of the second analog switch Braz second output character determining unit

and inverting negative voltages.

Brief Description of the Drawings

Figure 1 shows the structural diagram of the device analog-to-digital Converter.

Figure 2 shows the structural diagram of the unit for determining the sign and inverting negative voltages.

Figure 3 and 4 are timing diagrams explaining the operation of the device.

Utility Model Implementation

An analog-to-digital converter consists of a sampling-storage circuit (TSW) 1, the first input of which is connected to the analog input of the device, the second input of TSW 1 is connected to the first output of the control unit (BU) 2 and the input of the delay element (EZ) 3, the output of which is connected to the control input of the sawtooth voltage generator (GPN) 4; the output of TSW 1 is connected to the input of the unit for determining the sign and inverting negative voltages (BOS AND ION) 5, the first output of which is the m-th output (the sign bit of the output codogram) of the device, and the second output through GPN 4 is connected to the signal input of the comparison unit (BS ) 6, the first and second inputs of the reference voltage of which is supplied, respectively, the reference voltage of high and low levels; the BS output 6 is connected to the input of the first operand of the arithmetic adder (AC) 7, the output of which is connected to the information input of the battery 8, the output of which is connected to the input of the second operand of the AC 7; the second output of the control unit 2 is connected to the reference frequency generator (GOCH) 9, the output of which is connected to the control input of the battery 8, and the third output of the control unit 2 to the installation input of the battery 8; BS 6 is designed as a multi-threshold device, and the output of the battery 8 is a group of (m-1) (bits

converted signal module code) of the device outputs.

TSW 1 is designed to select the voltage level of the input signal at the command of BU 2 and store this level during the conversion time.

The block diagram of the unit for determining the sign and inverting negative voltages (BOS AND ION) 5 is shown in figure 2.

The input BOS AND ION 5 is connected to the inputs of the second analog key (AK) 10, the inverting DC amplifier (IUPT) 11 and the non-inverting input of the voltage comparator (KN) 12, the output of the latter is connected to the input of the inverter 13, the control input of the second analog key (AK) 10 and the first output of BOS AND ION 5, the output of IUPT 11 is connected to the input of the first AK 14, the output of which, together with the output of the second AK 10 form the second output of BOS AND ION 5.

BOS AND ION 5 is designed to determine the sign (polarity) of the voltage level of the input signal and relay the signal further with a unit transmission coefficient in the case of its positive polarity, and in the case of negative polarity, additionally expose the translated signal to the inversion.

BOS AND ION 5 works as follows.

KN 12, depending on the polarity of the input signal, forms a positive or negative threshold, which plays the role of a sign discharge (a logical unit or zero, arriving at the first output of the BOS AND ION 5, and subsequently arriving at the first output (sign discharge) of the device, and the same control action entering the AK 14 through the inverter 13, and AK 10 directly, that is, the state of AK 14 and AK 10 are reciprocal.

In the case of a positive polarity signal entering the input BOS AND ION 5:

- KN 12 forms a positive potential;

- the first output BOS AND ION 5 receives a signal with a logic level

units;

- AK 10 is transferred to the open state, AK 14 is closed;

- the input signal is transmitted to the second output of the BOS AND ION 5.

In the case of a negative polarity signal entering the input BOS AND ION 5:

- KN 12 forms a negative potential;

- the first output BOS AND ION 5 receives a signal with a logic level of zero;

- AK 10 is put into a closed state, AK 14 is open;

- the input signal inverted IUPT 11 is transmitted to the second output of the BOS AND ION 5.

Thus, BOS AND ION 5 actually forms the sign and module of the broadcast signal.

BS 6 is a comparator with 2 ⁿ comparison thresholds that evenly divide the measurement range (U _OB -U _OH ), where n> 0, and a unitary (thermometric) code converter, which takes place at the output of BS 6 comparators, into binary n-bit code (parallel ADC). The number of discharges of accumulator 8 and AC 7 is n + N, and 2 ^N is the number of summing cycles (the number of terms that form the result in the accumulator). Moreover, the ADC conversion time is actually equal to the time of the linearly decreasing voltage change between the two comparison thresholds of the multi-threshold BS 6.

The operation of the device is illustrated by the timing diagrams shown in figure 3 and 4. The device operates as follows.

On the analog input of the device receives the measured signal U _BX (figa).

At time t ₀ BU 2 generates a start pulse ("Start") of duration t ₀ ÷ t ₁ (Fig.3.b).

The pulse formation "Start" provides the memorization of the input signal level U _BX CBX 1. At the same time, BOS AND ION 5

starts to analyze the level of the signal stored by the TSW 1. By the time t ₁ (Fig.3.b), the TSW 1 completes the memorization process. In the General case, the interval t ₀ ÷ t ₁ (Fig.3.b) is calculated in units of ns. (In the AD9059 ADC, the aperture time is 2.7 ns. (Http://www.gaw.ru/pdf/AD/adc/ad9059.pdf), the sampling time of the built-in sampling-storage circuit is 1 ns. (Www.compitech. m / html.cgi / arhiv / 00_01 / stat_34.htm)).

By the time t ₂ (Fig.3.c), the voltage at the first (signal sign of the polarity of the input signal) and second (voltage module of the input signal level) outputs BOS AND ION 5 is stabilized. In the General case, the interval t ₁ ÷ t ₂ (Fig.3.v) is calculated in fractions of ns. It is determined primarily by the delay created by IUPT 11 (moreover, by the time of an additional increase in the transition characteristic of IUPT 11 from time t ₁ to time t ₂ ), (for example, the super-fast amplifier AD8009 is characterized by a slew rate of the output signal of 5500 V / μs, THS3001 - 6500 V / μs. (G. Volovich. Broadband integrated amplifiers. Http: //www.PLATAN.ru/shem/pdf/str27-1sx.pdf)), since the speed of modern comparators is comparable to the speed of the TSW, and by the time t ₂ AK 14 and 10 are already in a predetermined state. In other words, the delay introduced by BOS and ION 5 is negligible.

At time 1 h (Fig. 3.c, d), - time T _N (Fig. 4), an impulse is supplied from the output of the EZ 3 to the control input of the GPN 4, allowing the GPN 4 to start generating a voltage that decreases linearly from the level, equal to the measured voltage U _BX . At the same time, the GOCH 9 starts and the battery 8 is set to zero. The voltage from the output of the ГПН 4 is supplied to the input 2 of the ^n- threshold BS 6, which contains 2 ⁿ comparators. During the measurement, equal to 2N periods of the clock, occurs = 2 ^N acts:

- comparison of the output voltage of the GPN 4 with the thresholds of a multi-threshold BS 6;

- summation of the result in AC 7 with the contents of the battery 8;

- recording the result in the battery 8.

The measurement ends at time T _To (figure 4), - time t ₃ (Fig.3.v, g). The pulse period GOCH 9 T _O is chosen so that the measurement time equal to T _K -T _N = K · T _O would be equal to the time of the voltage change at the input of BS 6 between two adjacent thresholds.

For definiteness, for example, suppose that n = 6 and N = 4, i.e. the multi-threshold comparison device has 64 comparison levels, and the number of measurement steps is K = 2 ^N = 16. The measurement begins at time T _N , and ends at time T _To (figure 4). The measurement time is chosen equal to the time of a linearly decreasing voltage change between two adjacent levels of comparison and is equal to 16 · T _O , where T _O is the period of GOCH 9. As a result of the measurement, the number A equal to:

A = K ₁ · 62 + K ₂ · 61

wherein K ₁ + K ₂ = 16. This number A is the result of the conversion. When the measured voltage U _BX changes, the ratio between the amounts of K ₁ and K ₂ in the resulting sum A changes. For example, the results of two measurements at the resolution boundary can be equal to:

And ₁ = 10 · 62 + 6 · 61 = 986 with K ₁ = 10 and K ₂ = 6.

And ₂ = 9 · 62 + 7 · 61 = 985 with K ₁ = 9 and K ₂ = 7.

Non-observance of the exact equality K · T _O = T _K -T _N leads to an increase in the differential nonlinearity of the converter, and inaccuracies in inter-threshold voltages (U _por.i -U _por.i-1 ) lead to an increase in the integral nonlinearity of the converter.

Thus, the process of converting a voltage supplied from the second output PDO AND ION 5 in code at time T _R (4), - time

t ₃ (Fig.3.v, d) will end.

The output of the device will receive the result of the conversion:

- from the first output of BOS AND ION 5 - code mark of polarity of the input analog signal;

- from the outputs of the battery 8 is the code level of the voltage module of the input signal.

In other words, at time t ₃ (Fig. 3.c, d) an m-bit code is generated at the output of the device. The senior bit of which carries information about the polarity of the input signal, the remaining (m-1) bits are the code level of the voltage module of the input signal.

Introduction of TSW 1, EZ 3 and BOS AND ION 5, due to the unconditional fulfillment of the condition

in fact, it does not introduce additional delay into the conversion process, that is, it does not reduce the performance of the ADC, and moreover, their use helps to expand the functionality, increase accuracy or speed, or reduce the complexity of the device.

The expansion of functionality consists in providing the possibility of analog-to-digital conversion of not only unipolar positive signals, as in the prototype, but also unipolar negative and bipolar signals.

Introduction of TSW 1, EZ 3 and, first of all, BOS and ION 5, in the case of analog-to-digital processing of bipolar signals, due to the possibility of recalculating the dynamic range of the input signals and the quantization step of BS 6 (doubling them), taking into account:

a) preserving the complexity of the device (bit depths of BS 6, AC 7 and battery 8) leads to a significant increase in the accuracy of the analog-to-digital conversion of input signals due to an increase in the noise immunity of the comparators included in BS 6 (an actual half reduction of the quantization step);

b) maintaining the specified accuracy of the analog-to-digital conversion of the input signals, leads to:

1) to a significant simplification of the device due to the possibility of reducing the bit depth of BS 6, AC 7 and battery 8 per 1 discharge (in the case of n = 6, these are 32 high-precision comparators in BS 6);

2) to a significant increase in the speed of the device due to the possibility of reducing the capacity of the AC 7 and the battery 8 by 1 discharge (decreasing N by 1, that is, in the case N = 4, this corresponds to a decrease in the duration of the analysis interval from 16 · T _O to 8 · T _O ).

In any case, the introduction of BOZ AND ION 5 into the device, during analog-digital processing of bipolar signals, leads to an increase in the ADC bit by one bit (the highest bit of the code, which carries information about the polarity of the input signal, forms BOZ AND ION 5).

That is, there is both an extension of functionality and an increase in accuracy or speed or a decrease in the complexity of the device.

Claims (2)

1. An analog-to-digital converter containing a serrated voltage generator and a comparison unit, as well as a control unit, a reference frequency generator, an arithmetic adder and a battery, a battery information input connected to the output of the arithmetic adder, an input of the first operand of the arithmetic adder connected to the output of the comparison unit , the input of the second operand of the arithmetic adder is connected to the battery output, the second output of the control unit is connected to the reference frequency generator, you One of which is connected to the control input of the battery, and the third to the installation input of the battery, the comparison unit is designed as a multi-threshold device, and the battery output is a group of (m-1) (code bits of the converted signal module) device outputs, characterized in that in the device a sampling-storage circuit, a block for determining the sign and inverting negative voltages, a delay element, the analog input of the device is connected to the first input of the sampling-storage circuit, the second input of which is connected to the output of the control unit and the input of the delay element, the output of which is connected to the control input of the sawtooth generator, the output of the sampling-storage circuit is connected to the input of the sign detection and negative voltage inverting unit, the first output of which is the m-th output (the sign bit of the output codegram) of the device and the second output through the sawtooth generator is connected to the signal input of the comparison unit, the first and second inputs of the reference voltage of which are supplied respectively e voltage high and low. 2. The analog-to-digital Converter according to claim 1, characterized in that the unit for determining the sign and inverting negative voltages contains two analog switches, an inverting DC amplifier, a voltage comparator, an inverter, the input of the unit for determining sign and inverting negative voltages is connected to the inputs of the second analog a key, an inverting DC amplifier and a non-inverting input of the voltage comparator, the output of the latter is connected to the inverter input, the control input of the second analog switch, and moat output determination unit and to invert the sign of negative voltage, the DC output of the amplifier is connected to the input of the first analog switch, the output of which together with the output of the second analog switch constitute the second output unit, and determining the sign inverting negative voltages.