RU2815599C1 - Method of executing programs by processor using table of addresses of speculation on data - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to computer engineering. Method of executing programs by a processor using a table of addresses of speculation according to data includes a computing system comprising a processor with a VLIW architecture, which implements a DAM or ALAT mechanism, supporting the execution of speculative reading operations with entering into the table of addresses of speculation by data, checking and normal readings, a compiler, which translates the program code to the processor, wherein when executing the program code, the processor for several read operations at a common address performs only one common speculative read operation and one common verification read operation, and storing data from the remaining readings for the compensating code is carried out without using speculative operations.

EFFECT: faster execution of the final machine code on architectures with a dynamic mechanism for breaking dependencies.

1 cl, 3 dwg

Description

The invention relates to the field of computer technology and is used to optimize program code.

One of the ways to increase the speed of code by using the capabilities of the architecture of computing systems is to plan the simultaneous execution of several operations in one clock cycle, that is, to increase the parallelism of the code.

Increasing the speed of code operation by an optimizing compiler is achieved to a large extent by planning the parallel execution of operations on the devices of computing systems. However, the lack of information about the independence of reads and writes significantly limits the ability to change the execution order. In this case, you cannot swap read and write executions, delete repeated reads and writes at the same address, or simultaneously perform dependent operations that come before the write and after the read. When dynamically scheduling the execution of operations, information about the difference between read and write addresses can be detected already during code execution, which allows for quite efficient dynamic planning of the execution of operations. In the case of static planning, the main available methods for identifying address independence are the use of various methods of pointer analysis and the use of additional rules for working with pointers (restrict, strict aliasing), information about compliance with which in the source code is transmitted by the user using special options or pragmas. Despite the fact that pointer analysis is an extensive and developed set of methods, its capabilities are very limited in the case of passing pointers between procedures, the presence of global variables and the use of other constructs typical of C and C++ programs, and in the case of using irregularly calculated addresses from one type of object.

To ensure higher parallelism at the level of operations in processors with static scheduling, a mechanism has been developed to support dynamic breaking of dependencies at the device level, allowing some operations to be performed speculatively, that is, in advance. And in the event of subsequent receipt of information that a record was made at the address for reading, re-perform some of the operations using the correct value. This mechanism is implemented in Elbrus processors with VLIW architecture (DAM or Disambiguation of Accessing Memory), as well as, with minor differences, for Itanium architecture (Advanced Load Address Table or ALAT).

In the prior art, a method is known for using DAM and ALAT (prototype) for speculative code execution using dynamic dependency breaking, which consists of the following: instead of the original read to the potentially conflicting record, a speculative read operation (speculative load) is built, and in place of the original read operation, a check read operation (check load). In this case, the address of the initial reading at the hardware level is entered into a special table, and the consumers of the initial reading receive as input the data read by speculative reading. If a conflict later occurs and the data at the speculative read address is changed, this will affect the test read operation, which checks the data in the table. As a result, a transition will be made to a code with repeated execution of part of the operations (recovery code or compensating code), in which the data read by the check read operation will be used, and then a return transition to the check point will occur. This method is described in the “Guide to Effective Programming on the Elbrus Platform”, Neiman-zade M.I., Korolev S.D. © 2020, MCST JSC, pp. 90-91.

The disadvantage of this method is that instead of each reading of the source code, 2 reading operations are performed - a speculative reading operation and a verification reading operation, which slows down execution even in the absence of a conflict in addresses. In addition, there is a limit on the number of available speculative reads, since they need to be tracked in a table limited in size (32 for both architectures described above), and if this size is not enough, unnecessary data dependencies may remain, which will also negatively affect the speed of the code. .

The purpose of the method is to increase the speed of code execution by reducing the number of operations created when using the speculative reading mechanism, as well as by ensuring the applicability of the speculative execution mechanism for a larger number of source code readings.

This goal is achieved due to the fact that when executing program code, the processor performs only one common speculative read operation and one common verification read operation for several reading operations at a common address, and saves data from the remaining readings for the compensating code without using speculative operations.

Brief description of drawings and diagrams illustrating the proposed method and its application in the machine code planning process:

Fig. 1 - Scheme of the code compilation process with optimization.

Fig. 2 - Scheme of speculative code execution indicating the point of difference from the prototype.

Fig. 3 - Comparative diagram of the operation of the prototype and the proposed method.

After initial processing of the source code, the compiler generates an intermediate representation and also receives information about the presence of various computing devices, taking into account which it can make decisions about using the speculative planning mechanism (Fig. 1). At the stage of planning operations of hypernodes formed during the compilation process, in the event of potential conflicts between write and read operations, it is necessary to check for the presence of several read operations at the same address (Fig. 2). If they are found, then it is proposed to apply to them the method of executing programs by the processor using a data speculative address table. For other readings, the traditional method (prototype) is used.

The implementation of a method for executing programs by a processor using a data speculative address table is as follows:

1) One speculative read operation is constructed at a common address before write operations that potentially conflict with reads.

2) Instead of the results of the original reads for all corresponding consumers, the result of the constructed speculative read is used in the main code (not compensating).

3) At the point of the most recent initial reading at the common address, a verification read operation is constructed; at all other reading points at the common address, ordinary (non-speculative) readings are constructed, the result of which will be used in the general compensating code (Figure 3).

4) A compensating code is built for all speculatively executed operations. In it, for the read consumer (use) that used the result of the last read, the result of the test read is used. For other consumers, the results of the corresponding routine readings are used.

When applying the described method to n initial reads at a common address, 1 speculative read operation (speculative load), 1 check read operation (check load) and (n-1) regular read operation (load) are built, that is, a total of n+1 read operations . In this case, only one record is created in the table (DAM or ALAT) for all n source reads.

In the case of using a prototype for n initial reads at a common address, n speculative read operations and n test reads are constructed, that is, 2*n read operations. In this case, in the table (DAM or ALAT), for each initial read, its own record is created, that is, for n readings, n records are created.

In total, the application of the described method for each group of n readings at a common address allows, in comparison with the prototype, to reduce the total number of required read operations from 2*n to (n+1) operations, as well as to reduce the use of a table (DAM or ALAT) from n records to one. Reducing the total number of read operations allows for faster code execution due to fewer calculations required. Reducing the use of the table allows you to plan the speculative execution of more readings of the source code compared to the prototype, that is, speed up the execution of the code by increasing its speculativeness.

The developed method makes it possible to minimize the use of speculative reading operations and operations of checking the reading result, which increases the speed of execution of the final machine code on architectures with a dynamic mechanism for breaking dependencies such as DAM or ALAT.

Claims (1)

A method for executing programs by a processor using a table of data speculative addresses, including a computer complex containing a processor with VLIW architecture, implementing a DAM or ALAT mechanism that supports the execution of speculative reading operations with entry into the data speculative address table, verification and regular reading, a compiler that translates program code to the processor, characterized in that when executing the program code, the processor for several read operations at a common address performs only one common speculative read operation and one common verification read operation, and saves data from the remaining readings for the compensating code without using speculative operations.

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