RU2790533C1 - Data processing and storage device - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to computer technology. The data processing and storage device consists of a system on a chip containing a cluster of general-purpose processors, a cluster of DSP processors and hardware blocks for encoding and decoding digital video streams, as well as a supervisor with a trusted loading and control loop that monitors the physical state of system-on-chip components and remote control of the device.

EFFECT: providing improved performance, reliability and security of the data processing and storage device.

1 cl, 1 dwg

Description

The invention relates to the field of digital information processing, namely to data processing and storage devices, and can be used for processing and storing streaming audio and video data of access control and management systems, as well as intelligent computer vision systems.

The claimed device performs parallel reception of streaming digital information (for example, video and audio information) from several sources, software processing of the received information (for example, compression, selection of relevant information, identification of objects) in accordance with a given algorithm and storage of information on non-volatile media in the required format ( e.g. in database format, event log).

Closest to the claimed invention is a data processing and storage device described in the utility model patent of the Russian Federation No. 184681, containing a controller, N solid-state disks (HDD) connected by inputs / outputs to the controller, characterized in that it additionally includes a cluster of 1U servers as part of a network adapter with compression support, a central processing unit (CPU), the first input/output of which is connected to the second input/output of a network adapter with compression support, the third input/output is connected to the first input/output of the controller, a programmable logic integrated circuit FPGA, the first the input/output of which is connected to the second input/output of the CPU, the graphics processing unit GPU, the first input/output of which is connected to the fourth input/output of the CPU; a switch, the second input/output of which is connected to the second input/output of the controller, the third input/output is connected to the first input/output of the network adapter with compression support, and the first input/output is the input/output of the entire device. This data processing and storage device is chosen as a prototype of the claimed invention.

The disadvantages of the prototype device are the impossibility of changing the information compression algorithms without reprogramming the FPGA chip and the lack of means of monitoring the integrity of the software of the central processor. The impossibility of changing information compression algorithms without reprogramming the FPGA chip makes it difficult to use the device in systems that require adaptability (computer vision systems, self-learning systems), that is, it narrows the functionality and scope of the device. The lack of software integrity control and CPU health parameters reduce the degree of protection of the device from unauthorized actions and the reliability of the device as a whole.

The technical result of the invention is the creation of a data processing and storage device with an expanded scope, increased performance, reliability and security, through the use of a system on a chip, which contains a cluster of general purpose processors, a cluster of DSP processors and hardware blocks for encoding and decoding digital video streams; and also through the use of a supervisor with a trusted boot and control loop that provides monitoring of the physical state of system-on-chip components (monitoring of supply voltages and chip temperature), remote device management (integrity control and software updates, reboot, power on and off, logging of events ).

The set technical result is achieved by creating a data processing and storage device containing a system on a chip 2, which is connected to a group of drives 1 HDD, with a power supply 21, with DDR RAM 13, with a reprogrammable ROM 12 of the eMMC type, with a reprogrammable ROM 11 of the FLASH type SPI, with an operating temperature and voltage monitor 14, which is connected to a supervisor 15, which is connected to a power standby unit 22, as well as to a FLASH SPI type reprogrammable ROM 11, and to a system-on-chip 2, which contains an Ethernet controller unit 4, which is connected with a cluster 5 of general purpose processors, which is connected to a DDR RAM 13, with an eMMC flash ROM 12, with a FLASH SPI flash ROM 11, with a SATA controller 3, with a cluster 6 of DSP processors, with a video data codec 7, with the first controller 8 interface SPI and with the first controller 9 interface UART, and the supervisor 15 contains the controller 20 Ethernet, which is connected to the central processor 16 CPU, which is connected to the second UART interface controller 17, to the second SPI interface controller 18, and to the I/O controller 19 10, which is connected to the RESET block 10 and to the operating temperature and voltage monitor 14, which is connected to the first interface controller 9 UART, which is connected to the second controller 17 of the UART interface, and the second controller 18 of the SPI interface is connected to the first controller 8 of the SPI interface and to the reprogrammable ROM 11 of the FLASH SPI type, and

- system-on-chip 2, configured to receive, process information and write the processed information to a group of drives 1 HDD;

- cluster 5 of general-purpose processors is configured to implement algorithms for processing data streams, generating information for recording to a group of drives 1 HDD, as well as generating information for external consumers in the form they require;

- cluster 6 of DSP processors is configured to implement algorithms for processing data streams;

- video data codec 7 is configured to implement video and audio data processing algorithms;

- the first controller 8 of the SPI interface is configured to load the bootloader program of the operating system of the device from the external ROM;

- the first UART interface controller 9 is configured to remotely control the system-on-chip 2;

- reset unit 10 RESET is configured to reset the system on chip 2;

- reprogrammable ROM 11 of the FLASH SPI type is configured to store the boot program for the operating system of the device;

- reprogrammable ROM 12 of the eMMC type is configured to store programs of the operating system of the device and programs that implement algorithms for processing input data streams;

- the monitor 14 operating temperatures and voltages is configured to collect information about the status and mode of operation of the blocks that are part of the system on a chip 2;

- the supervisor 15 is configured to monitor the integrity of the device software and remotely control the device;

- the processor 16 CPU is configured to implement algorithms for monitoring the integrity of the device software, monitoring the technical condition of the system on the chip 2 and remote control of the device;

- the controller 18 of the SPI interface is configured to control the bootloader program of the operating system of the device;

- controller 19 input-output IO, is configured to receive information about the status and mode of operation of the blocks that are part of the system on a chip 2 and control the reset of the system on a chip 2;

- the power supply unit 21 is connected to the main power supply circuits of the device and is configured to provide supply voltages to the system-on-chip 2, a group of HDD drives 1, RAM 12 of the DDR type, reprogrammable ROM 11 of the eMMC type;

- standby power unit 22 is connected to the standby power circuits of the device and is configured to provide supply voltages to the supervisor 15, reprogrammable ROM 11 of the FLASH SPI type, monitor 14 of operating temperatures and voltages.

For a better understanding of the claimed invention, the following is a detailed description with the corresponding drawings.

Fig. General block diagram of a data processing and storage device made according to the invention.

Let us consider an embodiment of the claimed data processing and storage device (Fig.).

The composition of the claimed data processing and storage device includes the following elements.

A group of drives 1 HDD, for example, with a SATA interface, designed to store processed digital information.

System-on-chip SoC 1892VM248 2 designed for processing input and output information.

SATA 3 controller, which is part of the 1892VM248 2 SoC, designed to manage the writing and reading of HDD group 1.

Block 4 of Ethernet controllers, containing three controllers, which is part of the SoC 1892VM248 2, and is designed to control information sources, receive input information flows and transmit information to consumers requested by them.

Cluster 5 of eight general-purpose processors with MIPS64 architecture, which is part of the SoC 1892VM248 2, designed to execute algorithms for processing input data streams, generating information for writing to HDD group 1 and generating information for external consumers in the required form.

Cluster 6 of sixteen DSP processors with ELCORE-50 architecture, which is part of the SoC 1892VM248 2, and is designed to execute algorithms for processing input data streams from information sources and output data for external consumers.

Codec 7 of video data of the H.264 standard, which is part of the SoC 1892VM248 2, and is intended for executing video and audio data processing algorithms.

The first controller 8 of the SPI interface, which is part of the SoC 1892VM248 2, and is designed to load the bootloader program of the operating system of the device from external ROM.

The first controller 9 of the UART interface, which is part of the SoC 1892VM248 2, and is intended for remote control of the SoC 1892VM248 2.

Reset block 10 RESET, which is part of the SoC 1892VM248 2, and is intended for hardware reset of the SoC 1892VM248 2.

Reprogrammable ROM 11 of the FLASH SPI type, designed to store the boot program for the operating system of the device.

Reprogrammable ROM 12 type eMMC, designed to store the operating system programs of the device and programs that implement algorithms for processing input data streams.

RAM 13 type DDR, designed for programs and data needed to implement algorithms for processing input data streams and remote control of the device.

Monitor 14 operating temperatures and voltages, designed to collect information about the status and mode of operation of the units included in the SoC 1892VM248 2.

Supervisor Salyut EL24PM 15, designed to control the integrity of the device software and remote control of the device.

The processor 16 CPU, which is part of the supervisor Salyut EL24PM 15, is designed to perform algorithms for monitoring the integrity of the device software, monitoring the technical condition of the SoC 1892VM248 2 and remote control of the device.

The second controller 17 of the UART interface, which is part of the Salyut EL24PM 15 supervisor, and is intended for remote control of the SNK 1892VM248 2.

The second controller 18 of the SPI interface, which is part of the Salyut EL24PM 15 supervisor, and is designed to control the bootloader program of the device operating system.

The controller 19 of the input-output 10, which is part of the supervisor Salyut EL24PM 15, and is designed to receive information about the status and mode of operation of the units that are part of the SoC 1892VM248 2 and control the reset of the SoC 1892VM248 2.

Ethernet controller 20, which is part of the Salyut EL24PM 15 supervisor, and is designed for remote control of the device.

Power supply unit 21, connected to the main power supply circuits of the device and providing supply voltages to SNK 1892VM248 2, a group of drives 1 HDD, RAM 13 of DDR type, reprogrammable ROM 12 of eMMC type.

Standby power supply unit 22 connected to the device's standby power circuits and providing supply voltages to the supervisor Salyut-EL24PM 15, reprogrammable ROM 11 of the FLASH SPI type, monitor 14 of operating temperatures and voltages.

Streams of input data for processing and saving in the group of drives 1 HDD served on the first input-output unit 4 Ethernet controllers. From the second input/output of block 4 of Ethernet controllers, data is sent to the first input/output of cluster 5 of eight general-purpose processors with the MIPS64 architecture. If necessary, data can be processed by cluster 5 of eight general-purpose processors with MIPS64 architecture, cluster 6 of sixteen DSPs connected by its input-output to the second input-output of cluster 5 of eight general-purpose processors with MIPS64 architecture, video codec 7 of the H. 264, connected by its input-output to the third input-output of the cluster 5. The processed data through the fourth input-output of the cluster 5 goes to the first input-output of the controller 3 SATA, to which a group of drives 1 HDD is connected through a group of second inputs-outputs.

Information processing is carried out under the control of the operating system and application software (SW). To store the boot image of the operating system programs and application software, a reprogrammable ROM 12 of the eMMC type is used, connected by its input-output to the fifth input-output of the cluster 5. To store intermediate results of data processing, RAM 13 of the DDR type is used, connected by its input-output to the sixth input -cluster output 5.

To ensure the initial loading of the device, a reprogrammable ROM 11 of the FLASH SPI type is used, connected by its input-output to the first input-output of the first controller 8 of the SPI interface, and the first input-output of the second controller 18 of the SPI interface. The second I/O of the first SPI controller 8 is connected to the third I/O of the cluster 5. The second I/O of the second SPI controller 18 is connected to the first I/O of the CPU 16. The processor 16 CPU provides control of the integrity of the bootloader in the reprogrammable ROM 11 of the FLASH SPI type before the start of loading the SoC 1892VM248 2.

The processor 16 CPU through the first input-output connected to the second input-output of the controller 20 Ethernet provides for receiving and executing commands for remote control of the device, transmitting information about the current state of the device, updating the operating system software and data processing application software. The remote control commands are received from the external control channel of the device to the second input-output of the controller 20 Ethernet. The CPU 16 executes remote control commands with the second UART controller 17 connected by its first input/output to the first input/output of the CPU 16). The second controller 17 of the UART interface transmits control commands to the first controller 9 of the UART interface through its second input-output connected to the first input-output of the first controller 9 of the UART interface, and the latter transmits control commands to the cluster 5 through its second input-output. The central processor 16 CPU through the first and second controllers 9 and 17 of the UART interface controls the operability of the SoC 1892VM248 2, including the receipt of input data streams, the execution of processing algorithms and saving data in the HDD group 1, maintains device event logs, updates the device software.

The central processor 16 CPU through the controller 19 I / O IO, connected by its first input / output to the first input / output of the central processor 16 CPU, receives data on the operating temperature and supply voltages of the SoC 1892VM248 2. When the operating temperatures or supply voltages exceed the set boundary, the CPU 16 sends an alert via the Ethernet controller 20 to the control channel. The central processor 16 CPU through the controller 19 input-output IO, connected by its first input-output to the first input-output of the reset block 10 RESET, controls the hardware reset of the components of the SoC 1892VM248 2 when executing commands to turn on and off the device and when monitoring the integrity of the bootloader SnK 1892VM248 2.

Thus, the introduction of the SoC 1892VM248 2 device, which contains cluster 5 of eight processors with the MIPS64 architecture, cluster 6 of sixteen DSPs with the Elcore-50 architecture, and video codec 7 of the H.264 standard for encoding and decoding digital video streams, makes it possible to implement in the device a wide range of real-time data processing algorithms (compression of file data, object recognition in streaming audio and video information, encryption and decryption of data, etc.) and increases the overall performance of the device compared to single-processor devices.

The use of application software for data processing, loaded from reprogrammable ROM 11 of the eMMC type, ensures the change of processing algorithms without interfering with the hardware, which expands the scope of the claimed device in comparison with known devices with FPGA-based accelerators, where the processing algorithms are strictly dependent on the hardware configuration. funds.

The introduction of the Salyut EL24PM 15 supervisor into the device provides control over the integrity of programs (the supervisor's own bootloader 15, the OS image, and the SoC 1892VM248 2 application software), thereby eliminating the possibility of unauthorized interference (image substitution, code distortion) in the operation of the device. Supervisor Salyut EL24PM 15 controls the state of the device hardware (supply voltage, processor temperature), while reducing the likelihood of failures and failures in the device, thereby increasing the reliability of the claimed device. The presence of an external control channel of the supervisor Salyut EL24PM 15 provides remote control of the device (power on, power off, reboot, integrity check and software update, access to stored information). Introduction to the claimed device of a separate power supply unit 22 for powering the supervisor Salyut EL24PM 15 ensures continuity of performance monitoring and remote control of the claimed device.

The claimed data processing and storage device is based on the 1892VM248 chip, which is designed for use in equipment with video analytics support. The chip can be used in cognitive servers, learning neural networks, autonomous robotic systems and multimedia applications.

The introduction of the claimed SoC 1892VM248 device, which contains a cluster of eight processors with the MIPS64 architecture, a cluster of sixteen DSPs with the Elcore-50 architecture, hardware blocks for encoding and decoding digital video streams, makes it possible to implement a wide range of real-time data processing algorithms (file data compression, recognition objects in streaming audio and video information, encryption and decryption of data, etc.) and increased the performance of the device compared to single-processor devices.

The use of application software loaded from reprogrammable memory for data processing provides remote change of processing algorithms without interfering with the hardware, which expands the scope of the device compared to devices where processing algorithms depend on the hardware configuration.

The declared device includes an auxiliary module - the Salyut-EL24PM supervisor with a trusted boot and control loop, which provides monitoring of the physical state of the processors and ROM of the SoC 1892VM248, remote control (power and temperature monitoring, integrity control and software updates, reboot, power on and off , event logging).

The introduction of a supervisor into the composition of the claimed device provides control over the integrity of programs (the supervisor's own bootloader, the OS image and the application software of the SoC 1892VM248), thereby eliminating the possibility of unauthorized interference (image substitution, code distortion) in the operation of the device. The supervisor monitors the hardware status (supply voltage, temperature of processors) of the device, thereby reducing the likelihood of failures and failures in the operation of the device, and increases the reliability of the device.

The supervisor's information exchange channel provides remote control of the claimed device (turning the power on and off, rebooting and updating the software, access to stored information). To ensure continuous operation of the supervisor, it is powered from a standby power source.

The above version of the claimed data processing and storage device with an expanded scope, increased performance, reliability and security, due to the use of a system on a chip based on the 1892VM248 chip, which contains a cluster of general-purpose processors with the MIPS64 architecture, a cluster of DSP processors with the Elcore architecture -50, hardware blocks for encoding and decoding digital video streams; as well as through the use of a supervisor based on the Salyut-EL24PM module with a trusted boot and control loop that provides monitoring of the physical state of the components of the SoC 1892VM248 (monitoring of supply voltages, crystal temperature), remote control of the device (integrity control and software update, reboot, power on and off power supply, event logging).

Although the embodiment of the claimed invention described above has been set forth for the purpose of illustrating the claimed invention, it will be clear to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the claimed invention as disclosed in the appended claims.

Claims (17)

A data processing and storage device containing a system on a chip (2), which is connected to a group of drives (1) HDD, with a power supply (21), with RAM (13) of the DDR type, with a reprogrammable ROM (12) of the eMMC type, with a reprogrammable ROM (11) of the FLASH SPI type, with a monitor (14) of operating temperatures and voltages, which is connected to the supervisor (15), which is connected to the standby power supply unit (22), as well as to the reprogrammable ROM (11) of the FLASH SPI type and to the system on-chip (2), which contains a block (4) of Ethernet controllers, which is connected to a cluster (5) of general-purpose processors, which is connected to a RAM (13) of the DDR type, with a reprogrammable ROM (12) of the eMMC type, with a reprogrammable ROM (11) type FLASH SPI, with a controller (3) SATA, with a cluster (6) of DSP processors, with a codec (7) of video data, with the first controller (8) of the SPI interface and with the first controller (9) of the UART interface, and the supervisor (15) contains the controller (20) Ethernet, which is connected to the central processing unit (16) CPU, which The first one is connected to the second controller (17) of the UART interface, to the second controller (18) of the SPI interface and to the controller (19) of the input-output IO, which is connected to the reset unit (10) RESET and to the monitor (14) of operating temperatures and voltages, which is connected to the first controller (9) of the UART interface, which is connected to the second controller (17) of the UART interface, and the second controller (18) of the SPI interface is connected to the first controller (8) of the SPI interface and to the reprogrammable ROM (11) of the FLASH SPI type, and - the system on a chip (2) is configured to receive, process information and write the processed information to a group of drives (1) HDD; - a cluster (5) of general-purpose processors is configured to implement algorithms for processing data streams, generating information for writing to a group of HDD drives (1), as well as generating information for external consumers in the form they require; - a cluster (6) of DSP processors is configured to implement algorithms for processing data streams; - codec (7) of video data is configured to implement algorithms for processing video and audio data; - the first controller (8) of the SPI interface is configured to load the bootloader program of the operating system of the device from the external ROM; - the first controller (9) of the UART interface is configured to remotely control the system-on-chip (2); - the reset unit (10) RESET is configured to reset the system-on-chip (2) hardware; - reprogrammable ROM (11) of the FLASH SPI type is configured to store the bootstrap program for the operating system of the device; - reprogrammable ROM (12) of the eMMC type is configured to store programs of the operating system of the device and programs that implement algorithms for processing input data streams; - the monitor (14) of operating temperatures and voltages is configured to collect information about the state and mode of operation of the blocks that make up the system on a chip (2); - the supervisor (15) is configured to control the integrity of the device software and remotely control the device; - the processor (16) CPU is configured to implement algorithms for monitoring the integrity of the device software, monitoring the technical state of the system on a chip (2) and remote control of the device; - the controller (18) of the SPI interface is configured to control the bootloader program of the operating system of the device; - the controller (19) input-output IO is configured to receive information about the state and mode of operation of the blocks that are part of the system on a chip (2) and control resetting the system on a chip (2); - the power supply unit (21) is connected to the main power supply circuits of the device and is configured to provide supply voltages to the system on a chip (2), a group of drives (1) HDD, RAM (12) of the DDR type, reprogrammable ROM (11) of the eMMC type; - the standby power unit (22) is connected to the standby power circuits of the device and is configured to provide supply voltages to the supervisor (15), reprogrammable ROM (11) of the FLASH SPI type, monitor (14) of operating temperatures and voltages.

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