RU2771211C1 - Cold standby computing system - Google Patents

Abstract

FIELD: computer technology.SUBSTANCE: invention relates to computer technology and can be used in the creation of systems for solving information and computational problems of increased reliability in the event of an external destructive flow of particles and radiation. A cold-standby computing system containing two identical channels (VM1 and VM2), each of which consists of a processor, memory, the first I/O device, as well as the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth generators, the second processor, the second RAM, first PROM, second PROM, VM system controller, second I/O device, third I/O device, fourth I/O device, fifth I/O device, power reset node, first galvanic isolation node, the second galvanic isolation node, a secondary power supply, whose outputs produce 1.5 V, 1.8 V and 3.3 V, a recovery control device (YYB) is additionally introduced into the system.EFFECT: increase in reliability in the event of an external destructive flow of particles and radiation.13 cl, 91 dwg

Description

The invention relates to computer technology and can be used to create systems for solving information and calculation problems of increased reliability in the event of an external destructive flow of particles and radiation.

Known redundant dual-processor computing system [1] (analogue), containing a comparison circuit and two identical channels, each of which contains a system generator, the output of which is connected to the first input of the processor, the first output of the processor is connected to the first input of the switch, the second output of the processor is connected to the first the input of the OR element, the output of which is connected to the first input of the temporary health analyzer and the first input of the trigger, the output of which is connected to the first input of the OR-NOT element, the pulse generator, the output of which is connected to the second input of the temporary health analyzer, the output of which is connected to the first input of the failure counter and the second input of the trigger, the first output of the failure counter is connected to the second input of the OR-NOT element, the output of which is connected to the second input of the switch, the initial installation circuit, the output of which is connected to the second input of the processor, the second input of the OR element, the second input of the failure counter, the second output which is connected to the first input of the comparison circuit, the second input of which is connected to the second input of the failure counter of the second channel, the first output of the comparison circuit is connected to the third input of the OR-NOT element of the first channel, the second output of the comparison circuit is connected to the third input of the OR-NOT element of the second channel, the outputs of the switches are connected and are the output of the system, to which the necessary external devices (modules) are connected.

The disadvantage of a redundant dual-processor computer system is the lack of a self-diagnostic system for fault detection and a cold reserve, which provides increased reliability in the event of an external destructive particle and radiation flow.

The closest in technical essence to the invention is a system that consists of two redundancy channels 1.1, 1.2, each of which contains a processor unit 2, a serial interface unit 3, a memory unit 4, an input-output unit 5, a serial interface bus 6, a local bus 7 , system bus 8, block 9 shared memory and tires 10, 11 input-output.

The system uses the multiprocessing mode - the operation of two processor units in a structure with a shared memory. This mode allows processors to exchange processing results when duplicating in a parallel interface [2].

The described system as the closest to the proposed one is taken as a prototype.

The disadvantage of a redundant dual-processor computer system is the lack of a self-diagnostic system for fault detection and a cold reserve, which provides increased reliability in the event of an external destructive particle and radiation flow.

The objective of the invention is to increase reliability in the event of exposure to an external destructive flow of particles and radiation.

The current "hot" reserve is switched off under the influence of an external destructive flow of particles and radiation, and the system switches to a duplicated reserve ("cold" reserve), which was in the off state until the moment of failure.

The system contains a YYB recovery control device that is resistant to these influences and regularly copies the current operating state of the VM into it in advance, which allows not to completely repeat the calculations from the beginning, but to continue from the successfully completed stage of the program being executed.

The essence of the claimed invention, the possibility of its implementation and industrial use are illustrated by the drawings shown in Fig.1-57, where:

• figure 1 shows a block diagram of a computer system with a cold reserve:

• figure 2 shows a functional diagram of the system controller VM;

• figure 3 shows the functional diagram of the node BM_REC;

• figure 4 shows the functional diagram of the node BM_TRAN;

• figure 5 shows a functional diagram of the system controller UUV;

• figure 6 shows a functional diagram of the reserve management node (YYR);

• figure 7 shows a functional diagram of the node movement (Y_D);

• Figure 8 is a functional diagram of the MRAM control unit;

• Figure 9 shows a functional diagram of the receiver node (YYB_REC);

• Figure 10 is a functional diagram of the transmitter node (YYB_TRAN);

• figure 11 shows a functional diagram of the MCO node;

• Figure 12 is a functional diagram of the receiver node OU (REC_OU);

• Fig. 13 shows the operation algorithm of the node for determining the reaction mode;

• Fig. 13a shows the continuation of the operation algorithm of the node for determining the reaction mode;

• Fig.14 shows the operation algorithm of the redundancy switching node;

• Fig. 14a shows the continuation of the operation algorithm of the redundancy switching node;

• figure 15 shows the algorithm of the node time Y_TIME 31;

• Fig.15a shows the continuation of the algorithm of the node time Y_TIME 31;

• Fig.15b shows the continuation of the algorithm of the node time Y_TIME 31;

• Fig.16 shows the algorithm of the Y_TRIMP scheme of the movement node 30:

• figure 17 shows the algorithm of the Y_RCIMP scheme of the movement node 30:

• Fig. 17a shows the continuation of the operation algorithm of the Y_RCIMP circuit of the movement node 30:

• Fig. 18 is a diagram of MS for controlling VM1 and VM2;

• Fig. 18a shows the continuation of the MC diagram for controlling VM1 and VM2;

• Fig.19 shows the TRAN transmitter operation algorithm:

• Fig. 20 shows the operation algorithm of the Y_FYS_TRAN transmitter's control signal generating unit;

• figure 21 shows the operation algorithm of the BM_REC node of the receiver;

• Fig. 21a shows the operation algorithm of the unit for generating control signals U_FUS;

• Figures 22, 22a show the operation algorithms of the YYB receiver's control signal generating units.

• Fig. 23 shows the MRAM control node algorithm;

• Fig. 24 shows the operation algorithm of the MRAM timing diagramming unit (Y_DMRAM);

• Fig. 25 shows the operation algorithm of the HAMMING_CODER nodes (encoder_L 196, encoder_L 197;

• Fig. 26 shows the operation algorithm of the HAMMING_DECODER 197,198 nodes;

• Fig. 26a shows the continuation of the operation algorithm of the HAMMING_DECODER nodes;

• Fig. 27 shows the operation algorithm of the subaddress generation node;

• Fig. 27a, b shows the continuation of the operation algorithm of the subaddress generation node;

• FIG. 28 shows the algorithm of the terminal device control node (Y_YOU) 213;

• Fig.29 shows the operation algorithm of the node for determining the beginning of the exchange format with the selection of command words and data words;

• Fig.29a shows the continuation of the operation algorithm of the node for determining the beginning of the exchange format with the selection of command words and data words;

• figure 30 shows the algorithm of the receiver decoder;

• Fig. 30a shows the continuation of the algorithm of the receiver decoder;

• Fig.30b shows the continuation of the algorithm of the receiver decoder;

• Fig. 31 shows the operation algorithm of the CODER OU node;

• Fig. 31a shows the continuation of the operation algorithm of the CODER OU node;

• Fig. 32 shows the operation algorithm of the DECODER OU node;

• Fig. 32a shows the continuation of the operation algorithm of the DECODER OU node;

• Fig. 32b shows the continuation of the operation algorithm of the DECODER OU node;

• Fig.33 shows the operation algorithm of the DETECTOR node;

• Fig.34 shows the operation algorithm of the CONTROLLER node;

• Fig. 34a shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34b shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34c shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34d shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34d shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34e shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 34g shows the continuation of the operation algorithm of the CONTROLLER node;

• Fig. 35 shows the operation algorithm of the unit for generating control signals of the CM receiver;

• Fig. 36 shows the operation algorithm of the transmitter control signal generating unit (Y_FYS_BM_TRAN);

• Fig. 37 shows the operation algorithm of the telemetric channel memory unit (Y_TLMRAM);

• Fig. 37a shows the continuation of the operation algorithm of the Y_TLMRAM node;

• Fig. 37b shows the continuation of the operation algorithm of the Y_TLMRAM node;

• Fig. 38 shows the address space of the PROM 15 of the processor 1 1890 VM6YA when accessed from the M2 channel 53;

• Fig.39 shows the address space of the PROM 15 from the processor 1 1890 VM6Ya;

• Fig. 40 shows the address space of the PROM 16 of the processor 13 1890 VM7YA when accessed from the side of the M2 channel 53;

• Fig.41 shows the address space of the PROM 16 from the processor 13 1890 VM7Ya;

• Fig.42 shows the structure of the discharges of the COP;

• Fig. 43 shows the structure of OS information bits;

• Fig.44 shows the structure of information bits of transmitted and received data words;

• Fig.45 shows the description of the contents of the SD when working with formats 1 and 2;

• Fig.46 shows the address space of the registers of the system controller YYB 26 when accessed via PCI 67;

• FIG. 47 shows data exchange using 32-bit data words protected by 32 extra bits of Hamming code;

• Fig. 48 shows the frame structure;

• Fig.49 shows the total address space of the PROM 15,16, telemetry controller TMK 32 and persistent memory MRAM 28;

• Fig.50 shows the control commands PROM 15, 16;

• Fig.51 shows the structure of the packet with an example of data transmission "80000000 ₁₆ ";

• Fig.52, 52a shows the decoding of the telemetry package 3;

• Fig.53. the interpretation of the values of the signal "sPOWST" is presented;

• Fig. 54 shows the decoding of telemetry packets 6, 7, 8;

• Fig.55 shows the algorithm for calculating the checksum of packets 1-7;

• Fig.56 shows the decoding of the signal "sSWITCHINF";

• FIG. 57 is a description of the telemetry flags.

These advantages of the claimed computing system with a cold standby (CHR) over the prototype are achieved due to the fact that it contains two identical channels (VM1 and VM2), each of which consists of a processor 1, memory 2, the first input-output device 3, additionally introduced are the first 4, second 5, third 6, fourth 7, fifth 8, sixth 9, seventh 10, eighth 11 and ninth 12 generators, the second processor 13, the second RAM 14, the first PROM 15, the second PROM 16, the system controller VM 17 , second input/output device 18, third input/output device 19, fourth input/output device 20, fifth input/output device 21, power reset node (reset power) 22, first galvanic isolation node 23, second galvanic isolation node 24 , secondary power supply 25, the outputs of which produce 1.5 V, 1.8 V and 3.3 V, the recovery control device (YYB) is additionally introduced into the system, containing the YYB 26 system controller, the shock factor sensor assembly (hereinafter e - PF sensor) 27, external memory MRAM 28, reserve control node 29, movement node 30, time node (TIME) 31, telemetry node (TMK) 32, power reset node (reset power) 33, sixth I / O device 34, generator 35, filter 36 and power unit 37, the outputs of which produce 1.5 V and 3.3 V, and the input is connected to the output 38 of the filter 36 and to the first inputs of the channels BM1 and BM2, the first groups of outputs 39, 40 of which are connected with the first and second groups of inputs of the YYB 26 system controller, the first 41 and second 42 groups of outputs of which are connected to the groups of inputs of the external memory MRAM 28 and the telemetry node 32, respectively, the group of inputs-outputs 43 of the external memory MRAM 28 and the group of outputs 44 of the telemetry node TMK 32 connected to the input-output group and the third group of inputs of the YYB 26 system controller, the second 45 and first 46 control groups of outputs of which are connected to the first groups of inputs of the nodes of the PF sensor 27 and reserve control 29, the first groups of outputs 47,48 of which are connected to the the fourth and fifth groups of inputs of the YYB 26 system controller, the third group of outputs 49 of which is connected to the first input of the movement node 30 and the first group of inputs of the time node TIME 31, the output group 50 of which is connected to the sixth group of inputs of the YYB 26 system controller, the fourth 51 and fifth 52 the output groups of which are connected to the first groups of inputs of the first and second channels BM1 and BM2, the first outputs of which are interconnected, with the input of the sixth input-output device YYB 34, with the outputs of the third input-output devices 19 and are the first output 53 VCXR, the first 54 and the second 55 output group of which are connected to the first and second groups of outputs of the motion nodes 30 and the PF sensor 27, respectively, and the first 56 and 57 second groups of inputs are connected to the input group of the motion node 30 and the second group of inputs of the PF sensor node 27, the first output of which is the second output 58 VSHR, the first input 59 which is connected to the first input of the time node TIME 31, the third 61 and second 60 groups of inputs which are connected to the second groups of outputs of the movement nodes 30 and reserve control 29, the first output 62 and input 63 of which are connected to the input and second output of the PF sensor node 27, and the first 64 and second 65 inputs of the YYB 26 system controller are connected to the outputs of the sixth input device - output 34 and generator 35, the third 66 output of the VSHR in each channel is connected to the outputs of the second 18 I / O devices, the inputs and outputs of which are connected to the PCI bus 67, which is connected to the first inputs and outputs of the first 1 and second 13 processors, with inputs - outputs of the third 19, fourth 20 and fifth 21 input-output devices, with the inputs - outputs of the system controllers 17 and with the outputs of the generators 33 MHz 12, and the second 68 and third 69 groups of inputs-outputs of the first processors 1 are connected to the inputs-outputs of the first RAM2 and the first PROM15, and the groups of outputs 70 of the first processors 1 are connected to the first groups of inputs of the second processors 13, the second 71 and the third 72 groups of input-outputs of which are connected ny with groups of inputs/outputs of the second RAM 14 and with groups of inputs/outputs of the second PROM 16, the second 73 groups of inputs/outputs of the first PROM 15 are connected to the first groups of inputs/outputs of the first I/O devices 3, the second 74 groups of inputs/outputs of which are connected with the fourth groups of inputs-outputs of the first processors 1, the first 75 groups of inputs of which are connected to the first groups of outputs of the VM system controllers 17, the second 76 groups of outputs of which are connected to the second groups of inputs of the second processors 13, the group of outputs 77 of which is connected to the second groups of inputs of the first processors 1, the first 78, the second 79 and the third 80 inputs of which are connected to the outputs of the generators of the first 125 MHz 4, the second 80 MHz 5 and the third 24 MHz 6, respectively, and the fourth 81 inputs of which are connected to the outputs of the seventh generators 25 MHz 10 and the first inputs of the first devices I / O 3, the second inputs of which are connected to each other and to the second 82 input of the VCXR, and the third inputs are connected to the first 83 outputs of the first x processors, the fifth inputs of which are connected to the first outputs 84 of the VM 17 system controllers, the second outputs 85 of which are connected to the first inputs of the second processors 13, the second 86 and third 87 inputs of which are connected to the outputs of the fifth generators 24 MHz 8 and the sixth generators 25 MHz 9, the first 88 groups of inputs of the system controllers VM 17 are connected to the groups of outputs of the second nodes of galvanic isolation 24, and the third 89 groups of outputs of the system controllers VM 17 are connected to the groups of inputs of the first nodes of galvanic isolation 23, and the first 90 and second 91 inputs of the system controllers VM 17 are connected to power reset nodes 22 and fourth generators 24 MHz 7, and the outputs of 92 eighth generators 12 MHz 11 are connected to the first inputs of the second 18, third 19, fourth 20 and fifth 21 input-output devices, and the outputs of the fourth 20 and fifth 21 input-output devices VM1 channel outputs are connected to the outputs of the fourth 20 and 21 fifth input-output devices of the VM2 channel and are the fourth th 93 and fifth 94 outputs of the VSKhR system, and the third 95 group of outputs of the PF sensor 27 is connected to the seventh group of inputs of the YYB 26 system controller, the clock 96 and reset 97 outputs of which are connected to the clock and reset inputs of the PF 27 sensor nodes, reserve control 29, movement 30, time (TIME) 31 and telemetry (TMK) 32, and the second 98 and third 99 outputs of the reserve control node 29 are connected to the second inputs of the secondary power sources 25 in each channel BM1 and BM2, the third 100 group of outputs YYR 29 is connected to the second group inputs of the TMK 32 node, the second group of outputs of which is the third 101 group of outputs of the VSHR, the third 102 group of inputs of which is connected to the eighth group of inputs of the YYB 26 system controller, the third input 103 of which is connected to the output of the power reset node 33, and the sixth group of outputs 104 is connected with a group of inputs of the sixth input-output device 34, and the output 105 MKORST of the system controller VM 17 is connected to the second inputs of the second 18, three those 19, fourth 20 and fifth 21 I/O devices.

The VM system controller 17 in each channel contains a start diagram node 106 (START), a PCI bus interface node 107 (Y_PCI), a PCI memory node 108 (Y_RAM2), a node for receiving information from LVDS 109 (Y_MB_REC), a telemetry channel memory node 110 ( Y_TLMRAM), LVDS information transfer node 111 (Y_BM_TRAN), frequency generation node 112 (PLL), first AND element 113, second AND element 114, first multiplexer group 115, second multiplexer group 116, OR element group 117, whose output group is connected in each channel with the first and byte by byte with the second groups of inputs of the first group of multiplexers 115, the output group of which is connected to the input group of the Y_PCI node 107, the first group of outputs 118 of which is connected to the first groups of inputs of the Y_RAM2 node 108 and the Y_TLMRAM node 110, the first group of outputs of which is connected with the first group of inputs of the group of elements OR 117, the second group of inputs of which is connected to the first group of outputs of the node Y_RAM2 108, and the first group of outputs Y_BM_TRAN 111 is the third group of outputs 89 of the VM system controller 17, the BMCLK_O signal of which is connected to the first input of the Y_BM_TRAN 111 node and is the first output of the PLL 112, the second 119 output of which is connected to the first input of the Y_MB_REC node 109, the first 120, the second 121, the third 122 and the fourth 123 output groups of which are connected to the second, third, fourth and fifth groups of inputs of the node Y_TLMRAM 110, the second 124, third 125 and fourth 126 groups of outputs of which are connected to the first, second and third groups of inputs of the node Y_BM_TRAN 111, the fourth group of inputs of which is connected to the fifth output group 127 of the Y_MB_REC 109 node, the sixth 128 group of outputs of which is connected to the fifth group of inputs of the Y_BM_TRAN 111 node, the seventh 129 group of outputs Y_MB_REC 109 is connected to the second and sixth groups of inputs of the nodes Y_RAM2 108, Y_TLMRAM 110 and Y_BM_TRAN 111, respectively, and the eighth group of outputs is connected with the first and seventh groups of inputs of the nodes START 106, Y_TLMRAM 110 and Y_BM_TRAN 111, respectively, and are is the first 75 and second 76 groups of outputs of the system controller VM 17, which are also connected to the ninth, tenth and eleventh groups of outputs of the node Y_MB_REC 109, the first input 90 of the system controller VM 17 is connected to the first inputs of the nodes START 106, Y_RAM2 108, Y_TLMRAM 110 and Y_BM_TRAN 111, and the output group 130 of the START node 106 is connected to the eighth input group of the Y_BM_TRAN node 111, the fourth signal of which is connected to the first inputs of the PLL 112 and the first AND element 113, the fifth signal of which is connected to the first input of the Y_PCI node 107, the sixth signal of which is connected to the direct the input of the second element And 114 and with the second input of the node Y_MB_REC 109, the third input of which is connected to the second inputs of the nodes START 106, Y_RAM2 108, Y_TLMRAM 110, with the third input of the node Y_BM_TRAN 111 and is the second input 91 of the system controller VM 17, the input group 88 of which connected to the input group of the Y_MB_REC node 109 and to the second input of the PLL 112, the third output of which is connected to the second input of the first element And 113, the output of which is connected to the inverse input of the second element And 114, the output 131 of which is connected to the fourth input of the Y_MB_REC node 109, and the second group of outputs of the Y_PCI node 107 is connected to the first group of inputs and byte by byte to the second group of inputs of the second group of multiplexers 116, the group of outputs 132 of which is connected to the third group of inputs of the Y_RAM2 node 108 and the eighth group of inputs of the Y_TLMRAM node 110, the fifth group of outputs 133 of which is connected to the ninth group of inputs of the Y_BM_TRAN node 111, the third input of the Y_TLMRAM node 110 is connected to the third input of the Y_RAM2 node 108 and the output 13 of the Y_PCI node 107 , the input-output group of which is connected to the fourth inputs of the nodes Y_TLMRAM 110 and Y_RAM2 108 and is a group of input-outputs 67 of the system controller VM 17, the fifth 135 inputs of the nodes Y_TLMRAM 110 and Y_RAM2 111 are connected to the housing, the sixth input 136 of the node Y_TLMRAM 110 is connected to power supply, the output 137 of the node Y_TLMRAM 110 is connected to the control inputs of the first 115 and second 116 multiplex groups ditch, and the seventh, eighth and ninth signals of the group of outputs 130 of the node START 106 are the first 84, second 85 and third 105 (MKORST) outputs of the system controller BM 17.

The node for receiving information from LVDS 109 (Y_MB_REC) in each channel contains the first node REC0 138, the second node REC1 139, the third node REC2 140, the node for generating control signals (Y_FYS) 141, the first group of inverters 142, the second group of inverters 143, the inverse group of outputs which is connected to the first group of inputs of the Y_FYS 141 node, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh groups of outputs of which are connected to the first 120, second 121, third 122, fourth 123, fifth 127 , sixth 128, seventh 129, eighth 75, 76, ninth 75, 76, tenth 75 and eleventh 76 groups of outputs of the Y_MB_REC 109 node, the first, second and third signals of the input group 88 of which are connected to the first inputs of the nodes REC0 138, REC1 139, REC2 140, respectively, the second inputs of which are interconnected, with the first input of the Y_FYS node 141 and are the first input 119 of the Y_MB_REC node 109, the second input 130(6) of which is connected to the inverse input of the Y_FUS node 141, the second input group the input group of which is connected to the output group of the node REC0 138 and to the group of inputs of the first group of inverters 142, the inverse group of outputs of which is connected to the third group of inputs of the node Y_FYS 141, the fourth group of inputs of which is connected to the group of outputs of the node REC1 139 and to the group of inputs of the second group of inverters 143 , the fifth group of inputs of the node Y_FYS 141 is connected to the group of outputs of the node REC2 140, the third input of which is connected to the second input of the node Y_FYS 141, with the third inputs of the nodes REC0 138, REC1 139 and is the third input 91 of the node Y_MB_REC 109, the fourth input 131 of which is connected to the third input of the node Y_FYS 141 and with the fourth inputs of the nodes REC0 138, REC1 139 and REC2 140.

The node for transmitting information in LVDS 110 Y_BM_TRAN in each channel contains the first node TRAN 0 144, the second node TRAN 1 145, the third node TRAN 2 146, the node for generating control signals of the transmitter Y_FYS_BM_TRAN 147, the output group 89 of the node Y_BM_TRAN 110 is connected to the outputs of the nodes TRAN 0 144 , TRAN 1 145, TRAN 2 146, whose input groups are connected to the first, second and third output groups of the Y_FYS_ BM_TRAN 147 node, the first input group of which is connected to the output group of the first node TRAN 0 144, the first input of which is connected to the first inputs of the TRAN 1 nodes 145, TRAN 2 146 and is the first input 89 of the node Y_BM_TRAN 110, the first 124, the second 125, the third 126, the fourth 127, the fifth 128, the sixth 129, the seventh 75, 76, the eighth 130 and the ninth 133 groups of inputs of which are connected to the second, third , fourth, fifth, sixth, seventh, eighth, ninth and tenth groups of inputs of the node Y_FYS_TRAN 147, and the first signal of the eighth 130 group of inputs of which is connected to the second inputs of the nodes TRAN 0 144, TRAN 1 1 45, TRAN 2 146, the third inputs of which are interconnected and are the third 91 input of the node Y_MB_TRAN 110, the second input 90 of which is connected to the fourth inputs of the nodes TRAN 0 144, TRAN 1 145, TRAN 2 146, and the group of outputs of the node TRAN 1 145 is connected with the eleventh group of inputs of the node Y_FYS_BM_TRAN 147.

The YYB system controller 26 includes a data receiving node (YYB_REC) 148, an external memory management node (Y_MRAM) 149, a data transmission node (YYB_TRAN) 150, a YMKO node 151, a first PLL 152, a second PLL 153, a first multiplexer 154, a second multiplexer 155, first trigger 156, second trigger 157, first element AND 158, second element AND 159, third element AND 160, fourth element AND 161, fifth element AND 162, element 3AND-OR 163, first element OR 164, second element OR 165, first a multiplexer group 166, a second multiplexer group 167, the output group of which is the fifth output group 52 of the YYB system controller 26, and the MBCLK2 signal of which is connected to the output of the second multiplexer 155, the first input of which is connected to the case, and the second input is connected to the first input of the first multiplexer 154 and the first output of the first PLL 152, the inverted output 168 of which is connected to the first input of the node Y_MKO 151, the group of outputs Upr2_MKO of which and the signal TLV are the first control group of the output 45 of the YYB 26 system controller, the second control group of outputs 46 of which consists of the first and third groups of outputs of the YYB_REC node 148, from the first group of outputs of the Y_MKO node 151 and from the output of the second trigger 157, the information input of which is connected to the first input of the third element AND 160 and the output of the first element And 158, the input of which is the first signal of the fifth group of inputs 48 of the YYB 26 system controller, the second and third signals of which are connected to the first and second inputs of the fourth element And 161, the output 169 of which is connected to the first input of the Y_MRAM node 149, the input group is the outputs of which is the input-output group 43 of the YYB system controller 26, the first group of outputs 41 of which is connected to the first and second groups of outputs of the node Y_MRAM 149, the third group of outputs 170 of which is connected to the second group of inputs of the node Y_MKO 151, the second group of outputs of which is connected to the second output group 42 of the YYB 26 system controller, the third output group of which is connected with the first group of inputs of the node YYB_TRAN 150, with the third input of the node YYB_REC 148, with the third group of outputs of the node Y_MKO 151, with the second input of the node Y_MRAM 149, the fourth group of outputs 51 of the YYB 26 system controller is connected to the output group of the first group of multiplexers 166, and the signal MBCLK1 which is connected to the output of the first multiplexer 154, the second input of which is connected to the housing, and the fourth signal of the fifth group of inputs 48 of the YYB 26 system controller is connected to the inverse input of the second AND element 159, with the first inputs of the 3I-OR element 163 and the first OR element 164, with control inputs of the first multiplexer 154 and the first group of multiplexers 166, the first group of inputs of which is connected to the first group of inputs of the second group of multiplexers 167 and the first group of outputs 171 of the node YYB_TRAN 150, the second group of outputs 172 of which is connected to the first group of inputs of the node Y_MKO 151, the third, the fourth, fifth, sixth, seventh, eighth, ninth groups of inputs of which are connected with the fourth 173, fifth 174, sixth 175, seventh 176, eighth 177, ninth 178, tenth 179 groups of outputs of the node YYB_REC 148, the first output of which is connected to the third input of the fourth element AND 161 and is the first signal of the eleventh group of outputs 180, which is connected to the second group of inputs of the node YYB_TRAN 150 and the tenth group of inputs of the node Y_MKO 151, the fourth group of outputs of which is the sixth group of outputs 104 of the system controller YYB 26, the second group of outputs 42 of which is connected to the second group of outputs of the node Y_MKO 151, with the twelfth and second groups of outputs of the node YYB_REC 148, the second and third groups of inputs of which are connected to the first 39 and second 40 groups of inputs of the YYB 26 system controller, the third group of inputs 7 of which is connected to the third group of inputs of the node YYB_TRAN 150, the fourth group of inputs of which is connected to the eleventh group of inputs of the node Y_MKO 151 and is the fifth group of inputs 48 of the YYB 26 system controller, the fourth group of inputs 47 which th is connected to the twelfth group of inputs of the node Y_MKO 151, the fifth group of outputs 181 of which is connected to the fifth group of inputs of the node YYB_TRAN 150, the sixth and seventh groups of inputs of which are connected to the sixth 182 and seventh 183 groups of outputs of the node Y_MKO 151, the thirteenth group of inputs of which is connected to the eighth group of inputs of the node YYB_TRAN 150 and is the sixth group of inputs 50 of the system controller YYB 26, the first input 64 of which is connected to the second input of the node Y_MKO 151, the first and second outputs of which are connected to the first and second inputs of the fifth element AND 162, the output of which is connected to the third input node Y_MKO 151 and the first input of the node YYB_TRAN 150, the ninth and tenth groups of inputs of which are connected to the fifth 173 and fourth 172 groups of outputs of the node YYB_REC 148, the first input of which is connected to the first output of the second PLL 153 and is the first signal of the second group of outputs 42 of the YYB system controller 26, the second signal of which is connected to the second output of the second PLL 153 and the inverse input m of the first element And 158, and the second input of the YYB_REC 148 node is connected to the output 184 of the third element And 160, the second input of which is connected to the inverse input of the second trigger 157, the input of the first PLL 152, the output of the first trigger 156 and is a reset signal 97 of the YYB 26 system controller and nodes Y_MRAM 149, YYB_TRAN 150 and Y_MKO 151, the clock inputs of which are connected to the clock input of the second trigger 157, the node YYB_REC 148 and the output of the first PLL 152 and is the clock output 96 of the system controller YYB 26, and the control input of the second multiplexer 155 is connected to the control inputs of the second group of multiplexers 167, with a direct input of the second element AND 159, the second input of the first element OR 164 and is the fifth signal of the fifth group of inputs 48 of the YYB 26 system controller, the signals BMCLK1 and BMCLK2 of the first 39 and second 40 groups of inputs of which are connected to the second and third inputs element 3I-OR 163, the output of which is connected to the input of the second PLL 153, and the fourth, fifth and sixth whose inputs are connected to the output of the second element AND 159, the inverse output of the first element OR 164 and the housing, respectively, and the second 65 and third 103 inputs of the YYB 26 system controller are connected to the clock and inverse reset inputs of the first trigger 156, respectively, the information input of which is connected to power , and the sixth and seventh signals of the fifth group of inputs 48 of the YYB 26 system controller are connected to the first and second inputs of the second element OR 165, the output 185 of which is connected to the second input of the node YYB_TRAN 150, the third input of which is connected to the first output 186 of the first PLL1 52, and the second groups of inputs of the first 166 and second 167 groups of multiplexers are constant "7", and the first group of inputs of the YYB_REC 148 node is connected to the fifth group of inputs 48 of the YYB 26 system controller, the seventh 95 and eighth 102 groups of inputs of which are connected to the fourteenth and fifteenth groups of inputs of the Y_MKO node 151.

The reserve management node (YYR) 29 includes a reserve switching node (ASR) 187, a state machine (MS) 188, a first goodness determination node (GOOD1) 189, a second goodness determination node (GOOD2) 190, and a reaction mode determination node (YORR) 191, the first and second groups of outputs are the first group of outputs 48 of the node YYR 29, which also consists of the first group of outputs of the node ASR 187, from the first groups of outputs and the first groups of outputs of the nodes GOOD1 189 and GOOD2 190, the first groups of inputs of which are connected to the second group of outputs of the node ASR 187, the first output of which and the second signal of the MS 188 output group, which is also connected to the first input of the ASR 187 node, are the second group of outputs 60 of the YYR 29 node, the third and fourth groups of outputs of the ASR 187 node are connected to the first and second groups of inputs of the YORR node 191, the third group of outputs of which is connected to the third group of outputs 100 YYR 29, the output 62 of which is connected to the first signal of the group of outputs MS 188, the input of which is connected to the input 63 of the node YY R 29, the first input group 46 of which consists of the UPR_MKO group, which is connected to the first input group of the ASR node 187, to the second input groups of the GOOD1 189 and GOOD2 190 nodes, and to the third input group of the YORR node 191, and from the UPR_REC group, which is connected to the third groups of inputs of the GOOD1 189 and GOOD2 190 nodes, with the fourth, fifth and sixth groups of inputs of the YORR 191 node, the seventh group of inputs of which is connected to the second group of outputs of the GOOD1 189 node, the clock and reset inputs of which are connected to the clock and reset inputs of the ASR 187 nodes, GOOD2 190, YORR 191, MS 188 and are the clock 96 and reset 97 inputs of the YYR 29 node, and the output of the YORR 191 node is connected to the second input of the ASR 187 node, the second and third groups of outputs of the GOOD2 190 node are connected to the eighth and ninth groups of inputs of the YORR node 191, with the second and third outputs of the ASR 187 connected to the second and third outputs of the YYR 29.

The motion node (Y_D) 30 contains the first pulse analyzer (A_RCIMP1) 192, the second pulse analyzer (A_RCIMP2) 193, the first pulse generator (G_TRIMP1) 194, the second pulse generator (G_TRIMP2) 195, the output of which is the second signal of the first output group 54 of the Y_D node 30, and the first signal of which is connected to the output of the first generator G_TRIMP1 194, the inverse enabling input of which is connected to the inverse enabling input of the second generator G_TRIMP2 195 and is the input 49 of the node Y_D 30, the second group of outputs 61 of which is connected to the outputs of the first and second pulse analyzers G_RCIMP1 192 , G_RCIMP2 193, the information inputs of which are the first group of inputs 56 of the Y_D 30 node, the clock 96 and reset 97 inputs of which are connected to the clock and reset inputs A_RCIMP1 192, A_RCIMP2 193, G_TRIMP1 194, G_TRIMP 195.

The external memory control node (Y_MRAM) 149 comprises an encoder_L (K_L) 196, an encoder_H (K_H) 197, a control node (Y_Y) 198, an MRAM timing diagramming node (Y_DMRAM) 199, a decoder_L (DK_L) 200, a decoder_H (DK_H) 201, the output group of which is combined with the output group DK_L 200 and is the first group of inputs of the node Y_Y 198, the first group of outputs of which is connected to the third group of outputs 170 Y_MRAM 149, the first group of outputs 41 of which are the first, second and third outputs of the nodes Y_Y 198 and Y_DMRAM 199 and the first group of outputs of the node Y_DMRAM 199, which is also connected to the second group of inputs of the node Y_Y 198, the second group of outputs of which is connected to the first group of inputs of the node Y_DMRAM 199, the second group of outputs of which is connected to the groups of inputs DK_L 200, DK_H 201 and the third group of inputs of the node Υ_Υ 198, Υ of which is connected to the second group of inputs of the node Y_DMRAM 199 and is the first group of inputs 173 of the node Y_MRAM 149, the second group of inputs 174 of which is connected to the group node inputs K_L 196, K_H 197 and the fifth group of inputs of the node Υ_Υ 198, the fourth output of which is connected to the first input of the node Y_DMRAM 199, the fourth output of which is connected to the first input of the node Y_Y 198, the second and third inputs of which are connected to the first 169 and second 49 (1) the inputs of the Y_MRAM node 148, respectively, the clock input 96 of which is connected to the clock input of the Y_DMRAM node 199, the second input of which is connected to "power", and the reset input of which is connected to the reset input of the Y_Y node 198 and is the reset input 97 of the Y_MRAM node 149, bidirectional input-output 43 of which is a bidirectional input-output node Y_DMRAM 199, and the sixth group of inputs of the node Y_Y 198 is connected to the groups of outputs K_L 196, K_H 197.

The YYB receiver node (YYB_REC) 148 includes a first data receiving node (MB_REC0) 202, a second data receiving node (MB_REC1) 203, a third data receiving node (MB_REC2) 204, a control signal generating node (C_CSS) 205, a first group of inverters 206, and a second inverter group 207, the output group of which is connected to the first group of inputs of the control signal generation node 205, the first to twelfth output groups of which are the first to twelfth (42,46,173:180) output groups of the receiver node YYB_REC 148, the first group of inputs 48 of which is connected with the second group of inputs of the control signal generation node 205, the thirteenth group of outputs of which is connected to the information inputs of the first 202 MB_REC0, second 203 MB_REC1 and third 204 MB_REC2 data receiving nodes, the first output groups of which are connected to the third, fourth and fifth groups of inputs of the control signal generation node 205, and the second groups of outputs of which are the seventh 176 group of outputs of the receiver node ka YYB_REC 148, respectively, the sixth and seventh groups of inputs of the node generating control signals 205 are the second 39 and third 40 groups of inputs of the receiver node YYB_REC 148, the first input 42(1) of which is connected to the first inputs of the first 202 MB_REC0, the second 203 MB_REC1 and the third 204 MB REC2 of the data receiving nodes, the clock inputs of which are interconnected, with the clock input of the control signal generation node 205 and are the clock input 96 of the receiver node YYB_REC 148, the reset input 184 of which is connected to the reset inputs of the first 202 MB_REC0, the second 203 MB_REC1 and the third 204 MB_REC2 nodes receiving data and the reset input of the control signal generating node 205, the eighth group of inputs of which is connected to the output group of the first group of inverters 206, the group of inputs of which is connected to the group of outputs of the first 202 data receiving node MB_REC0, and the group of inputs of the second group of inverters 207 is connected to the group of outputs of the second 203 data receiving node MB_REC1, first input node generating control signals 205 is the third input 49(2) node receiver YYB_REC 148, the second groups of outputs of the data receiving nodes MR_REC0, MR_REC1, MR_REC2 are the seventh group of outputs of the receiver YYB_REC.

The YYB transmitter node (YYB_TRAN) 150 comprises a first data transmission node (TRAN0) 208, a second data transmission node (TRAN1) 209, a third data transmission node (TRAN2) 210, a transmitter control signal generating node (Y_FYS_TRAN) 211, first, second and third the output groups of which are connected to the information groups of the inputs of the first TRAN0 208, the second TRAN1 209 and the third TRAN2 210 data transmission nodes, the outputs of which are the output group 171 of the YYB_TRAN 150 node, the input groups from the first to the tenth (49,180,44,48,181-183,50,174,173) which are connected to the groups of inputs from the first to the tenth node Y_FYS_TRAN 211, the eleventh and twelfth groups of inputs of which are connected to the groups of outputs of the first TRAN0 208 and second TRAN1 209 data transmission nodes, the enabling inputs of which are interconnected, with the enabling input of the third TRAN2 210 data transmission node and are the second 182 input of the node YYB_TRAN 150, the third 183 input of which is connected to the TCLK of the first TRAN0 208, the second TRAN1 209 and three Thiego TRAN2 210 data transmission nodes, the clock and reset inputs of which are connected to the clock 96 and reset 97 inputs of the YYB_TRAN 150 node, the first input 45(1) of which is connected to the first input of the Y_FYS_TRAN 211 node.

The Y_MKO node 151 includes a subaddress data generating node (Y_FDP) 212, a terminal device control node (Y_YOU) 213, a data receiving node (REC_OU) 214, a coding node (CODER) 215, a decoding node (DECODER) 216, an error detection node (DETECTOR) 217 and controller 218, the first group of outputs of which is the second control group of outputs 46 of the system controller 26 and is connected to the first and second inputs of the CODER 215 node and to the first groups of inputs of the nodes Y_YOU 213 and CODER 215, the first group of outputs Upr_coder of which is connected to the second group of inputs node Y_YOU 213, the first group of outputs 219 of which is connected to the first groups of inputs of the data receiving node REC_OU 214, the error detection node 217 and the controller 218, and the second group of outputs is the fourth group of outputs 104 of the MKO node 151, the first input 64 of which is connected to the first input of the node DECODER 216, the first group of outputs 220 of which is connected to the second group of inputs of the node REC_OU 214, the first 221, the second 222 and the third 223 gr The output groups of which are connected to the second, third and fourth groups of inputs of the controller 218, the second, third, fourth, fifth groups of outputs and the inverse output of which are the first control group of outputs 45 Upr2_contr of the YYB 26 system controller, which is also connected to the first group of inputs of the Y_FDP node 212 , the first group of outputs of which is connected to the fifth group of inputs of the controller 218, the first output 224 of which is connected to the first input of the node REC_OU 214, the fourth group of outputs 225 of which is connected to the sixth group of inputs of the controller 218 and to the third group of inputs of the node Y_YOU 213, the fourth group of inputs of which connected to the third group of inputs of the node REC_OU 214 and the second group of outputs 226 of the node DECODER 216, the clock and reset inputs of which are connected to the clock and reset inputs of the nodes Y_YOU 213, REC_OU 214, CODER 215, DECODER 216, error detection 217, controller 218 and are clock 96 and reset 97 inputs of the node Y_MKO 151, second 170, third 173, fourth I 174 and the tenth 180 input groups of which are connected to the second, third, fourth and fifth input groups of the Y_FDP 212 node, respectively, the second and third groups of outputs of which are connected to the seventh and eighth groups of inputs of the controller 218, the second and third outputs of which are connected to the first and second the inputs of the error detection node 217, the output of which is connected to the first input of the controller 218, the second input of which is connected to the "power", the groups of inputs from the ninth to the thirteenth of the controller 218 are connected to the "case", and the fourteenth group of inputs is connected to the second and third groups of outputs of the node CODER 215, the third input of which is connected to the "case", and the fourteenth group of inputs of the Y_MKO 151 node is connected to the inverse groups of inputs of the nodes Y_YOU 213, REC_OU 214, controller 218 and is the eighth group of inputs 102 of the system controller YYB 26, and the fifth group of outputs of the controller 218 connected to the fifth group of inputs of the node Y_YOU 213, the third, fourth, fifth and sixth groups of outputs which are the groups of outputs VM6,7MOD(2:0) 183, MB_TEST(2:0) 182, Upr_MKO, FSH1,2VM6,7REN 181 of the node Y_MKO 151, the fifth group of inputs 175 of which is connected to the sixth group by the input of the node Y_YOU 213, and the first 172, sixth 176, seventh 177, eighth 178, ninth 179, twelfth 47, thirteenth 50 and fourteenth 95 groups of inputs of the node Y_MKO 151 are connected to the sixth, seventh, eighth, ninth, tenth eleventh, twelfth and thirteenth groups of inputs of the node Y_FDP 212, and the seventh group of outputs of the node Y_YOU 213 is connected to the second group of outputs 42 of the node Y_MKO 151.

The receiver node REC_OU 214 includes a node for determining the beginning of the exchange format with the selection of command words and data words (Y_ONFO) 227 and a decoder 228, the first to seventh output groups of which are the fourth group of outputs 225 of the REC_OU node 214, which also includes signals connected to the output of the decoder 228 and with the first group of outputs of the node Y_ONFO 227, the second group of outputs of which is connected to the first group of inputs of the decoder 228 and is the first group of outputs 221 of the node REC_OU 214, the second group of outputs 222 of which is connected to the third group of outputs of the node Y_ONFO 227, the fourth group of outputs which is connected to the second group of inputs of the decoder 228 and is the third group of outputs 223 of the node REC_OU 214, the first 220, second 226 and third 219 groups of inputs of which are connected to the first, second and third groups of inputs of the node Y_ONFO 227, the inverse group of inputs of which is connected to the inverse group inputs 102 node REC_OU 214, the first input 224 which is connected to the input node and Y_ONFO 227, the clock and reset inputs of which are connected to the clock and reset inputs of the decoder 228 and are the clock 96 and reset 97 inputs of the REC_OU 214 node, with the first and second inputs of the decoder 228 connected to the “case”.

Operation of a computer system with a cold reserve.

VSKhR is designed to solve information and calculation problems, increased reliability in the event of an external destructive flow of particles and radiation, implemented as part of on-board software (hereinafter referred to as BPO), consisting of special software (hereinafter referred to as SPO), and general software (hereinafter - ΟΠΟ).

Depending on the index of the use case (type of STR), the ARMS can be used as:

- central on-board computer;

- computational multichannel detection and homing system.

Structural diagram of the VCR is shown in Fig.1.

The WCR includes:

- recovery control device (hereinafter - YYB);

- two redundancy channels for computers (hereinafter referred to as VM) operating in a cold standby;

- BPO VM.

ΥΥΒ provides the solution of the following tasks:

- the inclusion of only one VM at a particular point in time;

- functioning as a terminal device 34 (hereinafter referred to as OU) via a multiplex information exchange channel GOST Ρ 52070-2003 (hereinafter referred to as MKIO);

- streaming recording and storage of the results of the work of ΟΠΟ and open source software;

- testing of the PF sensor;

- reception of signals: time stamp 59, start of movement 56, external influence 57 (data from the PF sensor);

- analysis of the results of the background control of the VM operation;

- switching from one VM to another in case of negative results of the background control of the VM operation;

- switching from one VM to another according to the signals of the PF sensor;

- introduction of a unified scale of onboard operating time from the moment of switching on, from the moment of the start of movement and from the moment of the end of the last impact recorded by the PF sensor;

- generation and output of data via telemetry channel (hereinafter referred to as TMK);

ΥΥΒ consists of the following main nodes:

- the movement node 30 provides fixation of the fact of the beginning of the movement of the VSR according to the signal the beginning of the movement;

- PF sensor unit 27 provides testing and registration of PF sensor signals;

- time node 31 provides the reception of the time stamp signal;

- reserve control node 29 ensures switching off and on of the VM power units;

- RESET POWER 33 node provides RST 103 signal generation (power reset);

- the MRAM 28 node provides storage of the results of the work of ΟΠΟ and open source software in a stable MRAM memory;

- TMK node 32 provides broadcasting of telemetry data via telemetry interface (TID, TIR) 101;

- the system controller YYB 26 provides the exchange of service, telemetric information between YYB and VM via the LVDS interface (nodes YYB_REC, Y_TRAN, Y_MRAM);

- UVV 34 ensures the operation of one interface device in accordance with GOST Ρ 520-2003 in the OS mode with a coupler connected to the main bus without a matching transformer for communication with ground equipment;

- 12 MHz generator 35 sets the operating frequency for the system controller ΥΥΒ 26;

- filtration unit 36 provides electromagnetic compatibility for primary power circuits;

- power node 37, providing digital power 3.3 V YYB from the primary power circuits;

VM provides the following tasks:

- functioning as an OS according to GOST Ρ 52070-2003;

- functioning as four bus controllers (hereinafter - UVV) in accordance with GOST Ρ 070-2003;

- formation of telemetry data;

- functioning as an Ethernet controller UBB 3;

- execution of algorithms implemented as part of ΟΠΟ and open source software in PROM 15 and in PROM 16;

- regular saving of the results of the work of ΟΠΟ and open source software in the stable memory MRAM YYB 28;

- loading previously saved results of ΟΠΟ and SPO operation when switching to another reserve from the persistent MRAM memory UUV 28.

The VM consists of the following main nodes:

- UVV 19 provides operation in accordance with GOST Ρ 52070-2003 of one interface device in the op-amp mode with a coupler connected to the main bus with matching transformers, three interface devices in the bus controller (CS) mode (with upper-level equipment (ALU)) with the coupler connected to main and reserve main bus with a matching transformer;

- the traffic and communication control unit includes a processor 1-1, RAM 2 and PROM 15 and interfaces DDR, Flash, RapidIO, RK (one-time commands), PCI, which ensure the execution of algorithms implemented in ΟΠΟ and open source software.

The DDR 68 interface ensures the interaction of the processor 1 1890 VM6Ya with 256 MB SDRAM DDR ECC RAM 2 and organization 32Mx72 (8 bits of the data bus are used to detect and correct single errors) with the following parameters:

- Operating frequency - 100 MHz.

- Bandwidth - 200 Mbps.

- Width of the data bus m / sx memory - 16 bits.

The Flash 69 interface provides for the interaction of the processor 1 1890 VM6Ya with the ROM 15 of the Flash type with a capacity of 8 MB and an organization of 8Mx8.

The address space of the PROM 15 with respect to the processor 1890 BM6I 1 is described in Fig.38, and the internal address space in Fig.39.

- The RapidIO 70 interface provides interoperability between the 1.13 1890 VM6Ya and 1890 VM7Ya processors.

- PK 75 interface provides interaction of the processor 1 1890 VM6Ya with the system controller 17 and with the nodes UUR 29, the PF sensor 27 and the movement 30 through the SK YYB 26 and SK 17.

- PCI 67 interface provides interaction between processors 1.13 1890 VM6Ya and 1890 VM7Ya, controllers UVV (18-21) GOST Ρ 52070-2003 and system controller 17, which contains registers for working with MRAM UUV 28, telemetry channel TMK 32, nodes time 31, movement 30, PF sensor 27, reserve management 29, general purpose registers.

- the detection node includes a processor 13, RAM 14 and PROM 16, DDRII, SPI, RapidIO, RK and PCI interfaces, which ensure the execution of algorithms implemented in ΟΠΟ and open source software.

The DDRII 71 interface ensures the interaction of the processor 13 1890 VM7Ya with RAM 14 of the SDRAM DDRII type with a capacity of 256 MB and an organization of 32Mx64 with the following parameters:

Operating frequency - 125 MHz.

Bandwidth - 500 Mbps.

The width of the data bus m / sx memory - 16 bits.

The SPI interface 72 provides interaction of the processor 13 1890 VM7Ya with the ROM 16 of the Flash type with a capacity of 16 MB and an organization of 128Mx1.

The address space of the PROM 16 relative to the processor 13 1890 VM7R is described in Fig.40, and the internal address space of the processor 1890 VM7R 13 when working with Flash - in Fig.41.

The RapidIO 70 interface provides interoperability between the 1.13 1890 VM6i and 1890 VM7i processors.

Interface PK 76 provides interaction of the processor 13 1890 VM7YA with the system controller 17 and with the WR 29 nodes, the PF sensor 27 and movement 30 through the SK YYB26 and SK17.

The PCI 67 interface provides interaction between processors 1.13 1890 VM6Ya and 1890 VM7Ya, controllers UVV (18-21) GOST Ρ 52070-2003 and system controller 17, which contains registers for working with MRAM YYB 28, telemetry channel TMK 32, time nodes 31, movement 30, PF sensor 27, reserve management YYR 29 general purpose registers.

- air-blast unit 3 provides communications via the Ethernet 82 interface;

Interface for providing access to processor 1 (1890 VM6Ya) from external subscribers. Interface type: Ethernet 100BASE-T.

- system controller 17 provides control of the AVU movement, synchronization of the interaction of the above nodes according to the operation algorithm and participates in the exchange of service and telemetry information with YYB via the LVDS interface (Y_BM_REC, Y_BM_TRAN, Y_TLMRAM);

- RESET POWER 22 node provides power reset generation;

- generators 4-12 set the operating frequencies for various devices and nodes;

- a node of galvanically isolated connectors 23,24 - is a connection of galvanically isolated MKIO and Ethernet interfaces through the mounting "OR" to external connectors;

- power node 25 provides 3.3 V digital power; 1.5V; 1.8V VM.

The VSHR on the M2 53 highway operates in the mode of three terminal devices OU VM1 19, OU VM2 19, OU YYB 34.

Own addresses of OU UUV 34, OU VM1 19 and OU VM2 19 are determined by the index of the system use case and are set by external jumpers. To prevent a reaction to the command word (CS) with an unreliable own address in the op-amp YYB 34, an odd parity check of the op-amp's own address is implemented using an external jumper.

OS YYB 34 is connected to the main bus M2 53 through a coupler without a matching transformer. There is no redundant trunk bus. OU VM are connected to the main bus through a coupler with a matching transformer. There is no redundant trunk bus.

For OU YYB 34, bit 10 of the command word (CS) is used as a sign of transmission of the CS (in accordance with section 4 of GOST Ρ 52070-2003). Thus, the number of available subaddresses is reduced from 30 to 15, and only the code "1111 ₁₂ " corresponds to the control command code (CU). A positive aspect of such use of this bit is a clear separation of the CS from the response word (OS), which greatly simplifies the analysis of emergency situations.

OU YYB 34 responds to messages of all formats. The "interface control accepted" bit in the OS is always set to "0". KU "Block i-transmitter" and "Unlock i-transmitter" are processed as valid invalid commands in accordance with section 5 of GOST Ρ 52070-2003.

In OS OU ΥΥΒ 34, the signs “OS transmission”, “message error”, “subscriber busy”, “CO malfunction”, “subscriber malfunction”, “group command accepted” are used in accordance with GOST Ρ 52070-2003. The "service request" and "interface control accepted" flags are not used and are set to logical zero.

The structure of the information bits of the COP received by the OS ΥΥΒ 34 is shown in Fig.42 and corresponds to GOST Ρ 52070-2003.

The structure of the OS information bits transmitted by the OS ΥΥΒ is shown in Fig. 43 and corresponds to GOST Ρ 52070-2003.

The structure of the information bits of the transmitted and received data words (SD) is shown in Fig.44 and corresponds to GOST Ρ 52070-2003.

The regular operation of the bus controller (KSh) of the GOST Ρ 52070-2003 interface with the OU UUV 34 is carried out at subaddresses from "10000 ₂ " to "10100 ₂ " and from "10101 ₂ " to "11000 ₂ ". When KSh is operating at subaddresses from “00001 ₂ ” to “01111 ₂ ” and from “11001 ₂ ” to “11101 ₂ ”, the OS UUV issues an OS with the flag “subscriber busy” and does not transmit SD in format 2.

The subaddress "11110 ₂ " is a sign of the testing mode of the OU UUV 34 and is implemented in accordance with section 4 of GOST Ρ 52070-2003.

The description of the contents of the SD when working with formats 1 and 2 is shown in Fig.45.

OUVM 19 does not function as an OS according to GOST Ρ 52070-2003 until the software initializes the 1.13 1890 VM6Ya or 1890 VM7Ya VM processors.

The PF 27 sensor unit is designed for prompt response to theoretically possible failures of a hot CM by switching to another CM, an external influence recorded by the PF 27 sensor by turning off the hot CM, waiting for the blind zone of the PF 27 sensor and then turning on another CM.

The registers of the PF sensor node are represented in the address space "1009 ₁₆ ".

External influence signals 57 DPFVOZ1, DPFVOZ2, DPFVOZ3 are received from three sensors to the PF sensor 27; 63 (a sign of exposure to damaging factors), which enters the YYR 29 node.

On the command coming from the MCO on the second group of control outputs 45 of the YYB system controller, and on the TEST signal coming from the state machine 188 YYR 29, the PF sensor test is started.

At the end of the RESET signal, the STATE state counter is at "00", setting the TIMER counter and the TEST_OUT signal to '0'. When the TEST 62 signal is present, the contents of the status and TIMER counters are incremented by '1' and the TEST_OUT signal is set to '1'. After 22 ms (the moment of reading readings from the sensors), the NORM, NOTNORM, NOTNORMRES signals are written to the register MN, MNN, MNNR, which, together with external influence 57, through the third group of outputs 95, enter the system controller YYB 26 for transmission to the multiplex channel M2 53 , TMK node 32 and to processors 1 and 13 via the PCI 67 interface. The second 55th group of outputs of the PF sensor 27 (VRR1, VRR2, VRR3) is used to expand the system.

The register of the PF sensor node 27 is available to the movement nodes 30 and reserve management 29 via the PCI interface 67 at the address "1009 ₁₆ " Fig.46. The register contains bits of the time counter since the end of the impact of damaging factors recorded by the sensor PF 27. The bits of the counter correspond to the bits of the signal "sSSSSCNT". The least significant digit of the counter contains a sign of the impact of damaging factors (“tSWITCH” signal), calculated from the signals of the PF 27 sensor, digits from 19 to 1 determine the time from the end of the impact of the PF 27 sensor from the beginning of the second (the price of the least significant digit is 3.2 μs), bits 31 to 20 determine the time since the end of the impact of the sensor PF 27 damaging factors in seconds. When a sign of the impact of damaging factors occurs, the time counter goes into the state of waiting for the removal of this sign. After that, the time counter remembers the time when the sign of the impact of damaging factors was removed and considers the time as a method for calculating the difference between the current time and the stored time. If there is no time stamp 59, the current time is calculated by the internal generator, and if there is, by the external signal of the time stamp 59.

The reserve control node 29 is designed to control the switching of VM1 and VM2. The YYR 29 consists of a state machine (MS) 188, an ASR node 187, a valid determination node 1 189, a valid determination node 2 190, a reaction mode determination node YYR 191.

Functional diagram YYR 29 is shown in Fig.6.

The operation diagram of MS 188 for controlling VM1 and VM2 is shown in figures 23 and 24, where "sMKOLIVE" - artificial fitness, "sMKOSTRT" - exchange at subaddress 19 MKO, "ΡΟΝ1" - switching on the secondary power source (VIP) VM1, "ΡΟΝ2" - turning on the VIP VM2, "CON1" - frequency supply to VM1, "CON2" - frequency supply to VM2, "TOM" - data transfer to VM1, "ΤΟΝ2" - data transfer to VM2, "sT" - time counter, "sPOWST "- the state of the machine, "sVMLIVE" - the hardware suitability of the VM, "sS" - a sign of the impact of damaging factors of a nuclear explosion (from MS 188), "sL" - a sign of the availability of the reserve (from the node for determining the reaction mode 191), "V" - a sign impact of the damaging factors of a nuclear explosion during normal operation, "sT1" - turn-on time counter BM1, "sT2" - turn-on time counter BM2, and consists of 15 states.

In state 0 MS 188 gets when you turn on UUV signal "RESET". In this state, VM1 and VM2 are turned off, the counters, except for the time counter, are reset to "0". MS 188 is in this state until the parameter “sSRV” is received from the system controller YYB 26 via the UPR1_MKO 46 bus from the YYB 26 system controller, which determines the device operation mode (standard or technological). After the “sSRV” parameter is received, the MS 188 sends a signal 62(1) to the ASR 187, which generates the PON1 signal 98, which turns on the VTS 25 BM1, supplies the reference frequency CLK 96, resets the time counter to “0” and passes to state 1.

State 1 is intended to wait for the end of the hardware processes associated with the inclusion and initialization of VM1. In this state, the machine starts the time counter. If impact 57 has arrived, then MS 188 will turn off VM1, remove the reference frequency CLK 96 and go to state 6. If there is no impact, then the time counter continues to count up to 200 ms. In this case, if the hardware health of VM1 is fixed before the time counter reaches 200 ms, then the MS 188 will start transmitting data to VM1 and go to state 2. If the time counter has counted up to 200 ms and the hardware health of VM1 is not fixed, then ASR 187 fixes a hardware failure VM1 and MS 188 transition to state 5.

State 2 is the main operating state of VM1. In this state, only BM1 is turned on, and the MS 188 analyzes the sign of validity (sL) of BM1. If the sign of validity is not fixed, then MS 188 remains in this state. If, however, during the main work will be recorded impact 57, then MS 188 will go to state 3 (signal SWITCH 63 from the node DFT 27).

In state 3, MS 188 for 1.7 μs prohibits the transmission of data and the reference frequency to VM1, after which it will go to state 4.

In state 4 MS 188 waits for 4 µs to turn off the reference frequency and determines the reason for the switch - impact or not. In the case of switching due to the influence of the MS 188, it will turn off the VM1 and go to state 7. If the switch occurred due to the absence of the VM1 validity signal, then the MS 188 will turn off the VM1, start the time counter for 10 ms, setting the value "88" to it to provide a pause in 10 ms, and will go to state 5.

State 5 is designed to form a correct pause before turning on the VM2. As soon as the time counter has counted to a value equal to or greater than 98 ms, and, at the same time, BM2 has been turned off for more than 500 ms, then the MS 188 will turn on BM2, apply the reference frequency, reset the time counter to "0" and go to state 9 .

MS 188 is in state 6 until the end of exposure 57. At the end of exposure 57, MS 188 will reset the time counter and go to state 5.

State 7 according to the operation algorithm is similar to state 6.

States 8-14 are designed to work with VM2 and, according to the operation algorithms, they are similar to states 1-7, respectively, with the only difference that VM1 is replaced by VM2, and VM2 is replaced by VM1.

Note: For states 1-7, the on-time counter BM2 is permanently decremented, and for states 8-14, the on-time counter BM1 is constantly decremented. These counters are necessary to avoid situations in which the same VM would turn off and then turn on in less than 500 ms.

The sign of the validity of the switched on VM (signal "sL") consists of the signs of the LIVEBM equipment and two signs of the validity of the control and communication nodes (signal LIVEGOOD1 (UPR_G1)) and detection (signal LIVEGOOD2 (UPR_G2)) and is necessary for the prompt response of the system to a failure by switching to another known good reserve, and not an attempt (series of attempts) to restore lost data. In the case of degradation of the element base of the system as a result of the impact of damaging factors of a nuclear explosion, this approach uses the property of "annealing" of the element base, which prolongs the time of successful operation of the system as a whole.

If YYB registered a hardware failure, then the signal "sL"=0.

From the moment the VM is turned on, within a time of 1000 ms, the power is turned on, the reset signals of the processors (1890 VM6Ya) 1 and (1890 VM7Ya) 13 are set and removed, and the primary software is loaded. The signal "sL" during all this time is "1" until the processor (1890 BM6R) 1 starts working.

The processors work independently. If at least one of them fails, then "sL"=0, which indicates the unsuitability of the VM and access to the resources of the persistent memory MRAM 28 is closed.

The "start time" of the processor (1890 VM6Ya) 1 is determined by the fact of the first increase in the counter of the integrated validity code (ICG) "sVM6LIVEINC" by "1". The "start time" of the processor (1890 VM7Ya) 13 is determined by the fact of the first increment of the counter of the integrated expiration code "sVM7LIVEINC" by "1".

The algorithm of operation of the site switching reserve 187 is shown in Fig.14,14a.

The failover switch node 187 defines the on/off pattern of the system's internal nodes against the background of the VM switchover.

The operation algorithm of the reaction mode determination unit 191 is shown in Figs. 13 and 13a.

The node for determining the response mode 191 is designed to determine the response mode to influences and determine the VMs that transmit telemetry information depending on the suitability of the processors.

The reaction mode determination unit 191 determines the presence of valid data from the VM based on the signs of their suitability.

The response mode determination node 191 determines the response mode of the HCW depending on the operating mode of the PF sensor node.

Three modes are defined:

standby mode Tstest="00";

exposure mode Tstest="01";

PF sensor mode Tstest="10";

Movement node 30 is designed to fix the start of movement

Functional diagram of the movement node 30 is shown in Fig.7.

Node motion 30 consists of the first 192 and second 193 pulse analyzers, the first 194 and second 195 generators.

The operation algorithms of the movement node of the Y_TRIMP and Y_RCIMP schemes are presented in Figs. 16, 17, 17a.

Pulse analyzers (192, 193) are designed to monitor and detect the presence of pulses of a given duration. Pulse generators (194, 195) are designed to generate these pulses.

The register of the motion node 30 is available to the "motion control and communication" and "detection" nodes via the PCI interface 67 at the address "1008 ₁₆ ", see Figs. 46, 46a, 46b. The register contains bits of the time counter and is available for reading. The bits of the counter correspond to the bits of the "sMOVECNT" signal described in FIGS. 45, 45a. The least significant digit of the counter contains a sign of the beginning of movement (signal "sMOVE"), which occurs when the signal "Start of movement" 56 appears.

The sign is set to zero only when the UUV is turned on. After the occurrence of a sign, the time counter remembers the time when the sign occurred and considers the time as a method of calculating the difference between the current time and the stored time. If there is no time stamp 59, the current time is calculated by the internal generator, and if there is, by the external signal of the time stamp 59.

The time node 31 is designed to count the time from the moment the device is turned on, the start of the movement of the object, and from the moment the impact ends.

The algorithm of the node time 31 is shown in Fig.15, 15a, 15b.

The register of the time node 31 is available to the "motion control and communication" and "detection" nodes via the PCI interface 67 at the address "1007 ₁₆ ", see Fig.46c.

The register contains the bits of the counter, which correspond to the bits of the signal "sTIMECNT" described in Fig.45, 45a. The least significant digit of the counter contains a sign of the absence of the time stamp signal 59, which occurs if the edge of the external signal of the time stamp 59 does not arrive within 1.5 s. The digit is reset to zero immediately after the appearance of the edge of the external signal of the time stamp 59. there is no time stamp 59, the time calculation is carried out according to the internal YYB generator 35. Any correction of the bits of the “sTIMECNT” signal when the external signal of the time stamp 59 appears or disappears is not required, however, differences in the accuracy of time calculation should be taken into account. The value of the "sTIMECNT" signal is also broadcast via the TMI 101 interface (TID, TIC).

The MRAM 28 YYB persistent memory unit is designed to store information that requires protection from special influencing factors.

The MRAM 28 YYB persistent memory node is available to external subscribers via the M2 53 bus and the "motion and communication control" and "detection" nodes via the PCI 67 interface.

The registers and flags of the MRAM YYB interface of the control node are presented in the address space "1002 ₁₆ ", "1003 ₁₆ ", "1004 ₁₆ ", "1005 ₁₆ " (see figa, 46b, 46c) and are designed to manage read caches and caches records, which are used to read data from the MRAM 28 and write data to the MRAM 28, respectively. The write caches of the MRAM 28 memory are located in the address space "0000 ₁₆ " - "01FF ₁₆ " and "0200 ₁₆ " - "03FF ₁₆ ". The MRAM 28 memory read caches are located in the address space "0400 ₁₆ " - "05FF ₁₆ " and "0600 ₁₆ " - "07FF ₁₆ ". (See FIG. 46) The read and write caches of the MRAM 28 are independent and can be operated in parallel.

General purpose registers R1 - R3 available to both processor 1 (1890 VM6Ya) and processor 13 (1890 VM7Ya) are located in the address space "1010 ₁₆ " - "1012 ₁₆ " (see Fig.46 d).

The persistent memory node 28 YYB supports both the normal (non-secure) mode of operation and the protected mode (in the mode of using the Hamming code for data protection).

The subscriber of OS YYB 34 has access to PROM 15, 16 VM, MRAM 28 (persistent memory) of 4 MB in Hamming mode and 8 MB without Hamming mode and RAM of the TMK node. The total address space of the VSHR system when accessed through the OU YYB 34 (channel M2) is shown in Fig.49. Each address operates 32 bits of data (signals "sMKODW", "sMRAMDR", "sBMD"). When working with persistent memory in Hamming mode (signal "sHAMMING" = 1), each address operates 32 bits of data, and without Hamming mode - 64 bits of data. Note - Processors 1.13 (1890 VM6Ya or 1890 VM7Ya) VMs work with persistent memory only in Hamming mode.

When enabled, the subscriber OU YYB 34 analyzes the current versions of YYB FPGA and FPGA VM with versions recorded in MRAM 28 (resistant memory) at the address "700010 ₁₆ ". If there is a mismatch, the versions in MRAM 28 (resistant memory) are replaced by the current versions, and the operating time parameters of the system located in MRAM 28 (resistant memory) at addresses "700000 ₁₆ " - "70000F ₁₆ "are reset to "0".

PROM control commands are presented in Fig.50.

The OS VM does not function as an OS according to GOST Ρ 52070-2003 until the software initializes the processors 1.13 1890 VM6Ya or 1890 VM7Ya VM.

In the protected mode of operation (signal "sHAMMING"=1), a Hamming code is used, and data is exchanged via 32-bit data words protected by 32 extra bits of the Hamming code (see FIG. 47). In the normal mode of operation of the system (signal "sSRV"=1, see Fig.45) for data exchange between the nodes "control and communication" and "detection" and node persistent memory MRAM 28 UUV uses only protected mode.

All 32 bits of the data word are conditionally divided into 12 groups, each of which is assigned to one of the three reliability groups.

The first group of reliability is characterized by the fact that 1 bit of the data word is encoded using 2 bits of additional Hamming code. Thus, this group allows the appearance and correction of one error per 3 bits of a protected word by the Hamming code.

The second reliability group is characterized by the fact that 2 bits of the data word are encoded using 3 bits of an additional Hamming code. Thus, this group allows the occurrence and correction of one error per 5 bits of a protected Hamming code word.

The third reliability group is characterized by the fact that 4 bits of the data word are encoded using 3 bits of an additional Hamming code. Thus, this group allows the appearance and correction of one error per 7 bits of a protected Hamming code word.

The Hamming-protected word has 4 first reliability groups, 2 second reliability groups, and 6 third reliability groups (see Fig. 47) and can correct up to 12 errors, provided they occur in different groups.

The TMK 32 node is intended for transmission of telemetric information (ТMI 101).

The transmission process of the TMI 101 consists of sending frames.

The transfer process of TMI is carried out only in one direction without a guarantee of delivery, i.e. VSHR does not generate responses to frames transmitted from it.

For storage and transmission of TMI 101, two RAMs are organized in the VSKhR, each with 2 banks with a capacity of 4 KB each. The first RAM (RAM1) is intended for recording the TMI generated by the processor 1 1890 VM6Ya. The second RAM (RAM2) is designed to record information generated by the processor 13 1890 VM7Ya. At the same time, in the general software (ΟΠΟ) and special software (SPO) of the VSHR, it is possible to fill the banks of RAM 1 and RAM 2 both by means of the processor 1 1890 VM6Ya and the processor 13 1890 VM7Ya.

TMI from VSHR is transmitted as a set of frames. The frame structure is shown in Fig.48. Each frame is a sequence of packets (eight mandatory packets, A packets (from 1 to 1024) with RAM 1 data and B packets (from 1 to 1024) with RAM 2 data, ending with an interframe pause. The total number of packets in a frame is from 10 to 2056. The minimum value of the interframe pause must be equal to the transmission time of one packet.The maximum value of the interframe pause is determined by the efficiency of the transmission initiator.

When the system is turned on or when switching to a reserve, the initiator of frame transfer is the TMK 32 telemetry channel controller until the start of processors 1.13 1890 VM6Ya or 1890 VM7Ya (hardware telemetry with parameters A=1 and B=1, packages 9 and 10 contain "garbage" values), after which either processor 1 1890 VM6R or processor 13 1890 VM7R (software telemetry with program control of parameters A and B) becomes the initiator of frame transmission. When switching to the reserve, the transmitted frame may be interrupted, and the inter-frame pause may reach a value equal to the switching time to the reserve. The “startup moment” of the 1890 VM6R processor is determined by the fact that the counter of the integrated expiration code “sVM6LIVEINC” is incremented by “1” for the first time. The "start time" of the 13 1890 VM7Ya processor is determined by the fact of the first increase in the counter of the integrated expiration code "sVM7LIVEINC" by "1".

The telemetry data packet is encoded by two signals "TLD" (data) and "TLC" (frequency) 101 (the third group of system outputs). The frequency of issuing the “TLC” signal and, accordingly, the duration of the packet in time depend on the value of the signal “TLV” (the second control group of outputs 45 of the YYB 26 system controller) (with “TLV” = 1, this corresponds to a transmission frequency equal to (1.5 ± 0 .0225) Mb/s, with "TLV"=0 this corresponds to a transmission frequency equal to (0.5±0.0075) Mb/s). The packet consists of 32 bits of data and a pause of 3 μs. The structure of the packet with an example of data transmission "80000000 ₁₆ " is shown in Fig.51. The values of the signals "TLC" and "TLD" at the moment of pause and interframe pause are equal to zero.

Packet 1 and Packet 2 are identical and contain the data value "ΒΒΒΒ5555 ₁₆ ", defined as the frame header. Packet 3 contains the hardware state, the decoding of which is shown in Fig.52, 52a and 53.

Packet 4 contains the number of the transmitted frame. When VSHR is enabled, the initial value of the number of the transmitted frame will become equal to one, and when the reserve is switched, it will continue numbering.

Package 5 contains parameters A, B. The value of parameter A corresponds to the number of TMI packages in RAM1 (the number 1024 is encoded by the code "0000000000 ₂ "). The value of parameter B corresponds to the number of TMI packets in RAM2 (the number 1024 is encoded by the code "0000000000 ₂ ").

Packet 6 contains the signal "sTIMECNT", packet 8 - the checksum of the information presented in packets 1 - 7. The decoding of packets 6-8 is shown in Fig.54.

Note - The algorithm for calculating the checksum of packets 1-7 is shown in Fig.55.

Digit 31 of package 3 indicates the operating mode of the software part of the VSHR: regular (value "1") or technological (value "0"). By default, VSKhR is switched on in the technological mode.

Bit 30 of packet 3 indicates the opening of access to MRAM resources 28 and telemetry from processors 1.13 1890 VM6Ya and 1890 VM7Ya. If the value is "1", then access is open, if "0" - then access is closed. The formation of the discharge occurs on the basis of the correct change in the validity codes of both processors 1.13. After the first correct change of the validity codes, access to the resources of MRAM 28 and telemetry opens no later than 20 µs.

Bits 29 and 28 of packet 3 indicate the switching status. When you turn on the VM for the first time since the last time you turned off the VSHR p. 29 and 28 take the value "3". In the case of switching from one VM to another, the p data will change its value, which will indicate the reason for the switch: "0" - switching on command from the M2 53 trunk, "1" - switching in the event of a VM failure, "2" - switching in the event of operation PF sensor.

Bit 26 of packet 3 indicates the mode of technological control of the multiplexers. In this mode, the management of the rack memory MRAM 28 is intercepted by the M2 53 bus. The value "1" means that this mode is enabled, "0" - that it is disabled. The mode is turned on and off by writing "1" and "0", respectively, to the "sMBMKO" signal in accordance with Fig.45. The mode can be enabled only in the technological mode of the system and is used only when working with stable memory MRAM 28 via the M2 53 bus.

Bit 25 of packet 3 indicates the recording mode. If the value of the signal "sMBMKO" is "0", this mode indicates that data is being written to the stable MRAM memory by 28 processors 1.13 1890 VM6Ya and 1890 VM7Ya. Bits (24:22), (11:14) of packet 3 denotes a switch flag and is described below.

To carry out TMI reception from the system controller UUV 26.

If the VSHR functions normally according to the program written into it, taking into account the operation of the algorithms for the operation of processors 1.13 with an integrated PCI 67 validity code, then package 3 will contain the binary code x1ab_c0xx_xx00_1000_0xxx_x11x_xxx0_xxxx, where x is arbitrary data, ab corresponds to p. 29 and 28, respectively, and should not be equal to the code "01 ₂ ".

Deciphering the “sSWITCHINF” signal (information about the reasons for switching, p. 29, 28 of package 3 correspond to p. 1, 0 of the “sSWITCHINF” signal, respectively, p. 24-22 of package 3 - p. 4-2, p. 14-11 of the package 3 - R. 8-5) is presented in Fig.56.

Bit 21 of package 3 indicates the mode of supplying a reset signal to processors 1.13 1890 VM6Ya and 1890 VM7Ya. The value of "1" means that the reset signal is on, "0" is off. The mode is turned on and off by writing "1" and "0", respectively, to the "sMKOVM67RST" signal in accordance with Fig.45. The mode can be enabled only in the technological mode of the VSHR and can be used to restart the processor without the operation of switching the VSHR off and on.

Bit 19 of Packet 3 denotes the hot VM hardware health indication and is calculated based on the signal output from YYB to the VM and relayed back to YYB. If the signal that came back to YYB is valid, then the hot VM hardware is considered good. The value "1" means that the equipment of the hot VM is good, "0" means that it is not good. If the hot VM hardware fails, YYB initiates a failover.

Bit 16 of packet 3 occurs in the event of a PLL1 YYB 152 block failure. 16 is "0". If the input frequency does not meet the specified requirements, then the input frequency invalid signal goes into the active level, and the value of p. 16 is equal to "1". R. 16 is a sign of a malfunction and does not reflect the current state. Used to log the occurrence of a fault.

Bit 15 of packet 3 occurs when the PLL2 YYB 153 block fails. 15 is "0". If the input frequency does not meet the specified requirements, then the input frequency invalid signal goes into the active level, and the value of p. 15 is "1". R. 15 is a sign of a malfunction and does not reflect the current state. Used to log the occurrence of a fault.

Bit 10 of packet 3 denotes the validity of the 1890 VM6A processor 1. The value "1" means that the processor regularly changes the expiration counter, "0" - that the processor does not work correctly.

Bit 9 of package 3 indicates the validity of the processor 13 1890 VM7Ya. The value "1" means that the processor regularly changes the expiration counters, "0" - that the processor does not work correctly.

Bit 8 of package 3 is a sign of the arrival of the “start of movement” signal 56, which occurs when the connection between the inputs and outputs of the signal “Start of movement 1” is closed or the connection between the inputs and outputs of the signal “Start of movement 2” is closed in the connector. The value "1" means the presence of the signal "the beginning of the movement" 56, "0" - the absence.

Bit 6 of packet 3 denotes a sign of double incrementation of the integrated validity code by the processor 1 1890 VM6R in a period of less than 5 μs, and is relevant only when the value of p. 29 and 28 equal to the code "01", respectively.

Bit 5 of packet 3 denotes a sign of double incrementation of the integrated validity code by the processor 13 1890 VM7R in a period of less than 5 μs, and is relevant only when the value of p. 29 and 28 equal to the code "01", respectively.

Bit 4 of packet 3 occurs in the event of a malfunction of the PLL block BM 112. If the input frequency per block corresponds to 44 MHz with a duty cycle of (50 ± 5)%, then the internal signal of the invalid input frequency is inactive, and the value of p. 4 is "0". If the input frequency does not meet the specified requirements, then the input frequency invalid signal goes into the active level, and the value of p. 4 is equal to "1". R. 4 is a sign of a malfunction and does not reflect the current state. Used to log the occurrence of a fault.

Bits 3-0 of packet 3 indicate the current state of YYB switchover MS 188.

In RAM for RAM 1 and RAM 2 there are three bit flags of Fig.57:

- flag for telemetry data transmission ("START" flag);

- flag for switching the memory bank available for writing (for RAM 1 and RAM 2) (flag "ΒΑΝΚ");

- indicator of readiness for transmission (flag "READY").

The state of the flag "START" can be controlled using ΟΠΟ and SPO VSKhR, the state of the flags "ΒΑΝΚ" and "READY" is changed automatically by the TMK 32 controller. The meaning of the states of the flags is shown in Fig.57.

The system controller VM 17 provides control of the movement of the upper-level equipment and participates in the exchange of service and telemetry information with YYB via the LVDS interface (Y_BM_REC, Y_BM_TRAN, Y_TLMRAM);

The VM system controller 17 consists of a start diagram node 106, a PCI interface node 107, a PCI memory node 108, a node for receiving information from LVDS Y_BM_REC 109, a memory node for the telemetry channel Y_TLMRAM 110, and a node for transmitting to the LVDS bus Y_BM_TRAN 111.

Functional diagram of the node receiving information from the LVDS 109 is shown in Fig.3.

The LVDS Information Receiving Unit (Y_BM_REC) 109 provides for decoding the serial LVDS code into a parallel code.

The node for receiving information from LVDS (Y_BM_REC) 109 consists of the first node REC0 138, the second node REC1 139, the third node REC2 140 and the node generating control signals (Y_FYS_BM_REC) 141, the first group of inverters 142, the second group of inverters 143.

The algorithm of the node generating control signals (Y_FYS_ BM_REC) 141 of the receiver VM is shown in Fig.35.

Functional diagram of the node for transmitting information to the bus LVDS(Y_BM_TRAN) 111 is shown in Fig.4.

The node for transmitting information to the bus LVDS (Y_BM_TRAN) 111 provides the conversion of the parallel code into a serial code.

The node for transmitting information to the LVDS bus (Y_BM_TRAN) 111 consists of the first node TRAN0 144, the second node TRAN1 145, the third node TRAN2 146 and the node for generating control signals of the transmitter Y_FYS_BM_TRAN 147.

The algorithm of the node generating control signals of the transmitter Y_FYS_BM_TRAN 147 is shown in Fig.36.

The memory node telemetry channel Y_TLMRAM 110 provides data storage for telemetry.

The algorithm of the memory node telemetry channel Y_TLMRAM 110 is shown in Fig.37, 37a, 37b.

The YYB 26 system controller organizes the data exchange of the YYB 26 recovery control device with VM1 and VM2 (via the LVDS interface), via the M2 highway (input-output device 34), TMK 32 nodes, MRAM 28, PF sensor 27, reserve control 29, movement 30 and time 31.

Functional diagram of the system controller YYB 26 is shown in Fig.5.

The YYB system controller 26 includes a data receiving node (YYB_REC) 148, an external memory management node (Y_MRAM) 149, a data transmission node (YYB_TRAN) 150, an MCO node 151, a first PLL 152, a second PLL 153, a first multiplexer 154, a second multiplexer 155, first trigger 156, second trigger 157, first element AND 158, second element AND 159, third element AND 160, fourth element AND 161, fifth element AND 162, element 3AND-OR 163, first element OR 164, second element OR 165, first a group of multiplexers 166, a second group of multiplexers 167.

The data transmission node (YYB_TRAN) 150 contains the first node TRAN 0 208, the second node TRAN 1 209, the third node TRAN 2 210, the node generating control signals of the transmitter Y_FYS_TRAN 211.

Functional diagram of the data transmission node (YYB_TRAN) 150 is shown in Fig.10.

Node YYB_TRAN 150 provides the conversion of parallel code to serial.

The algorithm of the node YYB_TRAN 150 is shown in Fig.19.

The node for generating control signals of the transmitter Y_FYS_TRAN 211 provides switching of input data for serial transmission over the LVDS interface.

The algorithm of the node Y_FYS_TRAN 211 is shown in Fig.20.

Node Y_FYS_TRAN 211 provides input data switching for serial transmission over the LVDS interface.

The YYB receiver node (YYB_REC) 148 includes a first data receiving node (MB_REC0) 202, a second data receiving node (MB_REC1) 203, a third data receiving node (MB_REC2) 204, a control signal generating node (C_CSS) 205, a first group of inverters 206, and a second inverter group 207.

Functional diagram of the node receiver YYB_REC 148 is shown in Fig.9.

Node YYB_REC 148 provides the conversion of serial code to parallel.

The algorithm of the node YYB_REC 148 is shown in Fig.21.

The node for generating control signals U_FUS 205 converts the signals received via the LVDS interface into control signals of the system.

The operation algorithm of the node generating control signals U_FUS 205 is shown in Fig.22.

The external memory management node (Y_MRAM) 149 generates a timing diagram for the external memory.

Functional diagram of the external memory management node (Y_MRAM) 149 is shown in Fig.8.

The external memory control node (Y_MRAM) 149 contains the encoder_L (K_L) 196, the encoder_H (K_H) 197, the MRAM control node (Y_YMRAM) 198, the MRAM timing diagramming node (Y_DMRAM) 199.

The operation algorithm of the MRAM control node 198 is shown in Fig.23.

Y_YMRAM 198 generates control signals for a two-port memory access switch (Y_DMRAM) 199.

FIG. 24 shows the operation of the Y_DMRAM node 199, which generates the MRAM timing diagram.

FIG. 25 shows the operation of the HAMMING_CODER nodes (encoder_L 196, encoder_H 197) that encode 32-bit data words with 32 extra bits of the Hamming code in accordance with FIG.

26, 26a shows the operation of the HAMMING_DECODER nodes (decoder_L 200, decoder_H 201) that decode 32-bit data words with 32 additional bits of the Hamming code in accordance with Fig.47.

Node MCO 151 provides communication VSHR channel MCO with the upper level system.

Functional diagram of the MCO node 151 is shown in Fig.11.

The MKO node 151 includes a subaddress data generating node (Y_FDP) 212, a terminal device control node (Y_YOU) 213, a data receiving node (REC_OU) 214, a coding node (CODER) 215, a decoding node (DECODER) 216, an error detection node (DETECTOR) 217, controller (CONTR) 218.

The subaddress data generating node (Y_FDP) 212 determines the format number and its basic features for the OU response in accordance with GOST R52070.2003.

The algorithm of work Y_FDP 212 is shown in Fig.27, 27a, 27b.

Terminal control node (Y_YOU) 213 generates an error when an incorrect address is selected.

The operation algorithm of the terminal control node (Y_YOU) 213 is shown in Fig.28.

The data receiving node (REC_OU) 212 provides, depending on the input features, the address direction of the data.

Functional diagram of the receiver node OU (REC_OU) 214 is presented in Fig.12.

The Receiver OU node (REC_OU) 214 contains a node for determining the beginning of the exchange format with the allocation of command words and data words (Y_ONFO) 227 and a decoder 228.

The algorithm of the node for determining the beginning of the exchange format with the selection of command words and data words 227 is shown in Fig.29, 29a.

The algorithm of the receiver decoder 228 is shown in Fig.30, 30a 30b

The coding node (CODER OU) 215 generates a code sequence of one CIE word based on its features.

The algorithm of the encoding node (CODER OU) 215 is shown in Fig.31, 31A.

The decoding node (DECODER OU) 216 provides decoding of the serial signal in accordance with GOST R520.2003 with word-by-word feature extraction.

The operation algorithm of the decoding node (DECODER OU) 216 is shown in Figs. 32, 32a, 32b.

The error detection node (DETECTOR) 217 provides protection against continuous output of data for 800 μs in the CIE.

The operation algorithm of the DETECTOR 217 node is shown in Fig.33.

The controller 218 controls the operation of the OU under the influence of received words from the MCO.

The algorithm of the controller 218 is shown in Fig.34, 34a, 34b, 34c, 34d, 34d, 34e, 34g.

Functional diagram of the system controller VM 17 is shown in Fig.2.

The system controller VM 17 provides control of the movement of the upper-level equipment and participates in the exchange of service and telemetry information with YYB via the LVDS interface (Y_BM_REC, Y_BM_TRAN, Y_TLMRAM);

The VM system controller 17 consists of a start diagram node 106, a PCI interface node 107, a PCI memory node 108, a node for receiving information from LVDS Y_BM_REC 109, a node for transmitting to the LVDS bus Y_BM_TRAN 111, a memory node for the telemetry channel Y_TLMRAM 110, PLL112, the first element AND 113, the second, the AND element 114, the first group of multiplexers 115, the second group of multiplexers 116, the OR element 117.

Functional diagram of the node receiving information from the LVDS 109 is shown in Fig.3.

The node for receiving information from the LVDS 109 provides decoding of the serial LVDS code into a parallel code.

The node for receiving information from LVDS 109 consists of the first node REC0 138, the second node REC1 139, the third node REC2 140 and the node generating control signals Y_FYS 141.

The algorithm of the node generating control signals Y_FYS 141 of the receiver VM is shown in Fig.35.

A functional diagram of the node for transmitting information to the LVDS bus 111 is shown in Fig.4.

The node for transmitting information to the LVDS bus 111 provides the conversion of a parallel code into a serial code.

The node for transmitting information to the LVDS bus 111 consists of the first node TRAN0 144, the second node TRAN1 145, the third node TRAN2 146 and the node for generating control signals of the transmitter Y_FYS_BM_ TRAN 147.

The algorithm of the node generating control signals of the transmitter Y_FYS_ BM_TRAN 147 is shown in Fig.36.

The memory node telemetry channel Y_TLMRAM 110 provides data storage for telemetry.

The algorithm of the memory node telemetry channel Y_TLMRAM 110 is shown in Fig.37, 37a, 37b.

Information sources

1. Patent No. 2264648, Russian Federation, MKI G06F 11/20, 2005 (analogue).

2. Patent No. 2010315, RF, MKI G06F 11/18, 1994 (prototype).

3. FPGA A3PE1500 - FG484I YUShKR.430103.586 D16.

4. FPGA A3PE1500 - PQ208I YUShKR.430103.585 D16.

5. DDR, JEDEC JESD79C standard.

6. DDRII, JEDEC JESD79-2F standard.

6. Ethernet, IEEE 802.3 standard.

Claims (12)

1. Computing system with a cold standby (CHR), containing two identical channels (VM1 and VM2), each of which consists of a processor, memory, the first input-output device, characterized in that the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth generators, second processor, second RAM, first PROM, second PROM, system controller, second I/O device, third I/O device, fourth I/O device, fifth device I / O, power reset node (reset power), first galvanic isolation node, second galvanic isolation node, secondary power supply, the outputs of which produce 1.5 V, 1.8 V and 3.3 V, an additional device is introduced into the system recovery management (YYB), containing the YYB system controller, the node of the sensor of damaging factors (hereinafter referred to as the PF sensor), external MRAM memory, the reserve management node (YYR), the movement node, the time node (TIME), the tele meters (TMK), a power reset node (reset power), a sixth input-output device, a generator, a filter and a power node, the outputs of which produce 1.5 V and 3.3 V, and the input is connected to the filter output and to the first inputs channels ВМ1 and ВМ2, the first groups of outputs of which are connected to the first and second groups of inputs of the YYB system controller, the first and second groups of outputs of which are connected to the groups of inputs of the external memory MRAM and the telemetry node, respectively, the group of inputs-outputs of the external memory MRAM and the group of outputs of the telemetry node TMK is connected to the input-output group and the third group of inputs of the YYB system controller, the second and first control groups of outputs of which are connected to the first groups of inputs of the PF sensor and reserve control nodes, the first groups of outputs of which are connected to the fourth and fifth groups of inputs of the YYB system controller, the third the output group of which is connected to the first input of the motion node and the first group of inputs of the time node TIME, the output group of which is connected line with the sixth group of inputs of the YYB system controller, the fourth and fifth groups of outputs of which are connected to the first groups of inputs of the first and second channels BM1 and BM2, the first outputs of which are interconnected, with the input of the sixth input-output device YYB, with the outputs of the third input-output devices - output and are the first output of the VSHR, the first and second groups of outputs of which are connected to the first and second groups of outputs of the motion nodes and the PF sensor, respectively, and the first and second groups of inputs are connected to the group of inputs of the motion node and the second group of inputs of the PF sensor node, the first output of which is the second output of the VSHR, the first input of which is connected to the first input of the time node TIME, the third and second groups of inputs of which are connected to the second groups of outputs of the movement and reserve control nodes, the first output and input of which are connected to the input and second output of the PF sensor node, and the first and the second inputs of the YYB system controller are connected to the outputs of the sixth I/O device ode and generator, the third output of the VCXR in each channel is connected to the outputs of the second input-output devices, the inputs-outputs of which are connected to the PCI bus, which is connected to the first inputs-outputs of the first and second processors, with the inputs-outputs of the third, fourth and fifth devices input-output, with the inputs-outputs of the VM system controllers and with the outputs of 33 MHz generators, and the second and third groups of inputs-outputs of the first processors are connected to the inputs-outputs of the first RAM and the first PROM, and the groups of outputs of the first processors are connected to the first groups of inputs of the second processors, the second and third input-output groups of which are connected to the input-output groups of the second RAM and to the input-output groups of the second EPROM, the second input-output groups of the first EPROM are connected to the first input-output groups of the first input-output devices, the second input-output groups - outputs of which are connected to the fourth groups of inputs-outputs of the first processors, the first groups of inputs of which are connected to the first groups outputs of the VM system controllers, the second groups of outputs of which are connected to the second groups of inputs of the second processors, the group of outputs of which is connected to the second groups of inputs of the first processors, the first, second and third inputs of which are connected to the outputs of the generators of the first 125 MHz, the second 80 MHz and the third 24 MHz respectively, and the fourth inputs of which are connected to the outputs of the seventh 25 MHz generators and the first inputs of the first input-output devices, the second inputs of which are connected to each other and to the second input of the VCXR, and the third inputs are connected to the first outputs of the first processors, the fifth inputs of which are connected to the first outputs of the VM system controllers, the second outputs of which are connected to the first inputs of the second processors, the second and third inputs of which are connected to the outputs of the fifth 24 MHz generators and the sixth 25 MHz generators, the first groups of inputs of the VM system controllers are connected to the groups of outputs of the second galvanic isolation nodes, and the third system control output groups VM ollers are connected to the groups of inputs of the first galvanic isolation nodes, and the first and second inputs of the VM system controllers are connected to the power reset nodes and the fourth 24 MHz generators, and the outputs of the eighth 12 MHz generators are connected to the first inputs of the second, third, fourth and fifth input devices -output, moreover, the outputs of the fourth and fifth input-output devices of the BM1 channel are connected to the outputs of the fourth and fifth input-output devices of the BM2 channel and are the fourth and fifth outputs of the VSKhR system, and the third group of outputs of the PF sensor is connected to the seventh group of inputs of the YYB system controller, the clock and reset outputs of which are connected to the clock and reset inputs of the PF sensor nodes, reserve control, movement, time (TIME) and telemetry (TMK), and the second and third outputs YYR are connected to the second inputs of the secondary power sources in each channel BM1 and BM2, the third group of outputs YYR is connected to the second group of inputs of the TMK node, the second group of outputs the third group of outputs of the VSHR, the third group of inputs of which is connected to the eighth group of inputs of the YYB system controller, the third input of which is connected to the output of the power reset unit, and the sixth group of outputs is connected to the group of inputs of the sixth input-output device, and the VM controller is connected to the second inputs of the second, third, fourth and fifth input-output devices. 2. A computer system with a cold standby according to claim 1, characterized in that the VM system controller in each channel contains a start diagram node (START), a PCI bus interface node (Y_PCI), a PCI memory node (Y_RAM2), an information receiving node with LVDS (Y_MB_REC), telemetry channel memory node (Y_TLMRAM), LVDS information transfer node (Y_BM_TRAN), frequency generation node (PLL), first AND element, second AND element, first group of multiplexers, second group of multiplexers, group of OR elements, group the outputs of which are connected in each channel to the first and byte by byte to the second groups of inputs of the first group of multiplexers, the output group of which is connected to the input group of the Y_PCI node, the first group of outputs of which is connected to the first groups of inputs of the Y_RAM2 node and the Y_TLMRAM node, the first group of outputs of which is connected to the first group of inputs of the group of OR elements, the second group of inputs of which is connected to the first group of outputs of the node Y_RAM2, and the first group of outputs Y_BM_TRAN is the third group of outputs of the VM system controller, the BMCLK_O signal of which is connected to the first input of the Y_BM_TRAN node and is the first PLL output, the second output of which is connected to the first input of the Y_MB_REC node, the first, second, third and fourth groups of outputs of which are connected to the second, third, fourth and the fifth groups of inputs of the Y_TLMRAM node, the second, third and fourth groups of outputs of which are connected to the first, second and third groups of inputs of the Y_BM_TRAN node, the fourth group of inputs of which is connected to the fifth group of outputs of the Y_MB_REC node, the sixth group of outputs of which is connected to the fifth group of inputs of the Y_BM_TRAN node , the seventh group of outputs Y_MB_REC is connected to the second and sixth groups of inputs of the nodes Y_RAM2, Y_TLMRAM and Y_BM_TRAN, respectively, and the eighth group of outputs is connected to the first and seventh groups of inputs of the nodes START, Y_TLMRAM and Y_BM_TRAN, respectively, and is the first and second groups of outputs of the VM system controller, which also connected with the ninth, tenth and by the eleventh group of outputs of the Y_MB_REC node, the first input of the VM system controller is connected to the first inputs of the START, Y_RAM2, Y_TLMRAM and Y_BM_TRAN nodes, and the output group of the START node is connected to the eighth group of inputs of the Y_BM_TRAN node, the fourth signal of which is connected to the first PLL inputs and the first AND element, the fifth signal of which is connected to the first input of the Y_PCI node, the sixth signal of which is connected to the direct input of the second element AND and to the second input of the Y_MB_REC node, the third input of which is connected to the second inputs of the START, Y_RAM2, Y_TLMRAM nodes, to the third input of the Y_BM_TRAN node and is the second input VM system controller, the input group of which is connected to the input group of the Y_MB_REC node and to the second input of the PLL, the third output of which is connected to the second input of the first AND element, the output of which is connected to the inverse input of the second AND element, the output of which is connected to the fourth input of the Y_MB_REC node, and the second group of outputs of the Y_PCI node is connected to the first group of inputs and byte by byte - with the second group of inputs of the second group of multiplexers, the group of outputs of which is connected to the third group of inputs of the Y_RAM2 node and the eighth group of inputs of the Y_TLMRAM node, the fifth group of outputs of which is connected to the ninth group of inputs of the Y_BM_TRAN node, the third input of the Y_TLMRAM node is connected to the third input of the Y_RAM2 node and the output node Y_PCI, the input-output group of which is connected to the fourth inputs of the Y_TLMRAM and Y_RAM2 nodes and is a group of inputs-outputs of the VM system controller, the fifth inputs of the Y_TLMRAM and Y_RAM2 nodes are connected to the case, the sixth input of the Y_TLMRAM node is connected to the power supply, the output of the Y_TLMRAM node is connected to control inputs of the first and second groups of multiplexers, and the seventh, eighth and ninth signals of the output group of the START node are the first, second and third (MKORST) outputs of the VM system controller. 3. The computer system with a cold standby according to claim 1, characterized in that the Y_MB_REC node in each channel contains the first REC0 node, the second REC1 node, the third REC2 node, the control signal generation node (Y_FYS), the first group of inverters, the second group of inverters, the inverse group of outputs of which is connected to the first group of inputs of the Y_FYS node, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh groups of outputs of which are connected to the first, second, third, fourth, fifth, sixth, the seventh, eighth, ninth, tenth and eleventh groups of outputs of the Y_MB_REC node, the first, second and third signals of the input group of which are connected to the first inputs of the nodes REC0, REC1, REC2, respectively, the second inputs of which are interconnected, with the first input of the Y_FYS node and are the first the input of the Y_MB_REC node, the second input of which is connected to the inverse input of the Y_FYS node, the second group of inputs of which is connected to the output group of the REC0 node and to the group of inputs ne of the first group of inverters, the inverse group of outputs of which is connected to the third group of inputs of the Y_FYS node, the fourth group of inputs of which is connected to the group of outputs of the node REC1 and to the group of inputs of the second group of inverters, the fifth group of inputs of the node Y_FYS is connected to the group of outputs of the node REC2, the third input of which is connected with the second input of the Y_FYS node, with the third inputs of the REC0, REC1 nodes and is the third input of the Y_MB_REC node, the fourth input of which is connected to the third input of the Y_FYS node and to the fourth inputs of the REC0, REC1 and REC2 nodes. 4. The computer system with a cold standby according to claim 1, characterized in that the Y_BM_TRAN node in each channel contains the first TRAN 0 node, the second TRAN 1 node, the third TRAN 2 node, the transmitter control signal generation node (Y_FYS_BM_TRAN), the Y_BM_TRAN output group is connected with the outputs of the TRAN 0, TRAN 1, TRAN 2 nodes, the input groups of which are connected to the first, second and third output groups of the Y_FYS_BM_TRAN node, the first input group of which is connected to the output group of the first TRAN 0 node, the first input of which is connected to the first inputs of the TRAN 1 nodes , TRAN 2 and is the first input of the Y_BM_TRAN node, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth groups of inputs of which are connected to the second, third, fourth, fifth, sixth, seventh, eighth, ninth and tenth groups inputs of the node Y_FYS_BM_TRAN, and the first signal of the eighth group of inputs of which is connected to the second inputs of the nodes TRAN 0, TRAN 1, TRAN 2, the third inputs of which are interconnected and are tr the third input of the Y_MB_TRAN node, the second input of which is connected to the fourth inputs of the TRAN 0, TRAN 1, TRAN 2 nodes, and the group of outputs of the TRAN 1 node is connected to the eleventh group of inputs of the Y_FYS_BM_TRAN node. 5. Computing system with a cold standby according to claim 1, characterized in that the YYB system controller contains a data receiving node (YYB_REC), an external memory management node (Y_MRAM), a data transmission node (YYB_TRAN), a Y_MKO node, a first PLL, a second PLL , the first multiplexer, the second multiplexer, the first trigger, the second trigger, the first AND element, the second AND element, the third AND element, the fourth AND element, the fifth AND element, the 3AND-OR element, the first OR element, the second OR element, the first group of multiplexers, the second multiplexer group, the output group of which is the fifth output group of the YYB system controller, and the MBCLK2 signal of which is connected to the output of the second multiplexer, the first input of which is connected to the housing, and the second input is connected to the first input of the first multiplexer and the first output of the first PLL, the inverse output of which connected to the first input of the Y_MKO node, whose output group Upr2_MKO and the TLV signal are the first control group of outputs of the YYB system controller, the second control group of outputs of which consists of the first and third groups of outputs of the YYB_REC node, from the first group of outputs of the Y_MKO node and from the output of the second trigger, the information input of which is connected to the first input of the third AND element and the output of the first AND element, the input of which is the first signal of the fifth group inputs of the YYB system controller, the second and third signals of which are connected to the first and second inputs of the fourth element AND, the output of which is connected to the first input of the Y_MRAM node, the input-output group of which is the input-output group of the YYB system controller, the first group of outputs of which is connected to the first and the second group of outputs of the Y_MRAM node, the third group of outputs of which is connected to the second group of inputs of the Y_MKO node, the second group of outputs of which is connected to the second group of outputs of the YYB system controller, the third group of outputs of which is connected to the first group of inputs of the YYB_TRAN node, with the third input of the YYBREC node, with the third group of outputs of the Y_MKO node, with about the second input of the Y_MRAM node, the fourth group of outputs of the YYB system controller is connected to the output group of the first group of multiplexers, and the MBCLK1 signal of which is connected to the output of the first multiplexer, the second input of which is connected to the housing, and the fourth signal of the fifth group of inputs of the YYB system controller is connected to the inverse the input of the second AND element, with the first inputs of the 3I-OR element and the first OR element, with the control inputs of the first multiplexer and the first group of multiplexers, the first group of inputs of which is connected to the first group of inputs of the second group of multiplexers and the first group of outputs of the YYB_TRAN node, the second group of outputs of which connected to the first group of inputs of the Y_MKO node, the third, fourth, fifth, sixth, seventh, eighth, ninth groups of inputs of which are connected to the fourth, fifth, sixth, seventh, eighth, ninth, tenth groups of outputs of the YYB_REC node, the first output of which is connected to the third input of the fourth element AND and is the first si the eleventh group of outputs, which is connected to the second group of inputs of the YYB_TRAN node and the tenth group of inputs of the Y_MKO node, the fourth group of outputs of which is the sixth group of outputs of the YYB system controller, the second group of outputs of which is connected to the second group of outputs of the Y_MKO node, with the twelfth and second groups of outputs node YYB_REC, the second and third groups of inputs of which are connected to the first and second groups of inputs of the YYB system controller, the third group of inputs of which is connected to the third group of inputs of the node YYB_TRAN, the fourth group of inputs of which is connected to the eleventh group of inputs of the node Y_MKO and is the fifth group of inputs of the system controller YYB, the fourth group of inputs of which is connected to the twelfth group of inputs of the node Y_MKO, the fifth group of outputs of which is connected to the fifth group of inputs of the node YYB_TRAN, the sixth and seventh groups of inputs of which are connected to the sixth and seventh groups of outputs of the node Y_MKO, the thirteenth group of inputs of which is connected to the eighth group of inputs of the YYB_TRAN node and is the sixth group of inputs of the YYB system controller, the first input of which is connected to the second input of the Y_MKO node, the first and second outputs of which are connected to the first and second inputs of the fifth element AND, the output of which is connected to the third input of the Y_MKO node and the first input node YYB_TRAN, the ninth and tenth groups of inputs of which are connected to the fifth and fourth groups of outputs of the node YYB_REC, the first input of which is connected to the first output of the second PLL and is the first signal of the second group of outputs of the YYB system controller, the second signal of which is connected to the second output of the second PLL and inverse input of the first AND element, moreover, the second input of the YYB_REC node is connected to the output of the third AND element, the second input of which is connected to the inverse input of the second trigger, the input of the first PLL, the output of the first trigger and is a reset signal of the YYB system controller, nodes Y_MRAM, YYB_TRAN and Y_MKO, clock whose inputs are connected to the clock input of the second trigger ger, YYB_REC node and the output of the first PLL and is the clock output of the YYB system controller, and the control input of the second multiplexer is connected to the control inputs of the second group of multiplexers, with the direct input of the second AND element, the second input of the first OR element and is the fifth signal of the fifth group of inputs of the system controller YYB, signals BMCLK1 and BMCLK2 of the first and second groups of inputs of which are connected to the second and third inputs of the 3AND-OR element, the output of which is connected to the input of the second PLL, and the fourth, fifth and sixth inputs of which are connected to the output of the second element AND, the inverse output of the first element OR and housing, respectively, wherein the second and third inputs of the YYB system controller are connected to the clock and inverse reset inputs of the first trigger, the information input of which is connected to power, and the sixth and seventh signals of the fifth group of inputs of the YYB system controller are connected to the first and second inputs of the second element OR , the output of which is connected to about the second input of the YYB_TRAN node, the third input of which is connected to the first output of the first PLL, and the second groups of inputs of the first and second groups of multiplexers are the constant "7", and the first group of inputs of the YYB_REC node is connected to the fifth group of inputs of the YYB system controller, the seventh and eighth groups whose inputs are connected to the fourteenth and fifteenth groups of inputs of the Y_MKO node. 6. Computing system with a cold standby according to claim 1, characterized in that the reserve management node (YYR) contains the reserve switching node (ASR), the state machine (MS), the first node for determining the validity (GOOD1), the second node for determining the validity (GOOD2 ) and a response mode determination node (YORR), the first and second groups of outputs of which are the first group of outputs of the node YYR, which also consists of the first group of outputs of the ASR node, from the first groups of outputs and the first outputs of the nodes GOOD1 and GOOD2, the first groups of inputs of which are connected with the second group of outputs of the ASR node, the first output of which and the second signal of the MS output group, which is also connected to the first input of the ASR node, are the second group of outputs of the YYR node, the third and fourth groups of outputs of the ASR node are connected to the first and second groups of inputs of the YORR node, the third group of outputs of which is connected to the third group of outputs YYR, the output of which is connected to the first signal of the MS output group, the input of which is connected to the input of node YYR, the first the first input group of which consists of the UPR_MKO group, which is connected to the first input group of the ASR node, to the second input groups of the GOOD1 and GOOD2 nodes and to the third input group of the YORR node, and from the UPR_REC group, which is connected to the third input groups of the GOOD1 and GOOD2 nodes, with the fourth, fifth and sixth groups of inputs of the YORR node, the seventh group of inputs of which is connected to the second group of outputs of the GOOD1 node, the clock and reset inputs of which are connected to the clock and reset inputs of the ASR, GOOD2, YORR, MS nodes and are the clock and reset inputs of the YYR node , moreover, the output of the YORR node is connected to the second input of the ASR node, the second and third groups of outputs of the GOOD2 node are connected to the eighth and ninth groups of inputs of the YORR node, and the second and third outputs of the ASR 187 node are connected to the second and third outputs of the YYR node. 7. Computing system with a cold standby according to claim 1, characterized in that the movement node (Y_D) contains the first pulse analyzer (A_RCIMP1), the second pulse analyzer (A_RCIMP2), the first pulse generator (G_TRIMP1), the second pulse generator (G_TRIMP2), the output of which is the second signal of the first group of outputs of the node Y_D, and the first signal of which is connected to the output of the first generator G_TRIMP1, the inverse enabling input of which is connected to the inverse enabling input of the second generator G_TRIMP2 and is the input of the node Y_D, the second group of outputs of which is connected to the outputs of the first and second pulse analyzers G_RCIMP1, G_RCIMP2, the information inputs of which are the first group of inputs of the Y_D node, the clock and reset inputs of which are connected to the clock and reset inputs A_RCIMP1, A_RCIMP2, G_TRIMP1, G_TRIMP2. 8. The cold standby computing system according to claim 1, characterized in that the external memory management node (Y_MRAM) contains encoder_L (K_L), encoder_H (K_H), control node (Y_Y), MRAM timing diagramming node (Y_DMRAM), decoder_L (DK_L), decoder_H (DK_H), whose output group is combined with the output group DK_L and is the first group of inputs of node Y_Y, the first group of outputs of which is connected to the third group of outputs Y_MRAM, the first group of outputs of which is the first, second and third outputs of nodes Y_Y and Y_DMRAM and the first group of outputs of the node Y_DMRAM, which is also connected to the second group of inputs of the node Y_Y, the second group of outputs of which is connected to the first group of inputs of the node Υ_DMRAM, the second group of outputs of which is connected to the groups of inputs DK_L, DK_H and the third group of inputs of the node Y_Y, the fourth group of inputs of which is connected to the second group of inputs of the Y_DMRAM node and is the first group of inputs of the Y_MRAM node, the second group of inputs of which is connected to g groups of inputs of the nodes K_L, K_H and the fifth group of inputs of the node Υ_Υ, the fourth output of which is connected to the first input of the Y_DMRAM node, the fourth output of which is connected to the first input of the Υ_Υ node, the second and third inputs of which are connected to the first and second inputs of the Y_MRAM node, respectively, the clock input which is connected to the clock input of the Y_DMRAM node, the second input of which is connected to "power", and the reset input of which is connected to the reset input of the Y_Y node and is the reset input of the Y_MRAM node, the bidirectional input-output of which is the bidirectional input-output of the Y_DMRAM node, and the sixth group node inputs Y_Y is connected to groups of outputs K_L, K_H. 9. Computing system with a cold standby according to claim 1, characterized in that the YYB receiver node (YYB_REC) contains the first data receiver node (MB_REC0), the second data receiver node (MB_REC1), the third data receiver node (MB_REC2), the control generation node signals (U_FUS), the first group of inverters and the second group of inverters, the output group of which is connected to the first group of inputs of the control signal generation node, the first to twelfth output groups of which are the first to twelfth output groups of the YYB_REC receiver node, the first group of inputs of which is connected to the second group of inputs of the node for generating control signals, the thirteenth group of outputs of which is connected to the information inputs of the first (MB_REC0), second (MB_REC1) and third (MB_REC2) data receiving nodes, the groups of the first outputs of which are connected to the third, fourth and fifth groups of inputs of the node for generating control signals, and the second groups of outputs are the seventh group of outputs of the receiver node Y YB_REC, respectively, the sixth and seventh groups of inputs of the control signal generating node are the second and third groups of inputs of the YYB_REC receiver node, the first input of which is connected to the first inputs of the first, second and third data receiving nodes, the clock inputs of which are interconnected, with the clock input of the generating node control signals and are the clock input of the receiver node YYB_REC, the reset input of which is connected to the reset inputs of the first MB_REC0, the second MB_REC1 and the third MB_REC2 data receiving nodes and the reset input of the control signal generation node, the eighth input group of which is connected to the output group of the first inverter group, the input group which is connected to the group of outputs of the first MB_REC0 of the data receiving node, and the group of inputs of the second group of inverters is connected to the group of outputs of the second MB_REC1 of the data receiving node, the first input of the node for generating control signals is the third input of the receiver node YYB_REC, the second groups of outputs Receive data tags MR_REC0, MR_REC1, MR_REC2 are the seventh group of outputs of the YYB_REC receiver. 10. The computer system with a cold standby according to claim 1, characterized in that the YYB transmitter node (YYB_TRAN) contains the first data transmission node (TRAN0), the second data transmission node (TRAN1), the third data transmission node (TRAN2), the control generation node transmitter signals (Y_FYS_TRAN), the first, second and third groups of outputs of which are connected to the information groups of inputs of the first TRAN0, second TRAN1 and third TRAN2 data transmission nodes, the outputs of which are the group of outputs of the YYB_TRAN node, the groups of inputs from the first to the tenth of which are connected to the groups of inputs from the first to the tenth node Y_FYS_TRAN, the eleventh and twelfth groups of inputs of which are connected to the groups of outputs of the first TRAN0 and second TRAN1 data transmission nodes, the enabling inputs of which are interconnected, with the enabling input of the third TRAN2 data transmission node and are the second input of the YYB_TRAN node, the third input which is connected to the TCLK of the first TRAN0, the second TRAN1 and the third TRAN2 data transmission nodes x, the clock and reset inputs of which are connected to the clock and reset inputs of the YYB_TRAN node, the first input of which is connected to the first input of the Y_FYS_TRAN node. 11. The computer system with a cold standby according to claim 1, characterized in that the Y_MKO node contains a subaddress data generation node (Y_FDP), a terminal device control node (Y_YOU), a data reception node (REC_OU), an encoding node (CODER), a decoding node (DECODER), an error detection node (DETECTOR) and a controller, the first group of outputs of which is the second control group of outputs of the YYB system controller and is connected to the first and second inputs of the CODER node and to the first groups of inputs of the Y_YOU and CODER nodes, the first group of outputs of which is connected to the second group of inputs of the Y_YOU node, the first group of outputs of which is connected to the first groups of inputs of the data receiving node REC_OU, the error detection node DETECTOR and the controller, and the second group of outputs is the fourth group of outputs of the MKO node, the first input of which is connected to the first input of the DECODER node, the first group whose outputs are connected to the second group of inputs of the REC_OU node, the first, second and third groups of outputs of which are connected connected with the second, third and fourth groups of inputs of the controller, the second, third, fourth groups of outputs and the inverted output of which are the first control group of outputs Upr2_contr of the YYB system controller, which is also connected to the first group of inputs of the Y_FDP node, the first group of outputs of which is connected to the fifth group controller inputs, the first output of which is connected to the first input of the REC_OU node, the fourth group of outputs of which is connected to the sixth group of controller inputs and the third group of inputs of the Y_YOU node, the fourth group of inputs of which is connected to the third group of inputs of the REC_OU node and the second group of outputs of the DECODER node, clock and the reset inputs of which are connected to the clock and reset inputs of the Y_FDP, Y_YOU, REC_OU, CODER, DECODER, DETECTOR nodes of the controller and are the clock and reset inputs of the MKO node, the second, third, fourth and tenth groups of inputs of which are connected to the second, third, fourth and the fifth group of inputs of the Y_FDP node, respectively, w The second and third groups of outputs of which are connected to the seventh and eighth groups of inputs of the controller, the second and third outputs of which are connected to the first and second inputs of the DETECTOR node, the output of which is connected to the first input of the controller, the second input of which is connected to the “power supply”, of the group of inputs to the ninth the thirteenth group of inputs of the controller are connected to the "case", and the fourteenth group of inputs is connected to the second and third groups of outputs of the CODER node, the third input of which is connected to the "case", and the fourteenth group of inputs of the MKO node is connected to the inverse groups of inputs of the nodes Y_YOU, REC_OU, controller and is the seventh group of inputs of the YYB system controller, and the fifth group of controller outputs is connected to the fifth group of inputs of the Y_YOU node, the third, fourth, fifth and sixth groups of outputs of which are the groups of outputs VM6,7MOD(2:0), MB_TEST(2:0), Upr_MKO, FSH1,2VM6,7REN of the MKO node, the fifth group of inputs of which is connected to the sixth group by the input of the Y_YOU node, and the first, sixth, seventh , the eighth, ninth, twelfth, thirteenth and fourteenth groups of inputs of the MKO node are connected to the sixth, seventh, eighth, ninth, tenth, eleventh, twelfth and thirteenth groups of inputs of the Y_FDP 212 node, and the seventh group of outputs of the Y_YOU node is connected to the second group of outputs of the Y_MKO node. 12. The computer system with a cold standby according to claim 1, characterized in that the receiver node REC_OU contains a node for determining the beginning of the exchange format with the selection of command words and data words (Y_ONFO) and a decoder, the first to seventh groups of outputs of which are the fourth group of outputs of the node REC_OU, which also includes signals connected to the decoder output and to the first group of outputs of the Y_ONFO node, the second group of outputs of which is connected to the first group of decoder inputs and is the first group of outputs of the REC_OU node, the second group of outputs of which is connected to the third group of outputs of the Y_ONFO node , the fourth group of outputs of which is connected to the second group of inputs of the decoder and is the third group of outputs of the REC_OU node, the first, second and third groups of inputs of which are connected to the first, second and third groups of inputs of the Y_ONFO node, the inverse group of inputs of which is connected to the inverse group of inputs of the REC_OU node , the first input of which is connected to the input of the Y_ONFO node, the clock and reset inputs of which are connected to the clock and reset inputs of the decoder and are the clock and reset inputs of the REC_OU node, with the first and second inputs of the decoder connected to the “case”.

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