RU2763903C1 - Group structure device for detecting the boundaries of a range of unit bits - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: device contains: M bits D0, …, D(M-l) of a group of input data from an N-bit binary number, output (n+1) and n-bit buses of the QD range width, the numbers of the lowest single digit QL and the number of single bits QU, respectively, the output flag of the single bits QF1, start-stop triggers TSS and single bits TU, two elements AND, group counter, element OR, priority encoders of the highest and lowest single digits, unit counting module, output registers of the number of the highest RGM single bit and RGL low single bit numbers, SMS difference adders and SMU single bits, the INC incrementor, the output register of the number of single bits, the external inputs for stopping STOP and starting START, clock signals WITH and asynchronous setting to the zero state of CLR, the internal flag of single bits in the FU group, the internal m-bit buses of the numbers of the highest and lowest single bits in the M-bit group, the internal (n-m) and (m+1) bit bus numbers of the BD group and the number of single bits in the AU group, respectively.

EFFECT: ability to identify the boundaries of the range of single bits, estimate the width of the range.

1 cl, 3 dwg

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to build automation tools and functional units of control systems, as well as to process the results of physical experiments.

PRIOR ART

A device is known for determining the number of ones (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, H03K 21/00, declared 04/11/2011, published 03/27/2012, Bull. No. 9), containing a controlled inversion unit, consisting from n-elements "EXCLUSIVE OR" (n - the number of digits of the input number), OR elements and modules consisting of the EXCLUSIVE OR element and the AND element, which are combined into groups consisting of tiers and combined into k-cascades (k =] log ₂ n[), so that each i-th cascade contains g(i)=n/2 ⁱ groups (i=1, …, k), each group of the i-th cascade is divided into j tiers (j=l, i), while the first tier of each group of the i-th cascade contains i modules, and each j-th tier of each group of the i-th cascade (j=2, ..., i,) contains (ij) modules and the "OR" element.

The disadvantage of this device is to determine only the total number of ones (zeros) in a binary number, and not to identify the range of single bits.

The cascade connection of priority encoders is known (John F. Wakerley. Designing digital devices. / Translated from English. Volume 1. M .: Postmarket, 2002, - 544 p., Fig. 5.51, p. 440-445) in which priority bits in the groups of the input number, between the groups the output signal of the work permission is sequentially transmitted, and the outputs of the group encoders are combined by a group of OR-NOT elements.

The disadvantage of this device is the linear growth of hardware with an increase in the capacity of the input number.

A device for detecting a range of single bits is known (RU No. 2717631 C1, IPC G06F 7/74, declared 11/07/2019, published 03/24/2020, Bull. No. 9), containing N bits of the input bus D - D1, D2, ..., DN, N bits of the output bus Q - Q1, Q2, ..., QN, the first group of (N-2) elements OR 1 ₁ , 1 ₂ , 1 _(n-2) , the second group of (N-2) elements OR 2 ₁ , 2 ₂ , 2 _(n-2) and a group of (N-2) elements AND 3 ₁ , 3 ₂ , …, 3 _(n-2) . Moreover, the first group of elements OR 1 ₁ , 1 ₂ , ..., 1 _(n-2) , united in a chain, forms an ordered group of consecutive units in the lower digits, the second group of elements OR 2 ₁ , 2 ₂ , ..., 2 _{(n- 2)} forms an ordered group of units in high-order digits, and in the group of elements AND 3 ₁ , 3 ₂ , ..., 3 _(n-2) the verification of unit values in the same digits of the ordered groups of units is carried out.

The disadvantage of this device is only the identification of the least significant and most significant bits of the range of single bits for a parallel incoming N-bit input binary number and filling the range with single bits, without calculating the bit numbers.

The closest device for the same purpose to the claimed invention in terms of a set of features is, taken as a prototype, a device for detecting the boundaries of the range of single bits (RU No. 2717934 C1, IPC G06F 7/74, H03K 21/00 declared 12/19/2019, published 03/27/2020 , Bull. No. 9), containing an N-bit input bus D, an output bus QR of a low-order number and an output bus QL of a high-order number containing M bits each, where M=]log ₂ (N+1)[(larger integer), group of (N-1) elements OR 1 ₁ , 1 ₂ , …, 1 _(N-1) , a group of (N-1) elements OR-NOT 2 ₁ , 2 ₂ , …, 2 _(n-1) , the first 3 ₁ and second 3 ₂ count units of lower ordered units, as well as the inner shift right line SR and the left shift inner line SL, which each contain N bits.

The disadvantage of this device is the definition of boundaries only for parallel incoming N-bit input binary number and the lack of funds for counting single bits in the range.

OBJECT OF THE INVENTION

The objective of the invention is to identify the number of the left (highest) unit bit and the number of the right (lowest) unit bit in the input data, estimate the range width and determine the number (sum) of unit bits in the range.

When processing the results of physical experiments, the device is designed to identify the range of events and determine the number of events.

The technical result of the invention is the expansion of the arsenal of tools for the same purpose, in terms of the possibility of detecting the boundaries of the range of single bits and estimating the width of the range, as well as fixing the number of the left (highest) single bit and the number of the right (lower) single bit in the input data, the range width code and the number of 1 bits in the range.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that the group structure device for detecting the boundaries of the range of single bits contains M bits D0, ..., D(M-1) of the input data group from the N bit binary number, consisting of L sets of M bits in the group , where N=L*M, the output n bit bus 20 of the number of the most significant bit QM, where n=log ₂ N and N=2 ⁿ , the output (n+1) bit bus 21 of the range width QD, the output n bit bus 22 numbers LSB QL, output (n+1) bit line 23 number of 1 bits QU, output flag 24 1 bits QF1, first start-stop flip-flop 1 TSS, second flip-flop 2 1-bits TU, first element AND 3, second element AND 4 , group counter 5, OR element 6, priority encoder of the most significant one bit 7, priority encoder of the least significant one bit 8, unit counting module 9, first output register 10 of the number of the most significant one bit RGM, second output register 11 of the number of the least its single bit RGL, the first adder 12 SMS difference, the incrementer INC 13, the second adder 14 single bits SMU, the third output register of the number of single bits 15, and also contains an external stop input 16 STOP, an external input 17 start work START, an external clock input 18 signals C, external input 19 of asynchronous setting to zero state CLR, internal flag of single bits in the group FU, internal m bit bus of the number of the most significant single bit UM in the M-bit group, where m=log ₂ M, M=2 ^m , internal m the bit line of the least significant one bit number UL in the M-bit group, the internal (nm) bit line of the group number BD, the internal (m+1) bit line of the number of ones bits in the M-bit group AU,

wherein the external clock input C 18 and the asynchronous reset external input CLR 19 are connected to the corresponding clock inputs C and the asynchronous reset CLR inputs of the first start-stop trigger 1 TSS, the second trigger 2 1-bits TU, the group counter 5 , the first output register 10 of the number of the highest single bit RGM, the second output register 11 of the number of the least significant single bit RGL and the third output register of the number of single bits 15,

the external input 17 of the start of work START is connected to the input S of the synchronous installation in a single state of the first trigger 1 start-stop TSS,

the external input 16 of the stop STOP is connected to the input R of the synchronous set to the zero state of the trigger TSS start-stop 1,

moreover, M bits D0, ..., D(M-1) of the input data group are connected to the corresponding inputs of the OR element 6, the priority encoder of the highest unit digit 7, the priority encoder of the least significant unit digit 8 and the unit count module 9,

while the output of the OR element 6 is an internal flag of single bits FU and is connected to the second inputs of the first 3 and second 4 elements AND and is connected to the input S of the synchronous setting to the single state of the second trigger 2 single bits TU, the inverse output of which is connected to the first input of the second element And 4, the output of which is connected to the operation enable input CE of the second output register 11 of the number of the least significant single bit RGL, and the direct output of the second trigger 2 single bits TU is connected to the first input of the increase of the incrementer INC 13 and is the output flag of single bits QF1,

moreover, the output of the trigger 1 start-stop TSS is connected to the work enable input CE of the group counter 5, to the work enable input CE of the third output register 15 and to the first input of the first element AND 3, the output of which is connected to the work enable input CE of the first output register 10 of the senior number single bit RGM,

in addition, the outputs of the group counter 5 are bits of the internal bus of the group number BD, which is connected to the groups of D-inputs of the high bits of the first 10 output register RGM and the second 11 output register RGL, while the outputs of the priority encoder of the highest unit bit 7 are the bits of the internal bus of the number of the highest unit bit UM in the group that is connected to the group of D-inputs of the least significant bits of the first 10 output register RGM, and the outputs of the priority encoder of the least significant bit 8 are the bits of the internal bus number of the least significant one bit UL in the group that is connected to the group of D-inputs of the least significant bits second 11 output register RGL,

moreover, the outputs of the units counting module 9 are the bits of the internal bus of the number of unit bits in the group AU, which is connected to the group of inputs of the first term of the second adder 14 unit bits SMU, whose output is connected to the group D-inputs of the third output register of the number of unit bits 15, the output of which connected to the group of inputs of the second term of the second adder 14 single bits SMU,

in addition, the output of the first 10 output register RGM is connected to a group of direct inputs of the first term of the first adder 12 difference SMS, in which the inverse group of inputs of the second term is connected to the outputs of the second 11 output register RGL, and the value of the logical unit "1" is applied to the transfer input CI, the output of the first adder 12 of the SMS difference is connected to the second group of inputs of the addend of the incrementer INC 13,

moreover, the output bits of the first output register 10 are n bits of the output bus 20 of the number of the highest unit bit QM, the bits of the outputs of the incrementer INC 13 and the output of the transfer CO of the incrementer INC 13 are the corresponding (n + 1) bits of the output bus 21 of the QD range width, the bits of the outputs of the second output register 11 are n bits of the output bus 22 of the number of the least significant bit QL, the bits of the outputs of the third output register 15 are (n+1) bits of the output bus 23 of the number of single bits QU.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a functional diagram of the proposed group structure device for detecting the boundaries of the range of single bits. In FIG. 2 and FIG. Figure 3 shows per-clock timing diagrams of operation for test examples with the number of bits of the input binary number N=16, the number of bits in the input data group M=4 and the number of groups L=4.

In FIG. 1-3 and the following designations are introduced in the text:

N - the number of digits of the input binary number,

M - the number of digits in the input data group,

L - the number of groups in the input binary number, where N=M*L,

D - input bus;

D0, ..., D3 (D(M-l) - binary digits of the M-bit group of the input bus;

QM - n bit output bus number of the most significant bit of the N bit binary number, where N=2 ⁿ , n=log ₂ N;

QL - n bit output bus number of the least significant bit of the N bit binary number;

QD - (n+1) bit output bus width range N bit binary number;

QU - (n+1) bit output bus of the number (sum) of single bits in the N bit binary number;

QF1 - output flag of single bits;

UM - internal m bit bus number of the most significant bit in the M-bit group, where M=2 ^m , m=log ₂ M;

UL - internal m bit bus number of the least significant bit in the M-bit group;

BD - internal (n-m) bit bus of the group number;

FU - internal flag of single bits in the group;

AU - internal (m+1) bit bus of the number of single bits in the M-bit group;

C - clock input;

CE - work permission input;

CLR - input of asynchronous setting to the zero state;

R - input of the synchronous setting to the zero state;

S - input synchronous installation in a single state;

START - external input to start work;

STOP - external stop input;

AND - element AND;

OR - OR element;

INC - range incrementer;

SM - adder;

CI - input transfer of the adder;

CO - output transfer of the adder;

ST - counter;

RG - register;

RGM - register of the highest number of single bits;

RGL - register of the minor number of single bits;

SMS - adder of the difference between the major and minor numbers;

SMU - unit bit adder;

T - trigger;

TSS - start-stop trigger;

TU - 1-bit flip-flop.

1 - the first start-stop trigger TSS;

2 - the second trigger of single bits TU;

3 - the first element AND (AND);

4 - the second element AND (AND);

5 - group counter;

6 - element OR (OR);

7 - priority encoder of the highest unit digit;

8 - priority encoder of the least significant bit;

9 - unit count module,

10 - the first output register of the number of the highest single bit RGM;

11 - the second output register of the number of the least significant single bit RGL;

12 - the first adder of the difference between the senior and junior SMS numbers;

13 - incrementer for increasing the width of the range INC;

14 - the second adder of single bits SMU;

15 - the third output register of the number (sum) of single bits;

16 - external stop input STOP;

17 - external input start work START;

18 - external clock input C;

19 - external input of asynchronous setting to zero state CLR;

20 - n bit output bus number of the highest unit bit QM;

21 - (n+1) bit output bus width range QD;

22 - n bit output bus number of the least significant bit QL.

23 - (n+1) bit output bus of the number (sum) of single bits QU;

24 - external flag of single bits QF1.

The proposed group structure device for detecting the boundaries of the range of single bits contains M bits D0, ..., D(M-1) of the input data group from the N bit binary number, consisting of L sets of M bits in the group, where N=L*M, the output n bit line 20 of the number of the most significant unit bit QM, where n=log ₂ N and N=2 ⁿ , output (n+1) bit line 21 of the range width QD, output n bit line 22 of the number of the least significant unit bit QL, output (n+ 1) bit line 23 of the number of single bits QU, output flag 24 single bits QF1, the first trigger 1 start-stop TSS, the second trigger 2 single bits TU, the first element AND 3, the second element AND 4, group counter 5, element OR 6, MSB priority encoder 7, LSB priority encoder 8, units counting module 9, RGM first output register 10, LSB number RGL second output register 11, SMS difference adder 12, incrementer INC 13, the second adder 14 single bits SMU, the third output register of the number of single bits 15, and also contains an external stop input 16 STOP, an external input 17 of the start of work START, an external input 18 clock signals C, an external input 19 asynchronous reset CLR , the internal flag of ones bits in the FU group, the internal m bit line of the number of the most significant unit bit UM in the M-bit group, where m=log ₂ M, M=2 ^m , the internal m bit line of the number of the least significant unit bit UL in the M-bit group , the internal (nm) bit line of the group number BD, the internal (m+1) bit line of the number of single bits in the M-bit group AU.

The first start-stop trigger TSS 6 takes a single value on the edge of the clock signal C between the signals of the external signals to start work START and stop STOP. The flag of single bits FU takes on a single value in the presence of single bits in the M-bit group of the input bus D0, D2, ..., D(M-l).

On the first adder 12 of the SMS difference, the bit number of the least significant bit transmitted from the second 11 output register RGL is subtracted from the bit number of the highest single bit transmitted from the first 10 output register RGM. Incrementor INC 13 increases the value of the second term by one at a single value at the input of the increment from the second trigger 2 single bits TU to take into account the difference in bits of the range boundaries. The second adder 14 of single bits SMU and the third output register 15 of the number of single bits form an accumulating adder and carry out the counting of units by groups.

The external clock input C 18 and the external CLR asynchronous reset input 19 are connected to the corresponding clock inputs C and the asynchronous reset CLR inputs of the first start-stop trigger 1 TSS, the second trigger 2 1-bits TU, group counter 5, the first output register 10 is the number of the highest single bit RGM, the second output register 11 is the number of the least significant single bit RGL and the third output register is the number of single bits 15.

The external input 17 of the start of work START is connected to the input S of the synchronous installation in a single state of the first trigger 1 start-stop TSS.

The external stop input 16 STOP is connected to the input R of the synchronous set to the zero state of the trigger TSS start-stop 1.

Moreover, M bits D0, ..., D(M-1) of the input data group are connected to the corresponding inputs of the OR element 6, the priority encoder of the most significant unit digit 7, the priority encoder of the least significant unit digit 8 and the unit count module 9.

The output of the OR element 6 is an internal flag of single bits FU and is connected to the second inputs of the first 3 and second 4 elements And and connected to the input S of the synchronous setting to the single state of the second trigger 2 single bits TU. The inverted output of the second trigger 2 single bits TU is connected to the first input of the second element And 4, the output of which is connected to the work permission input CE of the second output register 11 of the number of the least significant single bit RGL. The direct output of the second flip-flop 2 single bits TU is connected to the first input of the increase incrementer INC 13 and is the output flag of the single bits QF1.

Moreover, the output of the start-stop trigger 1 TSS is connected to the work enable input CE of the group counter 5, to the work enable input CE of the third output register 15 and to the first input of the first element AND 3, the output of which is connected to the work enable input CE of the first output register 10 of the number of the senior single bit RGM.

The outputs of the group counter 5 are bits of the internal bus number of the group BD, which is connected to the groups of D-inputs of the highest bits of the first 10 output register RGM and the second 11 output register RGL. The outputs of the priority encoder of the highest unit bit 7 are the bits of the internal bus number of the highest unit bit UM in the group, which is connected to the group of D-inputs of the least significant bits of the first 10 output register RGM. The outputs of the priority encoder of the least significant bit 8 are the bits of the internal bus number of the least significant single bit of the UL in the group that is connected to the group of D-inputs of the least significant bits of the second 11 output register RGL.

The outputs of the units counting module 9 are the bits of the internal bus of the number of single bits in the group AU, which is connected to the group of inputs of the first term of the second adder 14 unit bits SMU, whose output is connected to the group D-inputs of the third output register of the number of single bits 15, the output of which is connected with a group of inputs of the second term of the second adder 14 single bits SMU.

The output of the first 10 output register RGM is connected to a group of direct inputs of the first term of the first adder 12 difference SMS, in which the inverse group of inputs of the second term is connected to the outputs of the second 11 output register RGL, and the value of the logical unit "1" is applied to the transfer input CI. The output of the first adder 12 of the SMS difference is connected to the second group of inputs of the addend of the incrementer INC 13.

The bits of the outputs of the first output register 10 are n bits of the output bus 20 of the number of the highest unit bit QM. The bits of the outputs of the incrementer INC 13 and the transfer output CO of the incrementer INC 13 are the corresponding (n+1) bits of the output bus 21 of the QD range. The bits of the outputs of the second output register 11 are n bits of the output bus 22 of the number of the least significant bit QL. The bits of the outputs of the third output register 15 are (n+1) bits of the output bus 23 of the number of single bits QU.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The proposed device allows to detect the right (least significant) digit and the left (highest) digit of the input N-bit binary number, which have a single value, and to generate at the outputs of the device the numbers of the lower QL and the higher QM of single digits, the width of the range of single bits QD, the number (sum ) single bits QU, including boundaries, and if there are single bits, set the external flag of single bits QF1=1. If there are no single values in the bits of the input N-bit binary number, the outputs of the numbers QL and QM of the range boundaries, the width of the QD range, the sum of single bits QU are set to zero, and the external flag of the presence of single bits QF1=0 takes on the zero value.

The input N bit unsigned binary number is divided into L=N/M groups of M bits in each group, where N=2 ⁿ , n=log ₂ N, M=2 ^m , m=log ₂ M. Input data groups are sequentially received to the inputs of the device, while M binary digits of each of the L groups are fed in parallel to the corresponding inputs D0, ..., D(M-1) of the device (D0 is the least significant bit).

The operation of the device starts with a single START=1 signal and ends with a single stop signal STOP=1, which arrives simultaneously with the code of the last L-th group. Groups of input data arrive at each clock cycle on the rising edge of clock C.

On each cycle, the search for single bits in the M-bit group is carried out and the current numbers of the most significant and least significant single digits are formed, which are the least significant digits of the current numbers. At the same time, the groups are counted on the counter 5, the outputs of which are the highest digits of the current numbers. Thus, the full current numbers of identified single digits in a group are formed by combining two parts: the older one is the binary number of the group from the group counter 5, the younger one is the number of the digit in the group. Simultaneously, in the unit counting module 9, the units are counted in the M-bit group and the current total number of unit bits is counted in the second adder 14 unit bits SMU and the third output register 15.

Priority encoder 7 searches for the highest unit in the input M-bit group and generates at the output UM a binary m-bit number of this unit bit. The priority encoder 8 searches for the least significant unit in the input M-bit group and generates a binary m-bit number of this unit bit at the output UL. The codes on the internal buses UM and UL are the lower m digits of the current digit numbers, respectively, of the higher and lower unity, which are fed to the lower digits of the D-inputs, respectively, of the first 10 output register of the higher RGM number and the second 11 output register of the lower RGL number.

The group counter 5 counts groups and generates a binary code of the current group number at the output, which is transmitted to the internal bus BD and then to the higher bits of the D-inputs of the first 10th output register of the higher number RGM and the second 11th output register of the lower number RGL.

The number of units in the input M-bit group is counted by the units count module 9 and the binary code of the number (sum) of unit bits in the group is generated at the output AU. The current number (sum) of single bits in the input number is formed on the accumulative adder, implemented on the second 14 combinational adder of single bits SMU, and the third output register 15.

The width of the range of single bits is formed on the first 12 SMS adder as the difference between the current numbers of the highest and lowest single bits fixed respectively on the first 10 and second 11 output registers. The width of the range of single bits from the output of the first 12 adder SMS is further increased by one on the incrementer 13 INC, to correct the difference in the bits of the range boundaries, and is transmitted to the (n + 1) bit output bus of the range width QD. In this case, the most significant bit of the QD bus is the transfer output of the CO incrementer 13 INC.

At the output of the OR 6 element, a single value is formed when single values are detected in the input M-bit group, and the internal single flag FU=1 is set. The output of the OR element 6 is connected to the second inputs of the first 3 and second 4 elements AND and is connected to the input S of the synchronous setting to the single state of the second trigger 2 single bits TU, the inverse output of which is connected to the first input of the second element AND 4, the output of which is connected to the enable input work CE second output register 11. The direct output of the second trigger 2 single bits TU is the output flag of single bits QF1 and is also connected to the input increase by "1" incrementor 13 INC. The output of the first 1 start-stop trigger TSS is connected to the first input of the first element AND 3, which is connected to the work enable input CE of the first output register 10. Unit values at the outputs of the first element AND 3 and the second element AND 4 allow recording the current full values of the numbers of the highest and lower unit (range limits), respectively, to the first 10 output register RGM and the second 11 output register RGL, based on the values of which the current value of the QD range width code is formed on the first 12 SMS adder and the incrementer 13 INC.

The outputs of the first 10 output register RGM, the second 11 output register RGL, the incrementer INC 13 and the third output register 15 are the outputs of the corresponding output buses.

Thus, in the proposed device, on the output buses, in each clock cycle, the current values of the number of the most significant unit bit QM, the number of the least significant unit bit QL, the width of the QD range, the number (sum) of unit bits QU and the output flag of unit bits QF1 are set. On a single stop signal STOP on the corresponding output buses QM, QL, QD, QU and QF1, the final values for the input N bit binary number will be fixed.

The proposed device works as follows.

Before starting work, a signal is given at the external input 19 of the asynchronous setting to the zero state CLR, according to which the first trigger 1 start-stop TSS=0, the second trigger 2 single bits TU=0, the group counter 5 BD=0, the output first 10, second 11 and third 15 registers.

Further, with a single value of the start signal at the external 17 input START=1 (cycles 1 in Fig. 2 and Fig. 3 at N=16, M=4, L=4) on cycle 2 along the edge of the clock signal C at the external input 18 the first 1 start-stop trigger TSS=1 is set to the single state.

Further, in each cycle 2-5, starting from cycle 2, the external inputs of the device D0, ..., D3 (DM-1) receive in parallel M=4 bits of consecutive L=N/M=4 groups of the input N=16 bit binary number unsigned (with n=log ₂ N=4, m=log ₂ M=2). In this case, the least significant bit D0 is the first (right) bit of each input group (in Fig. 2 and Fig. 3, the least significant bits are shown on the left, the senior ones on the right). The values from the input bus D are fed to the corresponding inputs of the priority encoder of the highest unit digit 7, the priority encoder of the least significant unit digit 8, the OR element 6 and the unit count module 9.

On each cycle, the search for single bits in the M-bit group is carried out and, when single values are detected, the priority encoder 7 generates a binary m-bit number of the current high-order unit bit at the output UM, priority encoder 8 generates a binary m-bit number of the current low-order unit bit at the output UL , at the output of the OR 6 element, when single values are detected in the input M-bit group, a single value of the internal single flag FU=1 is formed, the units counting module 9 counts single bits, and at the output AU a binary code of the number (sum) of single bits in the group is formed.

In FIG. 2 shows two test cases - test No. 1 and test No. 2, in Fig. Figure 3 also shows two test cases - test #3 and test #4. In FIG. 2 in parentheses indicates the representation of values in binary code (2) or decimal code (10), and the outputs of flip-flops TSS and TU, flags of single bits FU and QF1 and logic elements 3 and 4 are shown in the form of timing diagrams.

In test No. 1 in cycle 2, the code of the zero group 0001, containing only one unit (D3=1), arrives at the inputs D0, ..., D3, therefore, at the outputs of the priority encoder 7, a binary two-digit number UM of the current senior unit digit UM=3 is formed and on The outputs of the priority encoder 8 form a binary two-digit number UL of the current low-order unit digit UL=3, which are transmitted to the two lower D-inputs, respectively, of the first 10 output register of the higher RGM number and the second 11 output register of the lower RGL number. At the same time, the code from the internal group bus BD=00 is transmitted to the two highest D-inputs of the first 10 and second 11 registers, since the code of the zero group is set on the group counter 5. At the same time, codes are set at the D-inputs of the first 10 and second 11 registers: D-RGM=00 11 and D-RGL=00 11.

_{In addition, the binary code AU (10)} =1 is generated at the output of the units counting module 9, which is added to the second 14 adder of unit bits SMU with a zero code at the output of the third register 15 and the code SMU ₍₁₀₎ =l is set at the output of the adder, which is transmitted to the D-inputs of the third register 15, which is written to at each cycle along the edge of the clock signal C at a single value of the first 1 start-stop trigger TSS=1.

At the same time, at the output of the OR element 6, a single value of the internal single flag FU=1 is formed. Therefore, further single values are set at the outputs of the first 3 and second 4 elements AND.

In cycle 3 of test No. 1 along the edge of clock signal C, with unit values at the outputs of the first element AND 3 and the second element AND 4, set in cycle 2, the corresponding current values of the numbers of the highest and lowest unit digits and the number (sum) of units are recorded on the output the first 10, the second 11 and the third 15 registers, respectively, and transferring these values to the output buses: QM=3, QL=3, QU=1. Also in cycle 3, on the edge of the clock signal, the second trigger 2 single bits TU=1 switches to a single state, at the inverse output of which a zero value is formed, and a single value of the output flag of single bits QF1=1 is formed. Further, according to the current values of the numbers of the most significant and least significant single digits on the first 12 adder SMS=0000 and incrementer 13, the range width code INC ₍₂₎ =0001 is generated, which is transmitted to the output bus QD ₍₁₀₎ =l. In addition, in cycle 3 of test No. 1, on the edge of clock signal C, the group counter 5 passes to the next state and the code BD ₍₂₎ = 01 is set on the internal group bus, the bits of which are the two most significant bits of the current number for the first group, which corresponds to the code with a shift 2 digits towards the higher digits BD*2 ^+m ₍₁₀₎ =4.

At the same time, in cycle 3 of test No. 1, the code of the next first group 1100, containing two lower units (D0=1, D1=1), is received at inputs D0, ..., D3, for which, similarly to cycle 2, two-digit codes of numbers of unit digits UM=1 and UL=0, the number (sum) of units AU=2 and at the output of the element OR 6 a single value of the internal single flag FU=1 is formed. At the same time, codes are set at the D-inputs of the first 10 and second 11 registers: D-RGM=01 01 and D-RGL=01 00, and at the output of the second 14 adder of single bits SMU=3.

In cycle 4 of test No. 1 along the edge of the clock signal C, with a unit value of the output of the first element AND 3, set in cycle 3, the corresponding current values of the number of the highest unit digit and the number (sum) of units are recorded in the output first 10 and third 15 registers, respectively, and transferring these values to the output buses: QM=5, QU=3. But since the zero value is set at the output of the second element AND 4, then the second register 11 is not written to and the code of the least significant bit RGL=0011 (QL=3) is stored, set at cycle 3. On the following cycles, writing to the second register 11 is also not is carried out, since the inverse output of the second 2 flip-flop TU is set (stored) to zero. Further, according to the current values of the numbers of the senior and junior unit digits, the range width code INC( ₂ )=0011 (QD ₍₁₀₎ =3) is formed.

In addition, in cycle 4 of test No. 1 on the edge of the clock signal C, the group counter 5 passes to the next state and the code BD ₍₂₎ = 10 is set on the internal group bus, the digits of which are the most significant digits of the current number for the second group, which corresponds to a code with a shift by 2 digits towards high digits BD*2 ^+m ₍₁₀₎ =8.

At the same time, in cycle 4 of test No. 1, the code of the second group 0111 is received at inputs D0, ..., D3, containing three high units, for which, similarly to cycle 3, codes are formed: UM=3, UL=1, AU=3, D-RGM=10 11, D-RGL=10 01 and SMU=6.

In cycle 5 of test No. 1 along the edge of clock signal C, with a single value at the output of the first element AND 3, set in cycle 4, the corresponding current values of the number of the highest unit digit are recorded and the number (sum) of units is written to the output first 10 and third 15 registers, respectively , and transferring these values to the output buses: QM=11, QU=6. Further, according to the current values of the numbers of the senior and junior unit digits, the range width code INC ₍₂₎ =1001 (QD ₍₁₀₎ =9) is formed.

At the same time, in cycle 5 of test No. 1, the code of the third group 0010, containing one unit (D2=1), is received at inputs D0, ..., D3, for which, similarly to cycle 3, codes are formed: UM=2, UL=2, AU=1, D -RGM=11 10, D-RGL=11 10 and SMU=7. In addition, a single value is set at the external stop input 16 STOP=1.

In cycle 6 of test No. 1, on the edge of the clock signal C, the corresponding codes are written to the output registers and the range width code INC ₍₂₎ =1100 (QD ₍₁₀₎ =12) is formed. At the same time, the first 1 start-stop trigger TSS=0 is switched to the zero state by the STOP=1 signal.

Thus, for test No. 1 on the output buses of the device, the codes of unit bit boundaries, range width, number of units will be set: QM=14, QL=3, QD=12, QU=7 and the external flag of unit bits QF1=1.

For test No. 2 (Fig. 2), similarly as in test No. 1, in cycle 1, before starting work, signals CLR and START=1 are given.

In test No. 2 for the code of the zero group D0, …, D3=0011 and the code of the first group D0, D3=0110 in cycles 2 and 3, the corresponding codes are formed in the same way as in test No. 1.

In cycle 4 of test No. 2, the code of the second group 0000 containing only zero values enters the inputs D0, D3. Therefore, a zero value is set at the output of the OR 6 element, since there are no single bits in the input group, and the internal flag FU=0, and then zero values are formed at the output of the first element AND 3 and at the output of the second element AND 4. Therefore, in cycle 5 to the front of the clock signal C is not written to the output first 10 and second 11 registers and the values are stored on the corresponding output buses. Writing to the third register 15 is performed, but the value is also stored, since there are no units AU=0 in the second input group.

In cycles 5 and 6 of test No. 2, similarly to test No. 1, the corresponding codes are formed, and recording is carried out in the output registers.

As a result, for test No. 2 on the output buses of the device, the codes for the boundaries of single digits, the width of the range, the number of units will be set: QM=12, QL=2, QD=11, QU=5, and the external flag of single bits QF1=1.

In test No. 3 (Fig. 3) in cycles 2 and 3, the code 0000 containing only zero values enters the inputs D0, D3 for the zero and first groups. Therefore, the zero value is set at the output of the OR element 6, since there are no single bits in the input group, and the internal flag FU=0, and then zero values are formed at the output of the first element AND 3 and at the output of the second element AND 4. Therefore, in cycles 3 and 4 on the edge of the clock signal C is not written to the output of the first 10 and second 11 registers and zero values are stored on the corresponding output buses. Writing to the third register 15 is performed, but the zero value is also stored, since there are no AU=0 units in the input groups.

In cycles 4-6 of test No. 3, similarly to test No. 1, the corresponding codes for the second and third input groups are formed at the inputs D0, ..., D3, and the output registers are written.

As a result, for test No. 3, the codes of unit bit boundaries, range width and number of units will be set on the output buses of the device: QM=13, QL=9, QD=5, QU=4, and the external flag of unit bits QF1=1.

In cycle 2 of test No. 4 (Fig. 3), the zero group code 1000 containing only one unit in the least significant zero digit D0=1 arrives at the inputs D0, ..., D3. Therefore, zero codes of numbers of the senior and junior unit digits UM=0 and UL=0 are formed. At the same time, at the output of the OR element 6, a single value of the internal single flag FU=1 is formed. Therefore, further single values are set at the outputs of the first 3 and second 4 elements AND.

In cycle 3 of test No. 4, the corresponding codes are written to the output registers. Also in cycle 3, on the edge of the clock signal, the second trigger 2 single bits TU=1 switches to the single state, at the inverse output of which a zero value is formed, and a single value of the output flag of single bits QF1 is formed.

In cycle 3 of test No. 4, the code of the first group 0000 containing only zero values is received at inputs D0, ..., D3, for which, similarly to cycle 4 of test No. 2, the flag FU=0 is formed, the output registers are not written and their values are saved.

In cycles 4 and 5 of test No. 4, the codes of the second group D0, D3=0100 and the code of the third group D0, ..., D3=0001 are received at the inputs D0, D3. In this case, in the third group, the single digit is the senior third D3=l (the senior fifteenth digit for the input N=16 bit binary number). In cycles 4 and 5, the corresponding codes are formed in the same way as in test No. 1 and the output registers are written. In this case, the following codes will be set in the output registers: QM=15, QL=0, QU=3. Further, according to the current values of the numbers of the most significant and least significant single digits, the code SMS=1111 is generated on the first adder 12, and the range width code INC(2)=0000 is formed on the incrementer 13. But at the same time, a single value is formed at the transfer output CO=1, which is transferred to the highest (n+1) bit of the output bus QD and the code QD ₍₁₀₎ =16 is set, corresponding to the range between zero and fifteenth digits for the input N=16 bit binary numbers.

As a result, for test No. 4 on the output buses of the device, the codes for the boundaries of unit digits, the width of the range, the number of units will be set: QM=15, QL=0, QD=16, QU=3 and the external flag of unit bits QF1=1.

The above information allows us to conclude that the proposed device solves the problem of identifying the boundaries of the range of single bits, estimating the width of the range and counting the number (sum) of single bits, as well as fixing the number of the left (highest) single bit and the number of the right (lower) single bit at the outputs of the device. bit in the input, the range width code, and the number of 1 bits in the range.

Claims (11)

The group structure device for detecting the boundaries of the range of single bits contains M bits D0, ..., D(M-1) of the input data group from the N bit binary number, consisting of L sets of M bits in the group, where N=L*M, output n bit line 20 of the number of the most significant unit digit QM, where n=log ₂ N and N=2 ⁿ , output (n+1) bit line 21 of the range width QD, output n bit line 22 of the number of the least significant unit digit QL, output (n+1 ) bit line 23 number of single bits QU, output flag 24 single bits QF1, first trigger 1 start-stop TSS, second trigger 2 single bits TU, first element AND 3, second element AND 4, group counter 5, element OR 6, priority MSB Encoder 7, LSB Priority Encoder 8, Units Counting Module 9, First Output Register 10 of RGM High One Bit Number, Second Output Register 11 of RGL LSB Number, First SMS Difference Adder 12, INC Incrementer 13, Second th adder 14 single bits SMU, the third output register of the number of single bits 15, and also contains an external input 16 stop STOP, external input 17 start work START, external input 18 clock signals C, external input 19 asynchronous reset CLR, internal flag unit bits in the FU group, the internal m bit line of the number of the most significant unit bit UM in the M-bit group, where m=log ₂ M, M=2 ^m , the internal m bit line of the number of the least significant unit bit UL in the M-bit group, internal ( nm) bit line of the group number BD, internal (m+1) bit line of the number of single bits in the M-bit group AU, wherein the external clock input C 18 and the asynchronous reset external input CLR 19 are connected to the corresponding clock inputs C and the asynchronous reset CLR inputs of the first start-stop trigger 1 TSS, the second trigger 2 1-bits TU, the group counter 5 , the first output register 10 of the number of the highest single bit RGM, the second output register 11 of the number of the least significant single bit RGL and the third output register of the number of single bits 15, the external input 17 of the start of work START is connected to the input S of the synchronous installation in a single state of the first trigger 1 start-stop TSS, the external input 16 of the stop STOP is connected to the input R of the synchronous set to the zero state of the trigger TSS start-stop 1, moreover, M bits D0, ..., D(M-1) of the input data group are connected to the corresponding inputs of the OR element 6, the priority encoder of the highest unit digit 7, the priority encoder of the least significant unit digit 8 and the unit count module 9, while the output of the OR element 6 is an internal flag of single bits FU and is connected to the second inputs of the first 3 and second 4 elements AND and is connected to the input S of the synchronous setting to the single state of the second trigger 2 single bits TU, the inverse output of which is connected to the first input of the second element And 4, the output of which is connected to the operation enable input CE of the second output register 11 of the number of the least significant single bit RGL, and the direct output of the second trigger 2 single bits TU is connected to the first input of the increase of the incrementer INC 13 and is the output flag of single bits QF1, moreover, the output of trigger 1 start-stop TSS is connected to the work enable input CE of the group counter 5, to the work enable input CE of the third output register 15 and to the first input of the first element AND 3, the output of which is connected to the work enable input CE of the first output register 10 of the highest number single bit RGM, in addition, the outputs of the group counter 5 are bits of the internal bus of the group number BD, which is connected to the groups of D-inputs of the high bits of the first 10 output register RGM and the second 11 output register RGL, while the outputs of the priority encoder of the highest unit bit 7 are bits of the internal bus number the most significant one bit UM in the group that is connected to the group of D-inputs of the least significant bits of the first 10 output register RGM, and the outputs of the priority encoder of the least significant one bit 8 are the internal bus bits of the number of the least significant one bit UL in the group that is connected to the group of D-inputs of the least bits of the second 11 output register RGL, moreover, the outputs of the units counting module 9 are the bits of the internal bus of the number of unit bits in the group AU, which is connected to the group of inputs of the first term of the second adder 14 unit bits SMU, whose output is connected to the group D-inputs of the third output register of the number of unit bits 15, the output of which connected to the group of inputs of the second term of the second adder 14 single bits SMU, in addition, the output of the first 10 output register RGM is connected to a group of direct inputs of the first term of the first adder 12 difference SMS, in which the inverse group of inputs of the second term is connected to the outputs of the second 11 output register RGL, and the value of the logical unit "1" is applied to the transfer input CI , the output of the first adder 12 of the SMS difference is connected to the second group of inputs of the addend of the incrementer INC 13, moreover, the output bits of the first output register 10 are n bits of the output bus 20 of the number of the highest unit bit QM, the bits of the outputs of the incrementer INC 13 and the output of the transfer CO of the incrementer INC 13 are the corresponding (n + 1) bits of the output bus 21 of the width of the range QD, the bits of the outputs of the second output register 11 are n bits of the output bus 22 of the number of the least significant bit QL, the bits of the outputs of the third output register 15 are (n+1) bits of the output bus 23 of the number of single bits QU.

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