RU2756408C1 - Computing apparatus - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: disclosed is a computing apparatus for finding the remainder modulo and the partial quotient, ensuring computation of the remainder R of the number A modulo P by means of sequential execution of (n/2-1) operations, wherein n is the amount of bits of the input number A in accordance with the expression: R=(2²(2²...(2²(a_n-1·2+a_n-2)+(a_n-3·2+a_n-4))+…+(a₃·2+a₂))+(a ₁·2+a ₀)) mod P, wherein a _i,

are the coefficients in the binary representation of the number A.

EFFECT: increase in the operation speed of the apparatus for computing the remainder modulo and the partial quotient.

1 cl, 2 dwg, 4 tbl

Description

The invention relates to computer technology and can be used to find the remainder modulo and incomplete quotient in digital computing devices, in cryptographic applications, as well as in digital signal processing devices and control systems.

There is a known device for forming the remainder of an arbitrary modulus of a number, containing registers, OR elements, a calculator, comparison circuits, a multiplexer, a delay element, an adder, a group of blocks of elements "I" and a block of permanent memory with connections (see AS USSR No. 1633495, cl . H 03 M 7/18, 1991). The disadvantage of the known device is low reliability, since its implementation requires a large amount of equipment.

Known is a combinational recurrent generator of residuals containing a combinational former of partial residuals, a block of keys and a block of modular adders (see RF patent No. 2029435, cl. 6 H 03 M 7/18, 20.02.1995, bull. No. 5). The disadvantage of this device is its limited functionality, namely the lack of the possibility of forming an incomplete private.

Known computing device containing adders and multiplexers (see RF patent No. 2348965, IPC G06F 7/72 (2006.01), H03M 7/18 (2006.01), 03/10/2009. Bull. No. 7). The disadvantage of this computing device is the large amount of equipment.

The closest in technical essence to the claimed invention is a computing device containing adders and multiplexers (see RF patent No. 2717915, IPC G06F 7/72 (2006.01), H03M 7/18 (2006.01), 03/26/2020. Bull. No. 9) ... The disadvantage of this computing device is its low performance.

The technical result of the invention is to increase the speed of the device, namely, to increase the speed of calculating the remainder modulo and incomplete quotient.

– четное и больше 2, образующих (n/2-1) ступеней преобразования, вход подачи двоичного кода числа, выход двоичного кода неполного частного, выход двоичного кода остатка от числа дополнительно введены на каждой ступени преобразования три схемы сравнения, трехвходовый элемент ИЛИ и двухвходовый элемент И, на первые информационные входы первых схем сравнения всех ступеней преобразования подается двоичный код модуля, на первые информационные входы вторых схем сравнения всех ступеней преобразования подается двоичный код удвоенного модуля, на первые информационные входы третьих схем сравнения всех ступеней преобразования подается двоичный код утроенного модуля, выходы первой, второй и третьей схем сравнения соединены соответственно с первым, вторым и третьим управляющими входами мультиплексора и с первым, вторым и третьим входами трехвходового элемента ИЛИ соответствующих ступеней преобразования, выход трехвходового элемента ИЛИ каждой ступени преобразования соединен с первым входом двухвходового элемента И соответствующей ступени преобразования, на второй вход двухвходового элемента И всех ступеней преобразования подается логическая единица, выход двухвходовых элементов И всех ступеней преобразования соединен со входом переноса сумматоров соответствующей ступени преобразования, на первый, второй и третий информационные входы мультиплексоров всех ступеней преобразования подаются соответственно инверсные двоичные коды модуля, удвоенного модуля и утроенного модуля, первые информационные выходы мультиплексоров всех ступеней преобразования соединены с первыми информационными входами сумматоров соответствующих ступеней преобразования, j-е разряды вторых информационных входов сумматоров и вторых информационных входов схем сравнения i-й ступени преобразования, где j=(0;1), соединены с (n-2i-j-1)-ми разрядами двоичного кода входного числа соответственно, второй и третий разряды вторых информационных входов сумматора и вторых информационных входов схем сравнения первой ступени преобразования соединены с (n-2)-м и (n-1)-м разрядами двоичного кода входного числа соответственно, информационные выходы сумматоров i-й ступени преобразования, где i=1,.., n/2-2, соединены со сдвигом на два разряда в сторону старших со вторыми информационными входами сумматоров и вторыми информационными входами схем сравнения (i+1)-й ступени преобразования, информационный выход сумматора (n/2-1)-й ступени преобразования является выходом двоичного кода остатка, вторые информационные выходы мультиплексоров являются выходом двоичного кода неполного частного, причем мультиплексор каждой ступени преобразования содержит два инвертора, трехвходовый элемент И, двухвходовый элемент И, три ключа, блок элементов ИЛИ и два элемента ИЛИ, причем первый вход трехвходового элемента И является первым управляющим входом мультиплексора, первый вход двухвходового элемента И является вторым управляющим входом мультиплексора и соединен со входом первого инвертора, выход которого соединен со вторым входом трехвходового элемента И, управляющий вход третьего ключа является третьим управляющим входом мультиплексора и соединен со входом второго инвертора и со вторыми входами первого и второго элементов ИЛИ, выходы которых являются вторым информационным выходом мультиплексора, выход второго инвертора соединен с третьим входом трехвходового элемента И и со вторым входом двухвходового элемента И, выход которого соединен с управляющим входом второго ключа и с первым входом второго элемента ИЛИ, выход трехвходового элемента И соединен с первым входом первого элемента ИЛИ и с управляющим входом первого ключа, информационные входы первого, второго и третьего ключей являются соответствующими информационными входами мультиплексора, а выходы соединены с соответствующими информационными входами блока элементов ИЛИ, выход которого является первым информационным выходом мультиплексора.To achieve a technical result in a computing device containing ( n / 2-1) adders, ( n / 2-1) multiplexers, where n is the input number,

- even and more than 2 forming ( n / 2-1) conversion steps, input for feeding the binary code of a number, output of the binary code of an incomplete quotient, output of the binary code of the remainder of the number, three comparison circuits, a three-input OR element and a two-input element And, the binary code of the module is fed to the first information inputs of the first comparison circuits of all conversion stages, the binary code of the doubled modulus is fed to the first information inputs of the second comparison circuits of all conversion stages, the binary code of the triple modulus is fed to the first information inputs of the third comparison circuits of all conversion stages, the outputs of the first, second and third comparison circuits are connected respectively to the first, second and third control inputs of the multiplexer and to the first, second and third inputs of the three-input OR element of the corresponding conversion stages, the output of the three-input OR element of each conversion stage is connected to the first input of the two-in of one AND element of the corresponding conversion stage, a logical unit is supplied to the second input of the two-input AND element of all conversion stages, the output of the two-input AND elements of all conversion stages is connected to the transfer input of the adders of the corresponding conversion stage, to the first, second and third information inputs of the multiplexers of all conversion stages, respectively inverse binary codes of the module, doubled module and triple module, the first information outputs of the multiplexers of all conversion stages are connected to the first information inputs of the adders of the corresponding conversion stages, the j -th bits of the second information inputs of the adders and the second information inputs of the comparison circuits of the i- th conversion stage, where j = (0; 1), connected to the ( n -2 i - j -1) th bits of the binary code of the input number, respectively, the second and third bits of the second information inputs of the adder and the second information inputs of the comparison circuits of the first conversion stages are connected to the ( n -2) -th and ( n -1) -th bits of the binary code of the input number, respectively, the information outputs of the adders of the i -th conversion stage, where i = 1, .., n / 2-2, are connected with a shift by two digits towards the higher ones with the second information inputs of the adders and the second information inputs of the comparison circuits of the ( i + 1) -th conversion stage, the information output of the adder of the ( n / 2-1) -th conversion stage is the output of the binary code of the remainder, the second the information outputs of the multiplexers are the output of the binary code of an incomplete quotient, and the multiplexer of each conversion stage contains two inverters, a three-input AND gate, a two-input AND gate, three keys, an OR gate and two OR gates, and the first input of the three-input AND gate is the first control input of the multiplexer, the first input of the two-input AND element is the second control input of the multiplexer and is connected to the input of the first inverter, the output of which is connected n with the second input of the three-input element AND, the control input of the third key is the third control input of the multiplexer and is connected to the input of the second inverter and to the second inputs of the first and second OR elements, the outputs of which are the second information output of the multiplexer, the output of the second inverter is connected to the third input of the three-input element And and with the second input of the two-input AND element, the output of which is connected to the control input of the second key and to the first input of the second OR element, the output of the three-input AND element is connected to the first input of the first OR element and to the control input of the first key, information inputs of the first, second and third keys are the corresponding information inputs of the multiplexer, and the outputs are connected to the corresponding information inputs of the OR element block, the output of which is the first information output of the multiplexer.

The essence of the invention lies in the implementation of the following method for calculating the remainder R of the number A modulo P. Let be

A = Q P + R , (1)

where A is a positive integer from which it is necessary to calculate the remainder R ;

P is a positive integer called the modulus;

Q is a positive integer that is an incomplete quotient of dividing A by P ;

R is a positive integer that is the remainder of dividing A by P.

Moreover

A = a _{n -1} · 2 ^{_n -1} + a ⁿ _-2 · 2 ^{_n -2} + a ⁿ _-3 · 2 ^{_n -3} + a ⁿ _-4 · 2 ^{n -4} +. ... ... + A ₃ · 2 ³ + a ₂ x 2 ² + a ₁ · 2+ a ₀ (2)

P = p _{n -1} · 2 ^{_n -1} + p ⁿ _-2 · 2 ^{n -2} +. ... ... + P ₁ · 2 ¹ + p ₀ (3)

Q = q _{n -2} · 2 ^{n -2} +. ... ... + Q ₁ · 2 ¹ + q ₀ (4)

R = r _{n -2} * 2 ^{n -2} +. ... ... + R ₁ · 2 ¹ + r ₀ (5)

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения числа A; where a _i ,

- coefficients taking the value 0 or 1 depending on the value of the number A ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения модуля P; p _i ,

- coefficients taking the value 0 or 1 depending on the value of the module P ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения неполного частного Q; q _i ,

- coefficients that take the value 0 or 1 depending on the value of the incomplete quotient Q ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения остатка R; r _i ,

- coefficients taking the value 0 or 1 depending on the value of the remainder R ;

n is the number of digits in the representation of numbers, n is even.

The task is to find the remainder R and the incomplete quotient Q from the known A and P. The residue is R in terms of the theory of numbers minus the number of A modulo P, so it says A comparable R modulo P:

A ≡ R (mod P ). (6)

The residual value R can be calculated as follows:

R ≡ A (mod P) = (a n -1 · 2 ^{_n -1} + a ⁿ _-2 · 2 ^{n -2} +... + A ₁ · 2+ a ₀₎ mod P. (7)

Let us rewrite expression (2) in the following form, combining two adjacent terms:

A = (a _{n -1} ·2 ^{n -1}+a _{n -2} ·2 ^{n -2}) + (a _{n -3} ·2 ^{n -3}+a _{n -4} ·2 ^{n -4}) +. ... ... + (a ₃ ·2³+a ₂ ·2²) + (a ₁ ·2+a ₀), (eight)

, принимает только четные значения:From each sum in brackets in expression (8) we take out 2 ⁱ outside the brackets, where

, takes only even values:

A = 2 ^{_{n -2 (a n -1 · 2+}} a n -2) +2 n -4 (a n -3 · 2+ a n -4) +. ... ... 2 ² (a ₃ · 2+ a ₂₎ + (a ₁ · 2+ a _0), (9)

, принимает только четные значения.In expression (9) to each of the n / 2 the formed sums of the form _{(a i +1 · 2+ a i} ), we get the factor 2 ^i, where

, takes only even values.

Next, we take the smallest nonzero degree 2 outside the brackets in (9):

A = 2²(2 ^{n -4}(a _{n -1} ·2+a _{n -2}) + 2 ^{n -6} (a _{n -3} ·2+a _{n -4}) +. ... ... + (a ₃ ·2+a ₂)) + (a ₁ ·2+a ₀), (ten)

Performing sequentially transformation (10) ( n / 2) -2 times we get:

A = February ² (Feb. ² ... (Feb. ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4)) +... + (A ₃ · 2+ a ₂₎₎ + (a ₁ a ₀ · 2+), (11)

where 2 ² occurs ( n / 2) -1 times.

Then expression (7) can be represented as follows:

R = (2 ² (2 ... ² (2 ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4)) +... + (A ₃ 2 · + a ₂₎₎ + (a ₁ · 2+ a ₀₎₎ mod P. (12)

It is known from number theory that the operation of reduction modulo is invariant to addition and multiplication, that is, the value of the remainder does not depend on whether it is calculated from the sum (product) or from each term (factor), and then the corresponding partial remainders are summed ( multiplied) and the remainder of the result is calculated modulo.

Based on the above, expression (12) can be calculated as follows.

First, at the first stage of conversion, the value is calculated

t = ₁ (February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4)) mod P. (13)

At the second stage of conversion, the value is calculated

t ₂ = (2 · t ² _{1 + (a n -5 · 2+ a} n -6)) mod P. (fourteen)

At the last ( n / 2-1) th conversion stage, the value is calculated

mod P, _{(15) t n / 2-1 = ((} a ₁ · 2+ a ₀₎ ² February · t _{n / 2-2} +)

which is the desired remainder R of the number A modulo P.

The operation of reduction modulo P at each transformation stage is performed based on the following considerations.

By definition, the value t _{i -1} lies in the range ₀ ≤ t _i -1 ≤ P -1, therefore, in accordance with expressions (13) - (15), the value

t _i = t _i February ² _-1 + _(-2 a _{n i -1} · 2+ a _{-2 i n -2),} (16)

before bringing it modulo can take values in the range from 0 to 4 P -1. The modulus of the value t _i is reduced according to the following rules

t _i (mod P ) = t _i if 0 ≤ t _i < P , (17)

t _i (modP) =t _i -P, ifP≤t _i <2P,

t _i (modP) =t _i - 2Pif 2P≤t _i <3P,

t _i (modP) =t _i - 3Pif 3P≤t _i <4P...

The bits of the incomplete quotient Q at each stage of the calculations take on values in accordance with Table 1.

Table 1.

senior rank least significant digit T _i 0 0 0 ≤ t _i < P 0 1 P ≤ t _i <2 P 1 0 2 P ≤ t _i <3 P 1 1 3 P ≤ t _i <4 P

The conditions for hitting the value of t _i in one of the intervals indicated in Table 1 are determined by the values of the comparison signals “greater than or equal to” at the outputs of the comparison of the comparison circuits in accordance with Table 2.

Table 2.

t _i t _i ≥ P t _i ≥ 2 P t _i ≥ 3 P 0 ≤ t _i < P 0 0 0 P ≤ t _i <2 P 1 0 0 2 P ≤ t _i <3 P 1 1 0 3 P ≤ t _i <4 P 1 1 1

Thus, if the value of the comparison signals is equal to "1" at the comparison outputs of all three comparison circuits, thent _i (modP) =t _i - 3P, if the value of the comparison signals is equal to "1" at the comparison outputs of the two comparison circuits, thent _i (modP) =t _i - 2P, if the value of the comparison signal is equal to "1" at the comparison outputs of one comparison circuit, thent _i (modP) =t _i -P... If the value of the comparison signals is "0" at the comparison outputs of all three comparison circuits, thent _i (modP) =t _i , i.e. modulus subtraction operationP from the magnitudet _i not executed.

Figure 1 shows a diagram of a computing device.

The computing device contains ( n / 2-1) conversion stages, where n is the bit width of the input number, each of which contains adders 1 and multiplexers 2, three comparison circuits 3, three-input OR gate 4, two-input AND gate 5, input 6 of the binary code feed number A , output 7 of the binary code of the incomplete quotient Q and output 8 of the binary code of the remainder R of the number A. The binary code of the module is supplied to the first information inputs of the first comparison circuits 3 of all conversion stages, the binary code of the doubled module is supplied to the first information inputs of the second comparison circuits 3 of all conversion stages, the binary code of the triple unit is supplied to the first information inputs of the third comparison circuits 3 of all conversion stages. The outputs of the first, second and third comparison circuits 3 are connected, respectively, to the first, second and third control inputs of the multiplexer 2 and to the first, second and third inputs of the three-input OR element 4 of the corresponding conversion stages. The output of the OR element 4 of each conversion stage is connected to the first input of the two-input AND element 5 of the corresponding conversion stage. A logical unit is fed to the second input of the two-input element AND 5 of all conversion stages, the output of the two-input elements AND 5 of all conversion stages is connected to the transfer input of adders 1 of the corresponding conversion stage. At the first, second and third information inputs of multiplexers 2 of all conversion stages, respectively, inverse binary codes of the module, doubled module and tripled module are supplied. The first information outputs of the multiplexers 2 of all conversion stages are connected to the first information inputs of the adders 1 of the corresponding conversion stages, the j -th bits of the second information inputs of the adders 1 and the second information inputs of the comparison circuits 3 of the i -th conversion stage, where j = (0; 1), connected to the ( n -2 i - j -1) th bits of the binary code 6 of the input number, respectively. The second and third bits of the second information inputs of the adder 1 and the second information inputs of the comparison circuits 3 of the first conversion stage are connected to the ( n -2) th and ( n -1) th bits of the binary code 6 of the input number, respectively. The information outputs of the adders 1 of the i- th conversion stage, where i = 1, .., n / 2-2, are connected with a two-bit shift towards the higher ones with the second information inputs of the adders 1 and the second information inputs of the comparison circuits 3 ( i +1 ) of the th stage of transformation. The information output of the adder 1 ( n / 2-1) -th conversion stage is the output 8 of the binary code of the remainder. The second information outputs of the multiplexers 2 are the output 7 of the binary code of the partial private.

Figure 2 shows a diagram of multiplexers 2.

Multiplexers 2 contain three inverters 9, a three-input AND element 10, a two-input AND element 11, three switches 12, a block of OR elements 13 and two OR elements 14. The first input of a three-input AND element 10 is the first control input of multiplexer 2. The first input of a two-input AND element 11 is the second control input of the multiplexer 2 and is connected to the input of the first inverter 9, the output of which is connected to the second input of the three-input element AND 10. The control input of the third key 12 is the third control input of the multiplexer 2 and is connected to the input of the second inverter 9 and to the second inputs of the first and second OR elements 14, the outputs of which are the second information output of the multiplexer 2. The output of the second inverter 9 is connected to the third input of the three-input AND element 10 and to the second input of the two-input AND element 11, the output of which is connected to the control input of the second key 12 and to the first input of the second OR element 14. The output of the three-input element And 10 is connected to the first input th of the first OR element 14 and with the control input of the first key 12. The information inputs of the first, second and third keys 12 are the corresponding information inputs of the multiplexer 2, and the outputs are connected to the corresponding information inputs of the OR element block 13, the output of which is the first information output of the multiplexer 2.

The computing device operates as follows.

The binary code of the number A is fed to the input 6 of the device, from which it is necessary to form the remainder R and the incomplete quotient Q. The high-order bits of the number A are fed to the input of the first conversion stage, and the low-order ones are fed to the input of the last one.

The binary code of the P module is fed to the first information inputs of the first comparison circuits 3 of all conversion stages, the second comparison circuits 3 - the doubled binary code of the P module, the third comparison circuits 3 - the triple binary code of the P module.

The inverse binary code of the P module is fed to the first information inputs of the multiplexers 2 of all conversion stages, the double inverse binary code of the P module is fed to the second information inputs, and the triple inverse code of the P module is fed to the third information inputs.

The first stage computes the conversion value t = ₁ (February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4)) mod P. Wherein calculating values February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4) is carried out by supplying respective bits of a _{n -1} ... a _{n -4} to respective inputs of the first transformation stages. To bring this value modulo P using the comparison circuits 3, the values of P , 2 P and 3 P are simultaneously compared with the input value and, depending on the range of the input value, in accordance with table. 2, signals appear at the corresponding outputs "greater than or equal" of the comparison circuits 3, which are then fed to the corresponding control inputs of the multiplexer 2.

The control signals of the multiplexer 2 (see Fig. 2) open one of the keys 12.

If the control signal appears at all three control inputs, then the third key 12 will be open. The control signal from the third control input will open the third key 12 and, through the second inverter 9, it will be fed as a logical zero to the third input of the three-input element AND 10 and to the second input of the two-input element And 11, prohibiting the passage of control signals from their first inputs to their outputs. As a result, the first and second keys 12 will be closed and the output of the multiplexer 2 will receive the value of the inverse binary code of the triple module P from its third information input. The results at the output of the adder would be the value of 1 February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4) - 3 P.

If the control signal appears at the first and second control inputs of the multiplexer 2, then in the same way only the second key 12 will be open, and the first and third keys 12 will be closed. As a result, the output of the multiplexer 2 will receive the value of the inverse binary code of the doubled module P from its second information input. At the output of the adder would be the value of 1 2 ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4) - 2 P.

If the control signal appears only at the first control input of the multiplexer 2, then in the same way only the first key 12 will be open, and the second and third keys 12 will be closed. As a result, the output of the multiplexer 2 will receive the value of the inverse binary code of the module P from its first information input. At the output of the adder would be the value of 1 February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4) - P.

If there are only zero signals at the control inputs of the multiplexer 2, then all keys 12 will be closed and a zero value is formed at the output of the multiplexer 2. As a result, the output of the adder 1 will be the value 2 ² ( a _{n -1} · 2+ a _{n -2} ) + ( a _{n -3} · 2+ a _{n -4} ).

Formed in the first stage conversion value t = ₁ (February ² _{(a n -1 · 2+ a n} -2) + (a n -3 · 2+ a n -4)) mod P arrives shifted by two bits in the direction senior (ie actually carrying out multiplication by 2 ² ) at the input of the next transformation stage. Signals a _{n -5} , a _{n -6} bits of the input number A are applied to the least significant two bits.

In the second stage of the transformation, similar calculations are carried out. The device operates in a similar way at the rest of the conversion stages.

Since at each conversion stage, two bits of the input number are processed simultaneously, then through ( n / 2-1) transformations at the output 8 of the device, a binary code of the remainder R of the number A modulo P is formed , and at the output 7 of the device, a binary code of an incomplete quotient Q.

Let's consider the operation of a computing device using an example.

Let the input number A = 215 ₁₀ = 11010111 ₂ , module P = 6 ₁₀ = 00000110 ₂ , bit width n = 8. Binary direct and inverse codes of values of the modulus P , 2 P , 3 P are presented in table. 3.

Table 3.

Binary straight code Binary inverse code Module P = 6 00000110 11111001 2 P value = 12 00001100 11110011 3 P value = 18 00010010 11101101

The values of the signals during the operation of the device at the inputs and outputs of adders 1, multiplexers 2 and comparison circuits 3 are presented in table. 4. The number of the conversion stage is given in the first column of Table 4. "Comparison circuit 1", "Comparison circuit 2" and "Comparison circuit 3", respectively designation of the first, second and third comparison circuits 3. "Multiplexer inf" - designations of information inputs and outputs of multiplexers 2, "Multiplexer control" - designations of the control inputs of multiplexers 2. "Input 1" and "Input 2", respectively, the first and second information inputs of adders 1, multiplexers 2 and comparison circuits 3, as well as the first and second control inputs of multiplexers 2 "Input 3" - the transfer input of adders 1, as well as the third information and third control inputs of multiplexers 2. "Output 1" - information outputs of adders 1, multiplexers 2 and comparison circuits 3. "Output 2" - the second information output of multiplexers 2.

Table 4.

Art No. Enter exit Comparison circuit Multiplexer Adder 1 2 3 inf control 1 Entrance 1 00000110 00001100 00010010 11111001 1 11110011 Entrance 2 00001101 00001101 00001101 11110011 1 00001101 Entrance 3 - - - 11101101 0 1 Exit 1 1 1 0 11110011 - 00000001 Exit 2 - - - ten - - 2 Entrance 1 00000110 00001100 00010010 11111001 0 00000000 Entrance 2 00000101 00000101 00000101 11110011 0 00000101 Entrance 3 - - - 11101101 0 0 Exit 1 0 0 0 00000000 - 00000101 Exit 2 - - - 00 - - 3 Entrance 1 00000110 00001100 00010010 11111001 1 11101101 Entrance 2 00010111 00010111 00010111 11110011 1 00010111 Entrance 3 - - - 11101101 1 1 Exit 1 1 1 1 11101101 - 00000101 Exit 2 - - - eleven - -

As a result, at the information outputs of the adder 1 of the third transformation stage, which are the output 8 of the binary code of the remainder R of the number A of the device, the code of the number 00000101 ₂ = 5 _{10 is formed} , which is the calculated remainder R of the number A = 215 modulo P = 6, and on the outputs 7 of the device generate a binary code 100011 ₂ = 35 ₁₀ , which is an incomplete partial Q. By direct verification, we establish that 215 = 35 · 6 + 5, which proves the correct functioning of the device.

In the prototype device, the remainder is calculated in ( n -1) sequential transformation steps, and in the proposed device, in ( n / 2-1) steps. As a result, the speed of the proposed technical solution in comparison with the prototype device will be at least twice as high.

Claims (1)

A computing device for finding the remainder modulo and incomplete quotient, containing (n / 2-1) adders, (n / 2-1) multiplexers, where n is the bit width of the input number, n is even and more than 2, forming (n / 2- 1) conversion steps, input for feeding the binary code of a number, output of a binary code of an incomplete quotient, output of a binary code of the remainder of a number, characterized in that three comparison circuits, a three-input OR element and a two-input AND element, are additionally introduced into it at each conversion stage. the information inputs of the first comparison circuits of all conversion stages are fed the binary code of the module, the binary code of the doubled module is fed to the first information inputs of the second comparison circuits of all conversion stages, the binary code of the triple module is fed to the first information inputs of the third comparison circuits of all conversion stages, the outputs of the first, second and the third comparison circuits are connected respectively to the first, second and third control inputs of the multiplex ora and with the first, second and third inputs of the three-input element OR of the corresponding conversion stages, the output of the three-input element OR of each conversion stage is connected to the first input of the two-input element AND of the corresponding conversion stage, a logical unit is supplied to the second input of the two-input element AND of all conversion stages, the output of the two-input elements And all conversion stages are connected to the transfer input of the adders of the corresponding conversion stage, to the first, second and third information inputs of the multiplexers of all conversion stages, respectively, inverse binary codes of the module, doubled module and triple module are fed, the first information outputs of the multiplexers of all conversion stages are connected to the first information inputs adders of the corresponding conversion stages, the j-th bits of the second information inputs of the adders and the second information inputs of the comparison circuits of the i-th conversion stage, where j = (0; 1), are connected to the (n-2i-j-1) -th bits of the binary code of the input number, respectively, the second and third bits of the second information inputs of the adder and the second information inputs of the comparison circuits of the first conversion stage are connected to the (n-2) -th and (n-1) -th bits of the binary code of the input number, respectively, the information outputs of the adders of the i-th conversion stage, where i = 1, ..., n / 2-2, are connected with a two-bit shift towards the higher ones with the second information inputs of the adders and the second information inputs of the comparison circuits of the (i + 1) th conversion stage, the information output of the adder of the (n / 2-1) th conversion stage is the output of the binary code of the remainder, the second information outputs of the multiplexers are the output of the binary partial private code, and the multiplexer of each the conversion stage contains two inverters, a three-input AND element, a two-input AND element, three keys, a block of OR elements and two OR elements, and the first input of the three-input AND element is the first control input of the multiplexer, the first input of the two-input element And is the second control input of the multiplexer and is connected to the input of the first inverter, the output of which is connected to the second input of the three-input element AND, the control input of the third key is the third control input of the multiplexer and is connected to the input of the second inverter and to the second the inputs of the first and second OR elements, the outputs of which are the second information output of the multiplexer, the output of the second inverter is connected to the third input of the three-input AND element and to the second input of the two-input AND element, the output of which is connected to the control input of the second key and to the first input of the second OR element, the output of the three-input AND element is connected to the first input of the first OR element and to the control input of the first key, the information inputs of the first, second and third keys are the corresponding information inputs of the multiplexer, and the outputs are connected to the corresponding information inputs a block of OR elements, the output of which is the first information output of the multiplexer.

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