RU2720553C1 - Method of organizing a system network in the form of a fail-safe non-blocking three-dimensional sparse p-ary hypercube - Google Patents

Abstract

FIELD: methods of organizing a system network.

SUBSTANCE: invention relates to a method of arranging a system network in the form of a fail-safe non-blocking three-dimensional sparse p-ary hypercube for multiprocessor systems with hundreds of processors-subscribers. In the method, when constructing a network, the topology of a three-dimensional p-ary sparse hypercube is used, which is an originally organized three-dimensional composition of flat networks. At that, the method includes in a certain way organized arrangement of flat networks on facets of hypercube with further integration of commutators of these networks in nodes of hypercube, which together with additional channels between network nodes provides declared properties of invention.

EFFECT: high fault tolerance of the system network due to the presence of different direct channels between any processors.

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Description

The invention relates to the construction of fail-safe, non-blocking, self-routing system networks for multiprocessor systems with hundreds of processor subscribers.

Fault tolerance in the proposed network is ensured by the presence of several different direct channels between any processors. Non-blocking at arbitrary permutation of packets means the possibility of their parallel transmission from sources to receivers on direct channels (without buffering in intermediate nodes), which increases the system performance. Self-routing involves the possibility of laying paths locally over nodes without the latter interacting with each other.

The invention provides a method for organizing a fault-tolerant, non-blocking, self-routing system network in the form of a 3-dimensional sparse sparse hypercube based on networks with the topology of a p-quasicomplete graph providing channel fault tolerance. In the future, for simplicity of presentation, we will call the resulting network the abbreviation “Fail-safe, non-blocking three-dimensional sparse r-ical hypercube”.

The constructed non-blocking sparse hypercube can have several hundred subscribers (processor cores) with two to three different direct channels between them. The presence of several channels not only ensures the fault tolerance of this hypercube, but also opens up the possibility of further increasing its speed due to their parallel use.

Generalized r-dimensional p-egg hypercube (“Bhuyan LN and Agrawal DP Generalized Hypercube and Hyperbus Structures for a Computer Network // IEEE Trans, on Computers. - 1984. - Vol. C - 33. No 4. - P. 323- 333 ") with the degree of nodes m = rp and the number of nodes N = p ^{r is} used as a system network in some modern multiprocessor computing systems (" Alverson R., Froese E., Kaplan L., and Roweth D. Cray ^® XC ™ Series Network . - URL: https://www.cray.com/sites/default/files/resources/CrayXCNetwork.pdf (accessed October 10, 2018). ”However, these networks are not non-blocking.

Introduced in the work “Karavay M.F., Podlazov V.S. Distributed full switch as an “ideal” system network for multiprocessor computing systems // Management of large systems. - 2011. - Issue. 34. - S. 92-116 "networks have the property of non-blocking. These networks have the topology of a quasi-complete graph or digraph and have a quadratic dependence of the number of nodes on their degree (network nodes in these networks are formed by combining a processor with the same switch in one node). Self-routing in these networks is static, in which the route from any source to any receiver for arbitrary permutation of data packets between nodes is uniquely determined by the numbers of nodes and therefore any source independently paves the entire conflict-free path to a receiver for arbitrary permutation of data packets between nodes. The main drawback of these networks is the small number of nodes in them. Networks in the form of a 2-dimensional generalized hypercube and 2-dimensional complete multiring had the topology of a quasicomplete digraph, and networks called flat planes had the topology of a quasicomplex graph.

In the work “Podlazov B.C. Conflict-free self-routing for a three-dimensional generalized hypercube // Control Problems. - 2018. - No. 3. - S. 26-32. " On the basis of a 2-dimensional hypercube, a non-blocking 3-dimensional p-ary hypercube was built, for which an algorithm of dynamic local self-routing was proposed. It allows you to simultaneously run conflict-free paths for arbitrary rearrangement of data packets between nodes based on only local information in intermediate nodes without interaction between them. This network in the form of a non-blocking 3-dimensional p-ary hypercube, proposed in this paper, was selected as a prototype.

The main disadvantage of the network described in the prototype is that, being non-blocking and self-routing, it does not have channel fault tolerance.

An object of the invention is the development of such a method of organizing a 3-dimensional network, which would provide, along with the properties of non-blocking and self-routing, also a given channel fault tolerance in the form of several (σ) different direct transmission paths of packets between processors.

The technical result of the invention is the ability to achieve (σ-1) -fold channel fault tolerance of the system network.

The technical result is achieved by the fact that a new method for organizing a system network in the form of a fault-tolerant, non-blocking, self-routing three-dimensional p-ary sparse hypercube is proposed, characterized in that R = Np network nodes, numbered from 0 to Np-1 (0, 1, 2, ..., Np-1) have N nodes in the order of their numbering on the faces XY _k (1≤k≤p) of a 3-dimensional p-ary generalized hypercube,

and each group is divided into p groups g _i (1≤i≤p) with x nodes in the first group (i = 1) and for nodes in the remaining groups (i = 2, 3, ..., p) subject to the condition x + y (p-1) = N, after which each group g _i is located at the intersection of the face XY _k with the face XZ _j (1≤j≤р), the number of which is calculated by the formula j = mod _p (i + k-1),

wherein each network node includes a processor and a switch connected by a duplex line, for communication with other network nodes in the processor organize groups OI _XY , OI _XZ on (p-1) duplex ports and group S _YZ from (p-1) simplex outputs, and in the switch, OI _XY , OI _XZ , M _YZ , D _YZ , C _YZ , I _{XZ groups} of (p-1) duplex ports and S _YZ group of (p-1) simplex inputs of the input ports are organized,

at the same time, (p-1) duplex ports OI _{XY of} each of the N switch faces XY _{k are} connected one by one (p-1) with duplex lines with (p-1) ports of different (p-1) processors of the same face, and similarly (p -1) the duplex ports OI _{XZ of} each of the N face switch XZ _{j are} connected one by one (p-1) with duplex lines with (p-1) ports of different (p-1) processors of the same face in accordance with the connection diagram of N switches and N processors obtained from an incomplete symmetric block diagram by replacing blocks with switches, elements with processors, incidence of blocks, and elements with connecting switches and processors and having the form of a table of N rows and p + 1 columns, each row of which contains the number of one switch and the number p of processors connected to it, and according to which p different processors are connected to each switch, and each processor is connected to p different switches, and each pair of processors is connected to σ different switches so that N = p (p-1) / σ + 1 , and σ defines the number of different paths between any two processors through different switches,

or in accordance with the connection diagram of N ^* switches and N ^* processors, obtained similarly from the extended block diagram in the form of a table of N ^* rows and p + 1 columns, and according to which p different processors are connected to each switch, and each processor is connected to p different switches, and each pair of processors is connected to σ or to σ + 1 different switches so that N ^* <p (p-1) / σ + 1, and σ or σ + 1 specify the number of different paths between any two processors through different switches

(p-1) ports of the groups of the same name M _YZ , D _YZ , C _YZ commutators located on p different faces XZ _j (1≤j≤p) at nodes that have equal numbers N modulo, i.e., n _a ≡n _b ( mod N) and n _a , n _b ∈ [0, Np-1], are connected by groups of (p-1) duplex lines, that is, each pair of switches in the same group is connected by a duplex line;

(p-1) duplex ports of the group I _XZ switches are connected by duplex lines parallel to the lines between nodes that are connected by OI _XZ lines,

and (p-1) the simplex outputs of the switches of the group S _{YZ are} connected to the simplex inputs of the processors parallel to the lines between nodes that are connected by lines of the group M _YZ ;

at the same time, inside each switch, for routing, full-switch communications are organized from the inputs O _XY to the outputs I _XY , I _XZ , M _YZ , D _YZ (O _XY and I _XY are the inputs and outputs of the duplex ports OI _XY , I _XZ are the outputs of the duplex ports OI _XZ ), from inputs M _YZ to outputs I _XZ , from inputs D _YZ to outputs C _YZ , from inputs C _YZ to outputs I _XZ , from inputs I _XZ to outputs S _YZ ,

moreover, ports and lines identical to them in the named groups are numbered from 1 to p-1 (1, 2, ..., p-1) (number 0 indicates intra-node communication in groups O _XY , O _XZ or lack of communication in group M _YZ ) and are set during routing in the group O _{XY by} numbers m ₁ (0≤m ₁ ≤р-1), in groups I _XZ and I _{XZ by} numbers m ₃ (0≤m ₃ ≤р-1), in the group M _{YZ by} numbers m ₂ (0≤m ₂ ≤р-1), in the group D _{YZ with} numbers m ^* ₂ (0≤m ^* ₂ ≤р-1), in groups C _YZ and S _{YZ with} numbers m ^* ₃ (0≤m ^* ₃ ≤р -1), (numbers m ₂ , m ^* ₂ , m ^* ₃ = ji if (ji) ≥0, and m ₂ , m ^* ₂ , m ^* ₃ = p + ji if (ji) <0), i and j are the numbers of XZ faces on which the source node and the receiver node are located),

and the establishment of direct paths during routing is carried out by the wormhole method using node switches independently of each other, taking into account the parameters of the routes given by the numbers m ₁ , m ₂ , m ₃ , m ^* ₂ = m ₁ , m ^* ₃ = ⏐ m ₂ -m ^* ₂ ⏐ in the headers of the pilot packets received by the switches and the presence of conflicts on the lines of the groups M _YZ and C _YZ as follows:

the parameters of the shortest route m ₁ , m ₂ , m ₃ in the header of the pilot packet generated by the processor, in the absence of conflicts, specify three stages of laying the direct path by the packet, namely, from the source node on the O _XY (m ₁ ) line to the next network node ( when m ₁ = 0, the path is laid to the switch of the source node), the switch of which sets the path along the line M _YZ (m ₂ ) to the next network node (when m ₂ = 0 there is no second stage), the switch of which sets the path along the line I _XZ (m ₃ ) to the receiving node (with m ₃ = 0, the receiving node is in the same node as the switch),

if the switch detects a conflict during the transmission of the pilot packet to the line M _YZ (m ₂ ), then paves the way to line D _YZ (m ^* ₂ ),

if the switch receives a pilot packet on the D _YZ line (m ^* ₂ ) and does not detect a conflict on the C _YZ line (m ^* ₃ ), then it paves the way to this line, or if a conflict is detected, paves the way on the I _XZ line (m ₃ ),

if the switch receives a pilot packet on line C _YZ (m ^* ₃ ), it paves the way on line I _XZ (m ₃ ), and if the switch receives a pilot packet on line I _XZ (m ₃ ), it paves the way on line S _YZ ( m ^* ₃ ).

The technical nature and principle of operation of the proposed network are illustrated by drawings.

In FIG. Figure 1 shows a quasi-complete graph with N = 7, p = 4, and σ = 2 (squares are commutators).

In FIG. Table 2 shows the connection diagrams for two quasi-complete graphs with N = 7, p = 4, σ = 1 and N = 7, p = 4, σ = 2

In FIG. Figure 3 shows the non-blocking flat networks PS (7, 3, 1) and PS (7, 4, 2).

In FIG. Figure 4 shows Table 2 of the parameters of the flowcharts BD (N, p, σ) for small values of p and σ.

In FIG. Figure 5 shows Table 3 of the parameters of the BD (N, p, σ) flowcharts and 1-extended BD (N ^* , p, σ | σ + 1) flowcharts for small values of p and σ.

In FIG. Figure 6 shows a 3-dimensional non-blocking hypercube and an example of a non-blocking route in it from node 10 to node 26.

In FIG. Figure 7 shows a sparse ternary hypercube of flat networks on the planes XY _i and XZ _j .

In FIG. 8 and FIG. Fig. 9 shows Tables 4 and 5 of the arrangement of flat networks PS (7, 3, 1) and PS (7, 3, 2) along the planes XY and XZ of a sparse hypercube.

In FIG. 10 and FIG. 11 are shown respectively Tables 6 and 7 of the placement by groups for flat networks isomorphic to PS (N, p, 2) and PS (N p, 3).

In FIG. Figure 12 shows the structure of the commutator of a sparse hypercube node at the intersection of the XY and XZ planes.

In FIG. 13 shows the structure of a ternary sparse hypercube with secant ribs M _YZ and an example of a 3-stage route in it.

In FIG. 14 and in FIG. Figure 15 shows the structure of the node switches in a sparse fail-safe hypercube and the structure of the node switches in a sparse fail-safe non-blocking hypercube.

In FIG. Figure 16 shows the graph of the path in a sparse fail-safe, non-blocking hypercube.

In FIG. 17 and in FIG. Figure 18 shows, respectively, illustrations of conflicts of the first and second types and their resolution.

In FIG. Table 8 shows the number of nodes R (p, σ) in 3-dimensional sparse hypercubes.

We describe a method for organizing the proposed system network.

We first consider the networks that we will use to construct from them 3-dimensional sparse p-ary hypercubes. In chapter 2.3 of the work “Karavay MF, Podlazov B.C. Distributed full switch as an “ideal” system network for multiprocessor computing systems // Management of large systems. - 2011. - Issue. 34. - S. 92-116 ”networks are proposed whose connection diagrams are a special bipartite graph, one part of which is made up of switches, and the other part is processors. The number of vertices in each lobe is N, and the degree of all vertices in each lobe is the same and equal to p. The value of p is chosen to be the minimum at which any two nodes in one lobe are connected and paths of length two through different nodes in another lobe. Each such path goes through one switch, and different paths go through different switches. We call a bipartite homogeneous graph with the described properties a minimal quasi-complete graph (Karavay MF, Parkhomenko PP, Podlazov BC Combinatorial methods for constructing bipartite homogeneous minimal quasi-complete graphs (symmetric flowcharts) // Autom. - 2009. - № 2. - S. 153-170 "). An example of such a graph is shown in FIG. 1 for p = 4, N = 7, and σ = 2. It is easy to see that each pair of subscribers is connected in two ways through different switches. This raises the question of the existence, finding of minimal quasi-complete graphs and their parameters.

It turns out that he has long been resolved in combinatorics. Such graphs are described in the language of incomplete balanced flowcharts, in particular, symmetric flowcharts ("Hall M. Combinatorics // Chapters 10-12. World. M. 1970. 424 S."). The symmetric block diagram BD (N, p, σ) defines the placement of N elements in N blocks, in which each block contains p different elements, each element is contained in p different blocks, and each pair of elements is contained in p different blocks and the equality N = p (p-1) / σ + 1. Replacing blocks with switches, elements with processors, incidence of blocks and elements with connections between switches and processors, we get a minimal quasi-complete graph. The connection diagrams thus obtained from symmetric block diagrams coincide with the connection diagrams of quasi-complete graphs and are presented in Table. 1 in FIG. 2. Table 1 with connection diagrams for two quasi-complete graphs with N = 7, p = 4, σ = 1 and N = 7, p = 4, σ = 2. In each row, the first cell specifies the number of the switch, and the remaining cells - the numbers of processors associated with this switch edge in the form of a duplex channel (two counter simplex channels).

If we combine the switch of the same name with the processor of a quasi-complete graph in one network node, then we get a flat network PS (N, p, σ). It is a non-blocking network with conflict-free static self-routing and has (σ-1) -channel fault tolerance for σ> 1. In FIG. Figure 3 shows the non-blocking networks of PS (7, 3, 1) and PS (7, 4, 2).

Self-routing in HC (N, p, σ). carried out according to the connection diagram (table. 1) using the node numbers of the subscriber-source and subscriber-receiver. The table contains the numbers of the switches connected by duplex channels to the subscriber-receivers. Among these switches are one that is connected in the same channel to the subscriber source. By the properties of quasi-complete graphs of such commutators, σ.

However, symmetric block diagrams of BD (N, p, σ) exist and, moreover, are not constructed for all values of the parameters p and σ. In the table. 2 in FIG. 4 shows the values of N for block diagrams at small values of these parameters. Empty cells mark flowcharts that do not exist by definition. Dashes in cells indicate flowcharts that cannot exist in theory, and crossed out values indicate flowcharts that have not yet been constructed.

The need to build fault-tolerant networks PS (N, p, σ) requires some effective filling of empty cells in the table. 2. For this, in the work “Karavay MF, Podlazov BC Extended block diagrams for ideal system networks // Control Problems. - 2012. - No. 4. - S. 45-51. " 1-extended block diagrams BD (N ^* , p, σ | σ + 1) were proposed and constructed, defining connection tables for 1-extended flat PS networks (N *, p, σ | σ + 1), in which the Some of the subscribers are connected by σ + 1 in different ways, and the rest are exactly σ in different ways. The values N and N ^{* of the} number of nodes in the above block diagrams are given in table. 3 in FIG. 5, where the latter are underlined.

Now we show how to build a three-dimensional sparse hypercube from these fault-tolerant non-blocking self-routing flat networks. Recall that in the non-blocking 3-dimensional p-ary hypercube proposed in the prototype, a non-blocking straight path can be laid between two vertices. However, this path is unique and has no backup paths. In FIG. Figure 6 shows a 3D hypercube and an example of such an unblockable route from node 10 to node 26 in it. The initial stage of the route is a simplex channel on the XY ₂ edge parallel to the X axis from the node 10 processor to the node 11 switch, and the second stage is a simplex channel on the edge XY ₂ parallel to the Y axis from the switch of the node 11 to the switch of the node 17 and the final step is the simplex channel on the edge XZ ₃ parallel to the Z axis from the switch of the node 17 to the processor of the node 26, abbreviated 10 → 11 → 17 → 26.

In the proposed method of organizing a fault-tolerant non-blocking network in the form of a self-routing sparse 3-dimensional p-ary hypercube, the following fragments can be distinguished:

- placement of fault-tolerant flat networks on the XY and XZ faces of a 3D hypercube so that the identical local node numbers of the flat networks of XY and XZ faces coincide at the intersection of the faces, combining identical switches in the nodes,

- the introduction of additional lines between the XZ face commutators with identical local node numbers to ensure fully connected nodes of the sparse hypercube,

- the introduction of additional lines in a sparse fault-tolerant 3-dimensional hypercube to ensure non-blocking of the resulting network.

We demonstrate the proposed method by the example of constructing a 3-dimensional hypercube from flat PS networks (7, 3, 1) without loss of generality.

Let us build a network with R = Np nodes. We number them from 0 to Np-1 (0, 1, 2, ..., Np-1) and arrange them in N nodes in ascending order on the vertical faces XY _k (1≤k≤p) of a 3-dimensional p-ary generalized hypercube. So in FIG. Figure 7 shows a sparse ternary hypercube with planar networks located on the XY _i and XZ _j planes (connections in planar networks are not shown, but they are such as in Fig. 3).

In the obtained sparse hypercube, in addition to the general numbering of nodes, we introduce the values of these numbers by mod N. The numbers obtained mean the numbering of nodes within each face and are shown in FIG. 7 in brackets. Note that on all faces XY and XZ, as a result, we received N nodes each, numbered from 0 to N. We will call this numbering, in contrast to the general, local.

It can be seen that the nodes from the 0th to the 6th are located on the vertical XY ₁ face, the nodes from the 7th to the 13th on the XY ₂ face, the nodes from the 14th to the 20th on the XY ₃ face. Moreover, each series of N nodes is distributed over the horizontal faces XZj (1≤j≤p) in a certain way. So in FIG. Figure 7 shows that the nodes of the XY ₁ face are distributed along the horizontal faces as follows: nodes 0, 1, 2 on the XZ ₁ face, nodes 3, 4 on the XZ ₂ face, nodes 5, 6 on the XZ ₃ face, and each next series of N nodes are distributed along horizontal faces similarly to the previous one, but with a cyclic shift by one horizontal face up. In general terms, the method of partitioning along horizontal faces is formulated as follows: each series of N nodes is divided into p groups g _i (1≤i≤p) with x nodes in the first group (i = 1) and by nodes in the remaining groups (i = 2 , 3, ..., p) subject to the condition x + y (p-1) = N, after which each group g _i is located at the intersection of the face XY _k with the face XZ _j (1≤j≤p), the number of which is calculated by the formula j = mod _p (i + k-1). Such a partition into groups g _i (1≤i≤р), defined by a pair (x, y) is called d partition.

An example of such an arrangement of PS nodes (7, 3, 1) along the XY and XZ planes in relation to the local numbers (LN) specified by the d partition (3, 2) is presented in Table 4 in FIG. 8 (in the general case d, the partition is defined by the pair (p, p-1)). An example of a similar arrangement for PS (7, 4, 2) defined by d by partition (1, 2) is presented in Table 5 in FIG. 9.

The partitioning of d into groups for the remaining PS networks (N, p, 2) is presented in Table 6 in FIG. 10, and for PS networks (N, p, 3) in table 7 in FIG. eleven.

We got a sparse hypercube in which identical local numbers of N nodes of networks of different faces coincide. Recall that in the rarefied hypercube of FIG. 7, a flat PS network is used (7, 3, 1), in the general case, the nodes on each face are nodes of a flat PS network (N, p, σ) (or an extended flat PS network (N *, p, σ | σ + 1) ) with σ | σ + 1 in different ways.

Each switch of a flat network on XY faces also belongs to a certain flat network on XZ faces. These switches provide paths between source and destination subscribers on these faces. The named paths consist of two arcs - the output arc Oxy on the XY edge from the source subscriber to the switch and either the input arc I _XY from the switch to the destination subscriber on the same XY edge, or the input arc I _XZ to the destination subscriber on the XZ edges ( 12).

However, the constructed sparse fail-safe hypercube is not fully connected, because there are no paths between part of the subscribers who are in different vertical and horizontal planes, for example, between subscribers 0 and 11 or 0 and 16 in FIG. 7.

To ensure full connectivity, we additionally lay edges between the nodes of the XY and XZ planes, which have the same local number as is done in FIG. 13. We call such edges secant M _YZ , because they intersect the planes XY and XZ. They also form a complete graph between nodes with identical local numbers, that is, the numbers n _a ≡n _b (mod N), where n _a , n _b ∈ [0, Np-1],

In this case, duplex channels corresponding to secant edges are laid only between the node switches.

Now, any shortest path that is not covered by flat networks XY and XZ can be represented as a three-stage one consisting of lines of the groups O _XY , M _YZ, and I _XZ . Let the node of the subscriber-source is on the verge XY _i ,, and the node of the subscriber-receiver is on the verge XZ _j . The first line O _XY is located on the XY _i edge and passes from the source subscriber to the switch of the first intermediate node located on the XY _i edge and the XZ _k edge. The second edge M _YZ extends from the edge XZ _k to the edge XZ _j - from the switch of the first intermediate node to the switch of the second intermediate node. The third line I _XZ is on the verge XZ _j and passes from the switch of the second intermediate node to the subscriber-receiver.

где значки в скобках указывают номера портов коммутаторов узлов 0, 3 и 10, к которым подсоединены одноименные линии. Для плоских сетей с σ>1 и выше в гиперкубе аналогично будут проложены резервные параллельные пути с использованием резервных путей содержащихся в исходных плоских сетях.Let us consider an example of a route in a rarefied hypercube constructed on the basis of a substation (7, 3, 1) (Table 1 and Fig. 2). Let the nodes of the subscriber-source and subscriber-receiver have numbers 0 and 16 (2). They lie on different faces - XY ₁ and XZ _3, respectively. A three-arc path, an example of which is shown in FIG. 13 to the right, contains a line from the processor in node 0 to the switch in node 3 in a flat network of a PS (7, 3, 1) of the XY ₁ face, then a line of the cutting edge between the switches in nodes 3 and 10 (3) and a line from the switch in the node 10 (3) to the receiver at node 16 (2) of the flat network of the PS (7, 3, 1) of the XZ ₃ face. Abbreviated this route we write in the form of a chain of nodes 0 → 3 → 10 (3) → 16 (2) or a chain of lines

where the icons in brackets indicate the port numbers of the switch nodes 0, 3, and 10 to which the lines of the same name are connected. For planar networks with σ> 1 and higher in the hypercube, parallel backup paths using the backup paths contained in the original planar networks will be similarly laid.

In order to maintain the possibility of constructing such 3-stage routes to the switch, in addition to the above-described connections shown in FIG. 12, additional communications are introduced from the Oxy line from subscribers to the M _YZ line to the switches and from the M _YZ line from the switches to the I _XZ line to the subscribers, as shown in FIG. 14.

Thus, a fault-tolerant network is constructed in the form of a 3-dimensional fully-connected rarefied hypercube. However, in such a network, conflicts can occur during arbitrary rearrangement of data packets between nodes. To ensure non-blocking, additional groups of D _YZ , C _YZ , M _YZ , S _YZ , I _XZ no p-1 lines and corresponding additional ports and switching lines are introduced into the structure of the switch, as shown in FIG. 15. The lines of the groups D _YZ , C _YZ , in the hypercube are laid between the switches parallel to M _YZ , the lines of the groups S _{YZ are} laid between the same nodes as M _YZ , but from the switches to the subscribers. The lines of I _XZ groups are laid between the same nodes as the I _XZ lines, but between the node switches. We show that these additions provide the required non-blocking.

In FIG. Figure 16 shows the route graph in the resulting network, demonstrating the operation of the node switches when laying non-blocking 3-stage paths taking into account possible conflicts using the wormhole method. To lay a direct route from node s to node d, the pilot packet must contain five numbers m ₁ , m ₂ , m ₃ , and m ^* ₂ , m ^* ₃ , where m ^* ₂ = m ₁ and m ^* ₃ = ⏐m ₂ -m ^* ₂ ⏐. The numbers indicate the port numbers of the switches and the matching line numbers in the groups that the switches will use in self-routing, and are calculated by each source in advance. In FIG. 16, one can trace the laying of 3 options of paths: 1) in the absence of conflicts, 2) in the event of a conflict of the first kind on the line M _YZ (m ₂ ), 3) in the case of a conflict of the first kind on the line M _YZ (m ₂ ) and the second kind on line C _YZ (m ^* ₃ ).

Во втором случае прокладывается обходной путь с использованием линий D_YZ(m^* ₂) и C_YZ(m^* ₃), а именно, s→t→h→i→d и

В третьем случае прокладывается обходной путь с использованием линий D_YZ(m^* ₂), I _XZ(m₃) и S_YZ(m^* ₃), а именно, s→t→h→e→d и

In the first case, the switches pave the path given by three numbers m ₁ , m ₂ , m ₃ , which we write in the form of a sequence of nodes and lines, respectively, s → t → i → d and

In the second case, a workaround is made using the lines D _YZ (m ^* ₂ ) and C _YZ (m ^* ₃ ), namely, s → t → h → i → d and

In the third case, a workaround is made using the lines D _YZ (m ^* ₂ ), I _XZ (m ₃ ) and S _YZ (m ^* ₃ ), namely, s → t → h → e → d and

Let us consider in more detail the causes of conflicts and ways to overcome them.

We will set the lines O _XY , M _YZ, and I _XZ with the port numbers m1, m2, and m3 (0≤m1, m2, m3≤р-1) from which they exit. For M _YZ lines, these ports are numbered in ascending order of line lengths, defined as follows. Let the line M _YZ pass from the plane XZ _i to the plane XZ _j , then its length L (i, j) = ji if (ji) ≥0, and L (i, j) = p + ji if (ji) < 0. The ports of the group of lines D _YZ , C _YZ, and S _YZ are numbered the same as M _YZ , and the lines O _XY and I _{XZ in the} same way for all ports from which they exit. The lines I _XZ (m ₃ ) are numbered similarly to the lines I _XZ (m ₃ ).

A situation in which several paths claim one second line M _YZ is considered a conflict of the first type. Such a conflict occurs if several paths claim to pass through node t (Fig. 17) from different source nodes s and s ^* . Hereinafter, for brevity, we denote only two such nodes, which in fact can be any number from 2 to p-1. In FIG. 17, the conflict line is indicated by a bold dotted line.

The conflict resolution is carried out as follows: on deliberately different lines D _YZ , determined for each pilot packet by its parameter m ^* ₂ = m ₁ , paths to different bypass nodes h and h ^{* are} laid from node t (Fig. 17) and return from them to node i along the oncoming lines C _YZ . If there are no conflicts on the C _YZ lines, the paved paths are conflict-free. They will remain conflict free on the last lines I _XZ from the switch of node i to the receivers in nodes d and d ^* . Lines D _YZ are obviously different, because they go from the same port numbers as the lines O _XY from nodes s and s ^* to node t. Different and return lines C _YZ . Let the conflicting line M _YZ from node t to node i leave the port with the number m ₂ , and the line D _YZ from the port with the number m ^* ₂ . Then, as the return line from node h to node i, line C _YZ with number m ^* ₃ = ⏐m ₂ -m ^* ₂ ⏐ is selected. Such a line will always be found, because lines C _YZ form a complete graph.

However, conflicts of the second type may also arise on the C _YZ lines. Each of them occurs if several paths from different nodes t and t ^* pretend to pass through node i in the second stage after the first stage (Fig. 18) and after a conflict of the first type occurs.

The conflict of the second type is resolved as follows (Fig. 18). From the intermediate node h, the paths are laid to bypass nodes e and e ^* along those lines I _XZ that have the same numbers m ₃ with lines I _XZ from node i to the receivers of nodes d and d ^*, respectively. All these lines I _{XZ are} different, because they complete the direct paths from node i. Therefore, the lines I _{XZ are} also different, and the paths are laid in different bypass nodes e and e ^* , from which they end without conflict on different lines S _YZ , but laid from the switches to the subscribers. This is clearly shown in FIG. sixteen.

As an illustration explaining the operation of the resulting network, we present the Dynamic Self-Routing Algorithm, which draws a direct path using the wormhole routing method.

1. If m ₁ = 0, then the path is laid along the local line in the node of the subscriber-source to the switch. Go to step 3.

If m ₁ > 0, then the path is laid from the subscriber-source on the line О _ХУ (m ₁ ). Go to step 2.

2. If m ₂ = 0 and m ₃ = 0, then the path is laid along the local line in the node of the subscriber-receiver from the switch to the subscriber. The end of the algorithm.

3. If m ₂ = 0 and m ₃ ≠ 0, then the path is laid along line I _XZ (m ₃ ) to the subscriber-receiver. The end of the algorithm.

If m ₂ ≠ 0 and m ₃ = 0, then the path is laid along the line M _YZ (m ₂ ) to the switch node of the subscriber-receiver and through a local line to the subscriber-receiver. The end of the algorithm.

If m ₂ > 0, then the presence of a conflict on the line M _YZ (m ₂ ) is checked. If there is no conflict, then the path is laid along this line M _YZ (m ₂ ). Go to step 4.

If m ₂ > 0 and there is a conflict, then the path is laid along the line D _YZ (m ^* ₂ ). Go to step 5.

4. The path is laid on line I _XZ (m ₃ ) to the subscriber-receiver. The end of the algorithm.

5. The path conflict along the line C _YZ (m ^* ₃ ) is checked.

If there is no conflict, then the path is laid along the line C _YZ (m ^* ₃ ). Go to step 4.

If the conflict takes place, then go to paragraph 6.

6. The path is laid along line I _XZ (m ₃ ). Go to step 7.

7. The path is laid along the line S _YZ (m ^* ₃ ). The end of the algorithm.

Note that the laying of direct paths according to the above algorithm can contain up to four stages. However, the transmission of all data packets on direct paths is carried out in one hop. The latter property allows us to state that the resulting network practically (in terms of transmission delays) has a unit diameter.

A new network is proposed in the form of a three-dimensional non-blocking fault-tolerant hypercube based on flat networks with the topology of a quasi-complete graph. This hypercube is called a sparse p-egg hypercube, because it contains fewer nodes than the non-blocking 3-dimensional p-ary hypercube used in the prototype, but allows exchanging the number of nodes by the number of different channels between them, which ensures its channel fault tolerance. Data transmission in the proposed network is carried out through direct channels between subscribers, which ensures its greatest performance. The intra-node switch in the resulting network has 9/8 more ports than in the non-blocking hypercube or multi-ring.

The constructed network can have several hundred subscribers (processor cores) with two or three different direct channels between them. The presence of several channels not only ensures the fault tolerance of this network, but also opens up the possibility of further increasing its speed due to their parallel use.

The field of applicability of this sparse hypercube is a system network in a multi-core single-chip processor accelerator.

In FIG. 18 in the table. Figure 8 shows the number of nodes R (p, σ) in the constructed 3-dimensional sparse hypercubes that determine the topology of the networks obtained by the proposed method. In it, the underlined values refer to hypercubes sharpened on 1-extended flat HC networks (N ^* , p, σ | σ + 1) in which N ^* <N. The remaining values are given by the formula R (p, σ) = N (p, σ) p, i.e. R (p, 1) = p ² p ³ + p, R (p, 2) = p ^{3/2 P-2/2} + p and R (p, 3) = r ^{3/3-p 2/3} + p.

Claims (1)

A method of constructing a system network in the form of a fault-tolerant non-blocking three-dimensional sparse hypercube, characterized in that R = Np network nodes, numbered from 0 to Np-1 (0, 1, 2, ..., Np-1), have N nodes in the order of numbering on the faces XY _k (1≤k≤p) of a three-dimensional p-ary generalized hypercube, and each group is divided into p groups g _i (1≤i≤p) with x nodes in the first group (i = 1) and nodes in other groups (i = 2, 3, ..., p) subject to the condition x + y (p-1) = N, after which each group g _i is located at the intersection of the face XY _k with the face XZ _j (1≤j≤р ), the number of which is calculated by the formula j = mod _p (i + k-1), while each network node includes a processor and a switch connected by a duplex line, groups OI _XY , OI _{XZ are} organized in the processor to communicate with other network nodes by ( p-1) duplex ports and the S _YZ group of (p-1) simplex outputs, and in the switch groups OI _XY , OI _XZ , M _YZ , D _YZ , C _YZ , I _{XZ are} organized by (p-1) duplex ports and the group S _YZ from (p-1) simple of the input port inputs, while the (p-1) duplex ports OI _{XY of} each of the N switch faces XY _{k are} connected one at a time by duplex lines with (p-1) ports of different (p-1) processors of the same face, and similarly (p -1) duplex ports OI _{XZ of} each of the N switch faces XZ _j connect one (p-1) duplex lines with (p-1) ports of different (p-1) processors of the same face in accordance with the connection diagram of N switches and N processors obtained from an incomplete symmetric block diagram by replacing blocks with switches, elements with processors, incidence of blocks and elements with connections between switches and processors and having the form of a table of N rows and p + 1 columns, each row of which contains the number of one switch and the number p processors connected to it, and according to which p different processors are connected to each switch, and each processor is connected to p different switches, and each pair of processors is connected to σ different switches so that N = p (p-1) / σ + 1, and σ sets the number of different paths between any two processors through different switches, or in accordance with the connection scheme of N ^* switches and N ^* processors, obtained similarly from the extended block diagram in the form of a table of N ^* rows and p + 1 columns, and according to which p different processors are connected to each switch, and each processor is connected to p different switches, and each pair of processors is connected to σ or to σ + 1 different switches so that N ^* <p (p-1) / σ + 1, and styles σ + 1 specify the number of different paths between any two processors through different switches; ports of the groups of the same name M _YZ , D _YZ , C _YZ switches located on p different faces XZ _j (1≤j≤p) at nodes that have equal numbers N modulo, that is, n _a ≡n _b (mod N) and n _a , n _b ∈ [0, Np-1], are connected by groups of (p-1) duplex lines, that is, each pair of switches in the same group is connected by a duplex line; the (p-1) duplex ports of the switches of group I _{XZ are} connected by duplex lines parallel to the lines between the nodes that are connected by OI _XZ lines, and (p-1) the simplex outputs of the switches of the group S _{YZ are} connected to the simplex inputs of the processors parallel to the lines between nodes that are connected by the lines groups M _YZ ; in this case, inside each switch, for routing, full-switch communications are organized from the Oxy inputs to the outputs I _XY , I _XZ , M _YZ , D _YZ (O _XY and I _XY are the inputs and outputs of the duplex ports OI _XY , I _XZ are the outputs of the duplex ports OI _XZ ) , from the inputs M _YZ to the outputs I _XZ , from the inputs D _YZ to the outputs C _YZ , from the inputs C _YZ to the outputs I _XZ , from the inputs I _XZ to the outputs S _YZ , and the ports and identical lines in these groups are numbered from 1 to p-1 (1, 2, ..., p-1) (number 0 indicates intra-site communication in groups O _XY , O _XZ or lack of communication in group M _YZ ) and are specified during routing in group O _{XY by} numbers m1 (0≤ m ₁ ≤р-1), in groups I _XZ and I _{XZ with} numbers m ₃ (0≤m ₃ ≤р-1), in group M _{YZ with} numbers m ₂ (0≤m ₂ ≤р-1), in group D _{YZ with} numbers m * ₂ (0≤m * ₂ ≤р-1), in groups C _YZ and S _{YZ with} numbers m * ₃ (0≤m * ₃ ≤р-1), (numbers m ₂ , m * ₂ , m * ₃ = ji if (ji) ≥0, and m ₂ , m * ₂ , m * ₃ = p + ji if (ji) <0), i and j are the numbers of XZ faces on which the source node is located and the receiving node), and the establishment of direct n During routing, wormholes are carried out by means of wormholes through node switches, independently of each other, taking into account the parameters of the routes given by the numbers m ₁ , m ₂ , m ₃ , m * ₂ = m ₁ , m * ₃ = ⏐ m ₂ -m * ₂ ⏐ the pilot packets received by the switches and the presence of conflicts on the lines of the groups M _YZ and C _YZ as follows: the shortest route parameters m ₁ , m ₂ , m ₃ in the header of the pilot packet generated by the processor, in the absence of conflicts specify three stages of laying the direct path with the packet, namely, from the source node on the O _XY line (m ₁ ) to the next network node (with m ₁ = 0, the path is laid to the switch of the source node), the switch of which sets the path along the M _YZ line (m ₂ ) to the next network node ( when m ₂ = 0, the second stage is absent), the switch of which sets the path on the I _XZ line (m ₃ ) to the receiver node (when m ₃ = 0, the receiver node is in the same node as the switch), if the switch detects a conflict when transmitting a pilot packet to line M _YZ (m ₂ ), then paves the way to line D _YZ (m ^* ₂ ), if the switch receives a pilot packet on the line D _YZ (m ^* ₂ ) and does not detect a conflict on line C _YZ (m ^* ₃ ), then paves the way to this line, or if a conflict is detected, it paves the way to line I _XZ (m ₃ ), if the switch receives a pilot packet on line C _YZ (m ^* ₃ ), then it paves the way to line I _XZ (m ₃ ), and if the switch receives a pilot packet on line I _XZ (m ₃ ), then paves the way to the line S _YZ (m ^* ₃ ).

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