RU2643622C1 - Computer module - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device contains an interface unit, a task separation unit, a task header memory unit, a task data memory unit, a task arbiter, a computational field from a group of N computing cores 6₁, …, 6_N, a group of N memory units of the computing core task numbers 7₁, …, 7_N, a multiplexer result unit, a result arbiter, a result header memory unit, a result data memory unit, an external interface, wherein each computational core 6₁, …, 6_N consists of input buffer memory 6-1, an operation unit 6-2, output buffer memory 6-3, and a control unit 6-4.

EFFECT: increasing the performance of the computational module.

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Description

FIELD OF TECHNOLOGY

The invention relates to the field of computing, in particular to high-performance computing devices for solving labor-intensive tasks using parallelization according to many independent subtasks.

BACKGROUND OF THE INVENTION

A known adaptive data processing system (RU No. 105487 U1, IPC G06F 15/16, application form 25.02.2011, publ. 06/10/2011, BI No. 16), containing N processing lines consisting of M _n processing modules, M _n selection blocks channels and output signal transmission line, application memory block, register for setting operating modes of processing modules, multiplexer / demultiplexer of output lines, N address decoders, priority encoder.

A disadvantage of the known system is the large amount of hardware and the complex structure of parallelizing the flow of applications of the system.

A well-known basic module of a multiprocessor computing system (RU No. 86332 U1, IPC G06F 15/16, stated May 21, 2009, published August 27, 2009, BI No. 24), comprising a computing field consisting of 16 computing elements located in nodes of a two-dimensional lattice 4 × 4 and interconnected by an orthogonal system of short-range communications, a call controller designed to transfer information between the base module and the host computer, and distributed memory blocks.

The disadvantages of this module are the complex matrix-pipelined structure and multi-bit information links between computing elements.

The closest device of the same purpose to the claimed invention in terms of features is the computing module adopted for the prototype (RU No. 139326 U1, IPC G06F 15/16, application form. 10.12.2013, publ. 04/10/2014, BI No. 10), containing a computing field of L computing elements corresponding to the number of parallelization channels, and each computing element contains S conveyor steps, a FIFO memory block, a variable X generator block, input and output buffers, a group of L comparison circuits, an OR element, four external inputs and four external outputs a.

The disadvantages of this computational module are the possibility of using it to process data by all computational elements according to only one algorithm, the synchronous operation of all computational elements when processing a single task for all, and the formation of a single set of results for all computational elements.

The reason that impedes the achievement of the technical result is the lack of means for individual exchange with computing elements when loading input data packets and reading result packets.

The problem to which the invention is directed, is to create a computing module having a single parameterizable computing environment for connecting computing cores, thereby simplifying the complexity of developing computing systems and increasing productivity by reducing exchange time and reducing service waiting time.

The technical result of the invention is to reduce the complexity and development time and increase productivity.

SUMMARY OF THE INVENTION

The specified technical result during the implementation of the invention is achieved by the fact that the computing module contains a group of N computing cores 6 ₁ , ..., 6 _N , an interface unit 1, a task separation unit 2, a task header memory block 3, a task data memory block 4, a task arbiter 5 , a group of N blocks of job numbers of computational cores 7 ₁ , ..., 7 _N , a block of multiplexers of results 8, an arbiter of results 9, a block of memory of headers of results 10, a block of memory of data of results 11, an external interface 12, with each computational core 6 ₁ , 6 includes _N input buffer memory 6-1, the operation unit 6-2, the output buffer control unit 6-3 and 6-4,

moreover, the external interface 12 is connected to the interface unit 1, the reset output 13 of which is connected to the corresponding reset inputs of the task separation unit 2, task header memory block 3, task data memory block 4, task arbiter 5, blocks of computing cores 6 ₁ , ..., 6 _N memory blocks job numbers 7 _1, ..., 7 _N, arbiter results 9, the memory block header result 10 and data storage unit results 11, as the interface unit 1 reading mode code bus results 14 is connected to the arbiter results 9, bus common parameters 15 Cpd ene with operating units 6-2 all cores 6 _1, ... 6 _N, bus assignments recording mode code 16 is connected to the arbiter 5 jobs, job streaming write bus 17 is connected to the job separation unit 2, the amount of code assignments bus 18 connected to the output block of memory headers for tasks 3, a bus for requests to write tasks 19 and a bus for requests for reading results 20 is connected to the outputs of all computing cores 6 ₁ , ..., 6 _N , with a bus of status code 21 is connected to the output of the block of memory for headers of results 10 and the output of the common characteristic Empty '21' mule block multiplexers of results 8, a bus for streaming reading the data of results 24 is connected to the output of the memory block of the data of the results 11, a bus for streaming reading of headers of the results 25 is connected to the output of the memory block of the headers of the results 10, and the output of the signal for reading the data of the results 22 is connected to the corresponding input of the block of results data memory 11 and the output of the signal for reading the headers of the results 23 is connected to the corresponding input of the memory block of the headers of the results 10,

a task separation unit 2 is connected to the corresponding input of the task header memory block 3 by a bus of recorded task headers 42 and a bus of recorded task data 43 is connected to a corresponding input of the task data memory block 4,

the block of headers of tasks 3 by the bus of read headers of tasks 26 and the output of the “Empty” flag of the task memory is connected to the corresponding inputs of the task arbiter 5, the output of which by the bus to read the headers of tasks 27 is connected to the corresponding input of the block of memory of the headers of tasks 3,

the job arbiter 5 with the job recording control bus 31 is connected to the input buffer memories 6-1 of the corresponding computing cores 6 ₁ , ..., 6 _N via the job recording buses 31 ₁ , 31 _N and connected to the memory blocks of the job numbers 7 ₁ , ..., 7 _N by tires 31 ' ₁ , ..., 31' _N , in addition, the task arbiter 5 is connected to the corresponding inputs of the memory blocks of task numbers 7 ₁ , ..., 7 _N via the buses 32 ₁ , ..., 32 _N, with the corresponding input of the arbiter of tasks 5 is connected to the bus of requests for recording tasks 19, including the outputs of requests for recording tasks from the calculation Yelnia cores 19 _1, ..., 19 _N, and the arbiter 5 jobs data bus read control tasks 29 is connected to the corresponding input data storage unit 4 jobs which output the read data bus 30 is connected with assignments corresponding inputs of the input buffer memory 6-1 corresponding computing cores 6 ₁ , ..., 6 _N ,

the corresponding outputs of the control units 6-3 of the computing cores 6 ₁ , ..., 6 _N with the result buses 33 ₁ , ..., 33 _{N are} connected to the corresponding inputs of the unit of the multiplexers of results 8, the corresponding output of which is connected to the corresponding input of the memory block via the results bus of the selected computing core 33 results data 11, moreover, respective outputs closure results read packet 34 _1, ..., 34 _N control units 6-3 cores 6 _1, ... 6 _N are connected to respective inputs of multiplexers unit 8 results, The appropriate output results closure reading package 34 which is connected to the corresponding inputs results arbiter 9, the storage unit 10 and results of header data result storage unit 11, respective outputs closure tasks 35 _1, ..., 35 _N control units 6-3 cores June _1, ... , _N 6 are connected to respective inputs of the storage units 7 job numbers _1, ..., _N, and 7 are connected to respective inputs of which multiplexers unit 8 results corresponding output event end 35 is connected to the corresponding I ladies memory block header of the results 10

the corresponding outputs of the blocks of memory of the numbers of tasks 7 ₁ , ..., 7 _N with the buses of the read numbers of the tasks 36 ₁ , ..., 36 _{N are} connected to the corresponding inputs of the block of multiplexers of results 8, the corresponding output of which is connected via the bus of the read numbers of the task 36 to the corresponding input of the block of memory of the results headers 10,

the corresponding outputs of the arbiter of the results 9 outputs of the signals of reading the results of 37 ₁ , ..., 37 _{N are} connected to the corresponding inputs of the blocks of the output buffer memory 6-3 of the corresponding computing cores 6 ₁ , ..., 6 _N , as well as the corresponding outputs of the arbiter of the results of 9 via the 38 number code bus of the selected computing core are connected to the control inputs of the block of results multiplexers 8, and through the bus of the number of words in the result package 39 are connected to the corresponding inputs of the memory block of the headers of the results 10, the output of the overflow sign 41 which is connected to the corresponding input of the result arbiter 9, the corresponding input of which is connected to the output 40 of the overflow sign of the result memory 11.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a functional diagram of a computing module.

In FIG. 1 the following notation is accepted:

1 - interface unit

2 - block separation tasks

3 - memory block headers tasks

4 - block data memory tasks

5 - task arbiter,

6 ₁ , ..., 6 _N - a group of N computing cores (VY),

6-1 - input buffer memory VYA,

6-2 - operational unit VJ,

6-3 - output buffer memory VYA,

6-4 - control unit VYA,

7 _1, ..., 7 _N - group of N memory blocks VYa job numbers,

8 - block multiplexers of results,

9 - the arbiter of the results,

10 - memory block headers of the results,

11 is a block of memory data data,

12 - external interface

13 - reset output,

14 - bus code reading mode results,

15 - bus general parameters transmitted by the parallel code,

16 - bus code mode recording tasks

17 - bus streaming recording jobs

18 - bus code number of jobs in the input memory,

19 - bus requests for recording tasks

19 ₁ , ..., 19 _N - requests for recording tasks from VY,

20 - bus requests to read the results,

20 ₁ , ..., 20 _N - requests for reading the results from VY,

21 - bus status code memory results,

21 'is the output of the common feature "Empty" of all memory blocks of the job numbers 7 ₁ , ..., 7 _N ,

22 - output signal read data data,

23 - output signal read headers of the results,

24 - bus streaming read data data,

25 - bus streaming reading of the headers of the results,

26 - bus read job headers,

27 - bus control reading the titles of tasks

28 - exit sign "Empty" memory tasks

29 - bus control read data tasks

30 - bus read data tasks,

31 - bus control recording tasks

31 _1, ..., 31 _N - account management tasks in the tire load cells,

31 ' ₁ , ..., 31' _N - outputs the end of the job recording in VY,

32 - bus recorded numbers of tasks,

32 _1, ..., 32 _N - tire recordable VYa job numbers,

33 ₁ , ..., 33 _N - result buses from VY,

33 - bus results selected VYA,

33 '- output sign of reliability of the result,

34 ₁ , ..., 34 _N - the outputs of the end of reading the result packages from VY,

34 - output end of reading the result package of the selected VJ,

35 ₁ , ..., 35 _N - outputs the end of tasks from VY,

35 - output end of the job selected VY,

36 ₁ , ..., 36 _N - bus readable job numbers from VV,

36 - bus readable job number of the selected VL,

37 ₁ , ..., 37 _N - outputs of signals for reading the results of VJ,

38 - bus code number selected by the arbitration scheme VY,

39 - bus number of words in the result package,

40 - output sign of memory overflow results,

41 - output flag overflow memory headers of the results,

42 - bus recorded titles of tasks,

43 - bus recorded data tasks.

DETAILED DESCRIPTION OF THE INVENTION

The proposed computing module (VM) is designed to combine the set of N computing cores 6 ₁ , ..., 6 _N. Independent sub-tasks are implemented on the data of the VL, and the proposed computational module is intended for solving them. Loading tasks for VYA and reading the results of their work are carried out by the control processor (UP).

The proposed computing module provides a unified parameterizable interface for embedding computing cores, which reduces the preparation of the module only to the development of computing cores 6 ₁ , ..., 6 _N.

The proposed computational module supports automatic loading of tasks into the VL from the input buffer memory of tasks and automatic reading of the results from the VL into the output buffer memory of the results. With automatic loading of tasks and automatic reading of results, the control processor does not control each VL, but only loads task packages into the input buffer memory and reads the result packages from the output buffer memory of the computing module.

The interface unit 1 converts the signals of the interface 12 from the control processor into the signals of the internal interfaces of the module. The buses of the internal interface of the module consist of 4 groups of buses: buses of command codes and constant parameters 13, 14, 15, 16, buses of streaming recording of tasks 17, buses of status signals of the module 18, 19, 20, 21 and buses of streaming reading of results with control signals 22 , 23, 24, 25.

The codes of commands and constant parameters consist of a reset signal (initial initialization) of module 13, a code for reading the results 14, a code for general (identical) parameters 15 transmitted by a parallel code for all VL 6 ₁ , ..., 6 _N , and a code for the mode of recording tasks 16 These codes are downloaded from the control unit into the corresponding registers of the interface unit 1. To change a command, it is necessary to re-write to the same register or re-write to the same group of registers.

The interface unit 1 converts the streaming recording commands and job packages received from the UE via the external interface 12 into data streams transmitted via the bus 17. The streaming recording bus of the jobs 17 consists of a directly recorded data bus and a recording signal. Each of the job packages consists of a package header and the data that follows.

The module status codes include the code for the number of job packets in the input memory 18, the code for the number of result packets in the output memory and the “Empty” flag for job numbers 21, requests to record jobs 19 and read the results 20 from VL 6 ₁ , ..., 6 _N. The interface unit 1 provides the reading of the status codes of the module with single read commands of the external interface from the unitary enterprise.

The signal for reading the results data 22, the bus for streaming reading the data for results 24, the signal for reading the headers of the results 23 and the bus for reading the headers of the results 25 read the results to the external interface 12 to the control unit. The interface unit 1 converts the streaming read commands of the external interface 12 into read signals 22 and 23 and receives results from the read buses 24 and 25.

The task separation unit 2 is used to separate the packets into headers and data 2. After the reset signal 13, the task separation unit 2 receives the first word on the stream recording bus 17 as the header of the task package, extracts from this word the code for the amount of data following the task package, remembers this code, writes the task header on the bus of the recorded task headers 42 to the memory of the task headers 3. When the following words arrive on the stream recording bus 17, the task separation unit 2 formats them depending on the set with the parameter of the width of the job data bus, writes the reformatted words on the bus of the recorded job data 43 to the job data memory 4 and counts the number of recorded data in this job package. When the number of recorded words of the data reaches the value specified in the header of the job package, the counter of the recorded words of the job package is reset, and the next word from the recording stream via the stream recording bus of tasks 17 is taken as the header of the new job package. If the bit width of the data bus VYA 30 is greater than the bit width of the stream recording bus 17, then block 2 converts the format of the data coming on the bus 17, combining several input words of the bus 17 into one recordable word on the bus 43.

The blocks of the input memory of the headers of tasks 3 and the data of tasks 4 are dual-port RAM, on one port of which only recording is performed, and on the other port is read-only. Writing to these memory blocks is carried out only sequentially, with the discipline of writing FIFO, and reading is carried out sequentially or with random access for re-reading job packets in the sequential loading mode of one job in the VL 6 ₁ , ..., 6 _N.

In the block of memory of the headers of tasks 3 are recorded the headers of tasks on the bus 42, which are then transmitted via the signals on the control bus 27 via the bus of the read headers 26 to the task arbiter 5. Block 3 also generates and issues for reading to the interface block 1 the code of the number of tasks on the bus 18 , as well as the sign of "Empty" job memory by output 28 to the job arbiter 5. The memory block of the job headers 3 by the reset signal 13 resets the internal counter of the write address to the memory and the counter of the number of job packets in the memory. In the mode of repeated reading of the same task for the operation of the counter of the number of packets in the input memory 3, the signal of the last reading of the packet header is also transmitted via bus 17.

The data block of the job data 4 writes the data of the job packages on the bus 43, to the address transmitted by the task arbiter 5 on the control bus 29, and the data of the job packages on the VL 6 ₁ , ..., 6 _N are read out on the bus of the read data of the tasks 30. The memory block of the data of tasks 4, by a reset signal 13, resets the counter of the memory write address. The memory block 4, when the width of the data bus VYA 30 is less than the bitness of the stream recording bus 17, when reading converts the format of the read data to the format of the bus 30, by multiplexing.

Task Arbitrator 5 reads task packages from blocks of input memory for task headers 3 and task data 4 and writes task data to computing cores 6 ₁ , ..., 6 _N , and the corresponding numbers to identify which task the result relates to, in N memory blocks job numbers 7 ₁ , ..., 7 _N. In this case, the task arbiter 5 receives from the interface unit 1 on the bus 16 the code for the mode of recording tasks, and on the bus 19 requests to record tasks from the computing cores. Via bus 31 from task arbiter 5, VIA 6 ₁ , ..., 6 _N receives control signals for recording tasks 31 ' ₁ , ..., 31' _N , and via bus 32 from task arbiter 5, they are sent to memory blocks of task numbers 7 ₁ , ..., 7 _N recordable job numbers, which are recorded by signals 31 ' ₁ , ..., 31' _N. According to the reset signal 13, the task arbiter 5 resets the address counters of the memory blocks 3 and 4 and goes into standby mode for removing the “Empty” sign at the output 28.

A task can generally consist of several packages. The header of the first job package contains the job recording mode code and the job number. The header of the last job package contains the attribute of the last package, which forms the signal for the end of the job loading. The signals for terminating the loading of tasks at the outputs 31 ' ₁ , ..., 31' _N inform the corresponding VL 6 ₁ , ..., 6 _N that the next task is loaded in the input memory 6-1 for execution, and initialize the recording of the number of this task in the corresponding memory block number tasks 7 ₁ , ..., 7 _N. If the task contains only parameters, and not the data for calculation, then the header of the last package of the task does not contain a sign that initiates the issuance of a signal to finish loading the task. The headers of all job packages contain the code for managing the job record (to which part of the input memory the data should be sent) and the number of data words in the package.

The job recording mode is determined by the job recording mode code in the header of the job package and the job recording mode code coming from interface unit 1 via bus 16. The proposed module supports the following job recording modes in VL 6 ₁ , ..., 6 _N :

- Recording in the corresponding reference load cell 6 _1, ... 6 _N, the number of which is transmitted from the interface unit 1 via the bus 16, without waiting for the availability of a write request from the task of this nucleus. The mode is intended only for recording parameters in VJ.

- Writing the task to the corresponding VL 6 ₁ , ..., 6 _N , the number of which is transmitted from the interface unit 1 via bus 16, after reading on the bus 19 to the UE the presence of a request to write the task from this core.

- Recording a task in the corresponding VL 6 ₁ , ..., 6 _N , whose number is indicated in the header of the first task packet, without waiting for a request to write a task from this kernel. The mode is intended only for recording parameters in VJ.

- Recording a task in the corresponding VL 6 ₁ , ..., 6 _N , the number of which is indicated in the header of the first task packet, with the expectation of a request to write a task from this core via bus 19. Analysis of requests to record tasks is performed automatically by the task arbiter 5.

- Recording tasks in parallel to all VL 6 ₁ , ..., 6 _N , without waiting for requests to record tasks from all cores. The mode is intended only for recording general parameters in VL 6 ₁ , ..., 6 _N.

- Recording a task in parallel to all VL 6 ₁ , ..., 6 _N , with the expectation of the presence of requests to record the task from all VL. Moreover, the analysis of requests for recording tasks is performed automatically by the task arbiter 5.

- Recording a task sequentially in all VL 6 ₁ , ..., 6 _N , with the expectation of the availability of requests to record a task from each core before writing the task to it. An analysis of requests for recording tasks is performed automatically by the task arbiter 5. This mode may be preferable to the parallel recording mode of a task if VL 6 ₁ , ..., 6 _N cannot combine the task recording and processing of the previous task, since it does not require readiness to write the task of all cores simultaneously, and while a task will be recorded in one core, the rest can process tasks.

- Recording the task in the corresponding VL 6 ₁ , ..., 6 _N , selected by the task arbiter 5. The task arbiter 5 automatically selects the corresponding VL 6 ₁ , ..., 6 _N for recording the task in accordance with the priority of the write requests from the VL 6 ₁ , ... , 6 _N. In this case, from each VL 6 ₁ , ..., 6 _N , a 2-bit write request code is received and analyzed on the buses 19 ₁ , ..., 19 _N. Zero code means no request. A larger code value corresponds to a higher request priority. With equal values of the request codes, VL 6 ₁ , ..., 6 _N with a lower serial number has a higher priority.

Computing cores 6 ₁ , ..., 6 _N must have the same interface with the rest of the module blocks, i.e. the same tire capacity 15, 30 and 33, but may have some differences in the internal structure. This is noted in FIG. 1 by numbers "1" ... "N", which are transmitted as parameters to the VW and can be taken into account in the synthesis of VV.

On the inputs of VL 6 ₁ , ..., 6 _N from the interface unit 1, a reset signal 13 and the same parameters for all VL 6 ₁ , ..., 6 _N are received on bus 15. From the job arbiter 5, buses come on VL 6 ₁ , ..., 6 _N write control 31 ₁ , ..., 31 _N , and from the data block of the job data 4 via the read bus 30 job data for recording. From the arbiter of results 9 to VL 6 ₁ , ..., 6 _N , signals are received to read the results 37 ₁ , ..., 37 _N. From the outputs of the VL 6 ₁ , ..., 6 _N , the bus of the VL 33 ₁ , ..., 33 _N results, the signals of the end of reading the result packets 34 ₁ , ..., 34 _N and the signals of the end of the tasks 35 ₁ , ..., 35 _N are sent to the block of multiplexers of results 8 . The signals on the buses 35 ₁ , ..., 35 _{N are} also fed to the reading inputs of the corresponding memory blocks of the job numbers 7 ₁ , ..., 7 _N.

Each VL 6 ₁ , ..., 6 _N consists of an input buffer memory 6-1, an operating unit 6-2, an output buffer memory 6-3, and a control unit 6-4.

Input buffer memory 6-1 includes parameter memory and data memory. The parameters are loaded before processing the array of tasks and do not change during the processing of this array of tasks, and the data changes from task to task. To combine the loading of task data into memory and the processing of previously loaded task data, the data memory consists of several identical blocks. In the memory 6-1 VYA data is written from the bus 30 under the control of the signals of the corresponding bus 31 ₁ , ..., 31 _N. Reading from the memory 6-1 to the operating unit 6-2 is carried out on the interface selected by the developer of VJ. The control of the modes of writing and reading tasks from the memory block 6-1 for processing in the operation block 6-2 is carried out by the control unit 6-4 of the corresponding VL.

The operating unit 6-2 VYA 6 ₁ , ..., 6 _{N is} brought to its initial state by a reset signal 13, it is launched to perform the next task by the control unit 6-4, it records the results of the task and the sign of the end of the processing of the task due to the overflow of the output buffer in the output buffer memory 6-3, generates and transmits to the control unit 6-4 a signal to complete the next task and a sign of overflow of the output buffer. If as a result of processing the next task by the operating unit 6-2, the overflow of the output buffer memory 6-3 is overflowed and the processing of the task is not completed, the operating unit remembers the breakpoint at overflow and, at the next start from the control unit 6-4, starts processing the remaining part of the job from this breakpoint, and the control unit 6-4 in this case does not switch to the input of the operating unit 6-2, the next input memory unit 6-1, but leaves the previously connected unit and starts the operation unit 6-2 for processing immediately when there is a free block of output memory 6-3.

The output buffer memory 6-3 also consists of several identical blocks to reduce downtime of the operating unit 6-2 while waiting to write and write to the input memory 6-1 or to wait for reading and reading from the output memory 6-3. The block numbers for recording the results from the operating unit 6-2 and reading the results from the VL are selected by the control unit 6-4. The results are written to the output memory 6-3 from the operating unit 6-2 by the interface selected by the developer of VJ. When the control unit 6-4 selects the next 6-3 memory block for reading to the control unit, a sign of the absence of results and a signal to end the reading of the results from this block are received from the memory block selected for reading. Reading the results from the memory output 6-3 occurs on the corresponding signal 37 ₁ , ..., 37 _N. Reading occurs in the general case with some pipeline delay.

The results read from the computing cores are output to the corresponding bus 33 ₁ , ..., 33 _N. These results are accompanied by a sign of reliability of the result 33 '(Valid). The last word of the result to be read is accompanied by a signal for the corresponding output 34 ₁ , ..., 34 _N , and if it is also the end of the job processing (there was no sign of overflow when recording the results from the operation unit), then a signal is issued for the corresponding output 35 ₁ , ... , 35 _N.

If there are no results in the task, the proposed module of the computing environment supports two different operating modes of VL. In the first mode, the control unit 6-4, when the output memory block 6-3 is selected for reading with a zero number of result words, does not issue a read request on the corresponding bus 20 ₁ , ..., 20 _N , and the corresponding output memory block 6-3, after it has been selected for reading, it immediately gives the corresponding signal for the end of task 35 ₁ , ..., 35 _N , after which the control unit immediately selects the next memory block of the results 6-3 for reading or waits for the results to be loaded into this block if the output memory 6-3 has only one block. In the second operation mode of the VL, after choosing to read the memory block 6-3 with zero number of results, the control unit 6-4 issues a corresponding request to read 20 ₁ , ..., 20 _N , as with a non-zero number of results, and the memory block 6- 3, it awaits the arrival of the corresponding read signal 37 ₁ , ..., 37 _N and, upon its arrival, outputs to the control unit 6-4 a read end signal, and to the output multiplexer block 8 at the outputs, the corresponding signals for reading the packets 34 ₁ , ..., 34 _N and the end Tasks 35 ₁ , ..., 35 _N. Moreover, the sign of reliability of the result on the bus 33 ₁ , ..., 33 _{N is} not issued. In the first mode, if there are no results, the task number is simply erased from the memory of the task numbers 7 ₁ , ..., 7 _N , and time is not spent on writing the headers of empty results to the output memory and reading them, and in the second mode, the numbers of the "ineffective" tasks are explicitly indicated in headings of results. The operating mode of the VL 6 ₁ , ..., 6 _N, in the absence of results, is selected by the VL developer.

The control unit 6-4 of the corresponding VL 6 ₁ , ..., 6 _N receives the reset signals 13, the end of the recording of the executed task in the input memory 31 ' ₁ , ..., 31' _N , the end of processing from the operation unit 6-2 with an overflow sign, zero quantity words of results in the selected block of output memory 6-3, the end of reading the results from the selected block for reading the output memory. The control unit 6-4 selects the block numbers of the input 6-1 and the output memory 6-3 for writing and reading, generates a start signal for the operating unit 6-2 and request codes from the kernel for recording the task and reading the results. The logic for generating write and read requests is determined by the developer of VJ. The request code is assigned the highest value, if it is the execution of the requested write or read operation that delays the next launch of the operating unit, if, in addition to performing the requested operation, for example, writing, it is also necessary to perform the read operation to start the operation unit, the priority of the request is set less, and if execution operations are possible, but the operation unit is working, then the priority is minimal. If it is impossible to perform this operation, a null request code should be generated.

The memory blocks of job numbers 7 ₁ , ..., 7 _N are FIFO memory blocks. The reset inputs 13 receive signals to the reset inputs of these memory blocks, the end recording signals of executed tasks 31 ' ₁ , ..., 31' _N are received, the read inputs used as signals to change the read number of the task receive signals to complete the tasks 35 ₁ , ... , 35 _N , to the data inputs - buses of recorded job numbers 32 ₁ , ..., 32 _N. From the outputs of the memory blocks of the job numbers 7 ₁ , ..., 7 _N , the job numbers, which include the read results and the “Empty” signs, are sent to the result multiplexer block 8 by the corresponding buses 36 ₁ , ..., 36 _N.

To the block of multiplexers of results 8, the number code of the selected VL 6 ₁ , ..., 6 _{N is} received from the arbiter of results 9 via bus 38. In accordance with this code, the multiplexer unit transmits one of the input buses of the results 33 ₁ , ..., 33 _N to the output bus 33, the job number from one of the input buses 36 ₁ , ..., 36 _N to the output bus 36, one of the input signals 34 ₁ , ..., 34 _N to the output 34, and one of the input signals 35 ₁ , ..., 35 _N to the output 35. Also, in the block of multiplexers of results 8 based on the signs of "Empty" memory blocks of job numbers 7 ₁ , ..., 7 _N , transmitted on lines 36 _1, ..., 36 _N, is formed by a common feature of "empty" for all memory blocks job numbers 21 ', which is transmitted over the bus 21 to the interface lock 1. The common attribute “Empty” of job numbers is used by the UE to determine the end of processing the entire job package, if the computational cores, in the absence of the results of the next job, do not give a read request, but immediately give a signal to finish the job 35 and the number of this job is absent headings of results.

The result arbiter 9 receives a reset signal 13, a mode code for reading the results on bus 14, requests for reading cores from the bus 20, end signals from the selected arbiter on the bus 34, a sign of reliability of the result code 33 'read from the selected kernel, and signs of overflow output memory blocks 40 and 41. The results arbitrator results reading results 9 generates signals 37 _1, ..., 37 _N in the respective processing core 6 _1, ... 6 _N, number of selected computational kernel code 38 results in a block multiplexer 8 and to the code lichestva words in the package 39 results in memory header block 10 results.

The mode of operation of the result arbiter 9 is determined by the control code received on the bus 14. The arbiter of results 9 can operate in three different modes:

- Reading the result from the corresponding VL 6 ₁ , ..., 6 _N , the number of which is transmitted from the interface block 1 via bus 14, after reading on bus 20 to the interface block 1 and analyzing the request to read the result from this core.

- Reading result successively from all load cells 6 _1, ... 6 _N, with the expectation of having read requests over the bus 20 the result of each load cell before reading result therefrom. An analysis of requests to read the result on the bus 20 is performed automatically by the arbiter of results 9. This mode can be used for the same time of loading, completing tasks and reading the results for all VL.

- Reading the result from the corresponding VL 6 ₁ , ..., 6 _N , selected by the arbiter of the results 9. In this case, the arbiter of the results 9 automatically selects the kernel for reading the result in accordance with the priority of requests for reading from the VL. Each core receives a two-bit read request code on the corresponding buses 20 ₁ , ..., 20 _N. Zero code means no request. A larger code value corresponds to a higher request priority. With equal values of the request codes, VL with a lower serial number has a higher priority.

The memory blocks of the headers of the results 10 and the memory of the data of the results of 11 implement the discipline of service FIFO.

The block of headers of the results 10 writes a signal to the end of reading the results 34 the header of the result, consisting of codes of the task number 36, the number of words in the result package 39 and the sign of the end of the task 35. By the read signal 23 from the interface unit 1, the headers of the result packets are read from the memory block 10 on the bus 25 to the interface unit 1. Also, the memory unit 10 issues a code for the number of result packets in the output memory for reading to the UP interface on the bus 21 to the interface unit 1 and a sign of overflow of the result headers memory Comrade 41 to Arbitrator of Results 9.

The result data memory unit 11 writes a result validity signal 33 'to the result data code coming on the bus 33. From this memory unit 11, the result data packets are read out on the read signal 22 coming from the interface unit 1 through the bus 24. Also, the memory block 11 gives a sign of overflow of the memory of the results 40 into the arbiter of the results 9. The memory block 11 also converts the bitness of the output bus of the VL 33 results to the bit width of the stream read operation 24. When the bit width of the output bus of the VL 33 results is lower than the bit width of the stream read operation 24 , the bit conversion occurs at the input of the memory block 11, and when the bit capacity of the bus 33 is greater than the bit capacity of the bus 24, the bit conversion occurs at the output of the memory block 11.

The proposed computing module operates as follows.

The control processor (UP) usually works with several offered VMs at the same time. On all modules and in each module, the same VL 6 ₁ , ..., 6 _N can be used, designed to perform the same tasks, or different VL 6 ₁ , ..., 6 _N , which can differ and are intended to perform fundamentally different tasks.

Work UP with VM occurs in the following sequence.

UE sets the operating modes of the module for recording tasks and reading results and general parameters of VL 6 ₁ , ..., 6 _N. After that, the UE performs initialization of the module, giving a reset signal 13, and starts working with the module. The reset codes, operating modes, and parameters transmitted by the parallel code are sent to the module via the interface bus UP 12 and after conversion in the interface unit 1 are fixed in its internal registers and transmitted to the module blocks via buses 13, 14, 15, and 16.

In the operation of the control processor with the VM after loading the modes, 3 processes can be distinguished: recording tasks, reading results and analyzing the end of work.

The process of recording tasks. The control processor periodically reads the number of job packets in the input memory by transmitting information from the bus 18 by the interface unit 1 to the external interface bus 12. The control processor, based on the volume of the memory blocks of the headers 3 and the data 4 of the jobs and the amount of job packets loaded into them, determines the amount free input memory and loads into it the maximum possible number of tasks from the array of tasks to perform. In the automatic selection mode VL 6 ₁ , ..., 6 _N , the task recording function ends here. In the VL select mode from the control unit, the control processor also reads write requests from the VL via bus 19, selects the core for recording from these requests, and sends the code for the number of this core and the initialization signal to overwrite the job from the input memory to the given core via bus 16. The VL selection mode for recording jobs from the UE is an auxiliary mode of the module.

The process of reading the results. The control processor periodically reads the number of result packets in the output memory. Reading occurs by transmitting information from the bus 21 by the interface unit 1 to the bus of the external interface 12 at the request of the unitary enterprise. If the number of result packets is nonzero, the control processor reads the headers of these results from the memory unit 10. Before starting the reading, the UE issues a request to the interface unit 1 to read the specified number of words on the bus 25. The interface unit 1 generates a read signal 23 with a duration corresponding to the number of read words , and on the bus 25 transmits from the memory unit 10 to the external interface 12 the required number of words. The control processor analyzes the read headers of the result blocks, sums the number of words in the result packets that are contained in these headers, taking into account the conversion of the capacity of the results to the capacity of the interface exchange, and reads from the memory block 11 the required number of results words. Before reading, the UE issues a request to the interface unit 1 to read the specified number of words on the bus 24. The interface unit 1 generates a read signal 22 with a duration corresponding to the number of words to be read, and transmits the required number of words from the memory unit 11 to the external interface 12 . In the automatic modes of selecting the VL for reading, the function for reading the results of the UP ends on this. In the selection mode of VL 6 ₁ , ..., 6 _N for reading from the control unit, the control processor also reads read requests from the VL on bus 20, selects the core for reading from these requests and sends the code for the number of this core and the signal to read the result from the given core on bus 14. The kernel selection mode for reading the results from the UE is an auxiliary mode of the module.

The process of analyzing the completion of work. If VYA 6 ₁ , ..., 6 _{N of the} module at the end of the processing of the task put a read request on bus 20 even if there are no results, then the end of the module is determined by the fact of reading all the results and the presence in the headings of these results of numbers of all tasks loaded into the module with signs their termination on the bus 34. If VYa do not submit a request to read on the bus 20 in the absence of results and, therefore, there are no results headers with numbers of ineffective tasks, then the termination of the module is determined by coincidence constituent conditions: a module contains all the jobs intended for it, the number of jobs in the input memory module is zero, the number of packets results in the output of the memory module is zero, all numbers memories jobs are "empty". The number of jobs in the input memory is determined by the UP by reading the code from bus 18, and the number of result packets in the output memory and the “Empty” flag of all memory blocks of the job numbers 7 ₁ , ..., 7 _{N are} determined by the UP by reading the bus 21.

Jobs come from the UE via the external interface 12, are converted by the interface unit 1 into the signals of the streaming recording bus 17, are separated by the unit 2 on the fly (without buffering) into the headers of the job packets and the job data directly loaded into the computational cores, which are written to the memory blocks headers of tasks 3 and data of tasks 4, respectively, on buses 42 and 43. In the block for separation of tasks 2, the first word coming after the reset signal 13 on the bus of tasks 17 is considered the heading of the task package, and this title is written communication via bus 42 to memory block 3. From this header, in block 2, the number of data words in this packet is stored, and then this number of words, taking into account the ratio of the word length of the job data and the word length of the interface exchange, is recorded from bus 17 through the task separation unit 2 to the data memory 4 via the bus 43. After the recording of the required number of words in the data memory unit 4, the next word received via the bus 17 is again perceived by the task separation unit 2 as the title of the next task.

In automatic selection mode VYA 6 ₁ , ..., 6 _N, the task arbiter block 5, if there is a task in the input memory by the signal at output 28, reads the header of the first task packet on bus 26 at address 27, and depending on the code of the core selection mode, Header writes the task to the selected one or to all of the computational cores 6 ₁ , ..., 6 _N without analyzing write requests from these kernels, or waits for a write request from the selected kernel in the header and, after its appearance, writes the task to this kernel, or waits for requests to appear to record from all cores simultaneously and record sends the task in parallel to all cores, or waits for a request from at least one core and writes the task to the core that is selected by the priority analysis circuit in the block of task arbiter 5. In the sequential recording mode of a task in all WL, the block of task arbiter 5 waits for a write request from the first core, writes the task to the first core, then returns the addresses on buses 27 and 29 to read the same task and waits for a write request from the second core, writes the task to the second core. Next, the task arbiter block 5 repeats the same actions sequentially for all other cores.

In the selection mode of the VL from the control unit, the control processor analyzes the write requests from the VL on the bus 19, issues the code of the selected core number and the write signal on the bus 16 to the task arbiter 5, through which the task arbiter 5 writes the task to the corresponding core.

When recording tasks in VL 6 ₁ , ..., 6 _N , the task arbiter block 5 generates control codes for writing to the cores via buses 31 ₁ , ..., 31 _N in accordance with the value of this code in the header of the corresponding task package for the selected kernel for recording or all cores. The duration of the recording code is determined by the number of words indicated in the packet header. Synchronously with the write control code, job arbiter 5 generates an address on bus 29 for reading job data, which is sent via bus 30 to the inputs of the VL data. If this task is executable, and not parameter packets, then upon completion of data recording for the last packet in the task, the task arbiter 5 generates signals to complete the recording of task 31 ' ₁ , ..., 31' _N , according to which control units VYA 6-4 record the reception in the core of the next task for execution, and in accordance with this control the selection of input memory blocks of task 6-1 for writing and reading, the next launch of the operating unit 6-2 and the formation of write requests 19 ₁ , ..., 19 _N and read 20 ₁ , ..., 20 _N. Also, by the signals of the end of the recording of the task 31 ₁ , ..., 31 _N received by the memory blocks of the task number 7 ₁ , ..., 7 _N , the number of tasks are written to these memory blocks from the buses 32 ₁ , ..., 32 _N. The numbers of tasks are generated in the task arbiter 5 from the code of the number of the task, memorized when the arbiter reads the title of the task, and the code of the number VY, if the record is made sequentially or in parallel to all cores.

Each of the computing cores 6 ₁ , ..., 6 _N sequentially processes the tasks received by this core, reading data from one of the blocks of the input memory 6-1 and writing the results to one of the blocks of the output memory 6-3. The memory blocks for reading 6-3 and for writing 6-1 are selected only sequentially. A condition for starting processing of the next task is the end of the processing of the previous task, the presence of the next task in one of the blocks of the input memory 6-1 and the presence of a free block in the output memory 6-3 for recording the result. The condition for starting the processing of the job after overflowing the block of the output memory 6-3 is a free block in the output memory 6-3.

Requests for reading the results 20 ₁ ... 20 _N are received by the arbiter of the results 9 and on the interface unit 1.

Arbitrator of results 9 operates in one of three modes: selecting the VL for reading the result according to the priority of the read request, sequential reading of the results from all the cores in the order of numbering, and choosing the core for reading the results from the control unit.

In the selection mode VL 6 ₁ , ..., 6 _N according to the priority of the request to read the result 20 ₁ ... 20 _N , the arbiter of the results 9, after the reset signal 13 or the end of reading the previous result, waits for at least one request and selects the core with the highest priority of the request for reading. In the sequential reading of the results in the order of the numbering of kernels, the arbiter of results 9 after the reset signal 13 waits for a read request from the 1st core, and after reading the result from the next core, waits for a request from the kernel with the following sequence number. In the kernel selection mode from the control unit, the control processor analyzes read requests from the VL via bus 20 and issues the code of the selected kernel number and the signal to start reading on bus 14 to the result arbiter 9. Based on this signal, the result arbiter 9 starts reading the results from the corresponding kernel. In the other two modes, the start of reading is automatically determined by the arbiter of results 9.

When reading the results, the arbiter of the results 9 puts on the bus 38 the number of VL, from which the results are read, and the read signal on the corresponding output 37 ₁ , ..., 37 _N. The read signal from the selected core reads the result on the corresponding bus 33 ₁ , ..., 33 _N , followed by a sign of reliability. When reading the last word in the result package from the output of the VJ, the corresponding impulse 34 ₁ , ..., 34 _{N is formed} , and if this is the last word of the result in the task, the corresponding impulse 35 ₁ , ..., 35 _N is also formed. The signals from each VL 6 ₁ , ..., 6 _N are supplied to the inputs of the block of multiplexers of results 8. Also, the inputs of the block of multiplexers 8 are supplied from the memory blocks of job numbers 7 ₁ , ..., 7 _N job numbers that are executed by cores 6 ₁ , ..., 6 _N , and the “Empty” signs of the corresponding memory blocks 7 ₁ , ..., 7 _N , which are transmitted to the outputs of the multiplexer unit 8 in accordance with the number set on the bus 38. Also, in the multiplexer block 8, the “Empty” sign of all job number memory blocks is generated 21 '. The signal to finish reading the result package 34 from the output of the multiplexer unit 8 is used by the result arbiter 9 to finish reading the next result package, the result header memory block 10 uses this signal to write the result packet header, and in the result data memory block 11 this signal resets the counter used for reformatting the words of the data of the results if the digit capacity of the output of the ID is several times less than the word capacity of the stream reading interface. The bus of task number 36 and the signal of the end of task 35 are received from the output of the multiplexer unit 8 only to the input of the memory of the results headers 10. The data bus of the results 33 is fed to the input of the data of the results 11 data, and the sign of the reliability of the results from the output 33 'goes to the arbiter of the results 9 the number of words in the result package and issuing this number on the bus 39 to the input of the memory of the headers of the results 10. Signs of overflows from the outputs of the memory blocks of the headers 41 and the data of the results 40 are sent to the arbiter of the results 9 to suspend and the process of reading the results in the presence of at least one of these signals.

The memory block of the headers of the results 10 on the signal to finish reading the packet of results 34 writes the header of the packet of results, consisting of the number of the task 36, the number of words in the result package 39 and the sign of the end of the task 35. The memory block 10 also generates an overflow sign 41 and a code for the number of result packets in the output memory 21. According to the read signal 23, the memory unit 10 issues the result headers to the streaming read bus 25.

The results data memory block 11 reformatts the data at the input or output. Writing to the memory unit 11 takes place according to the data reliability signal on the bus 33. The memory unit 11 generates an overflow sign 40. By the read signal 22, the memory unit 11 outputs the result data to the stream reading bus 24.

The proposed computing module was used in the development of a computer system with accelerators based on the Xilinx FPGA XC7K410T. In the development of sun on the FPGA based on the proposed BM used previously developed project parametrized computing environment and develop only computational core 6 _1, ... 6 _N interface, regulated proposed VM. Further, the parameters specify the width of the job data bus, the results bus and the bus of the VL parameters transmitted by the parallel code, the number of VL 6 ₁ , ..., 6 _N in the module and the frequency of synchronization of the recording of tasks, reading the results and processing. RTL-descriptions of VYa 6 ₁ , ..., 6 _{N are} integrated with the design of the computing environment, and in CAD for this FPGA, the project is compiled to obtain code for programming the FPGA. The number VL 6 ₁ , ..., 6 _N and the values of the synchronization frequencies are selected to achieve maximum performance of the VCA.

Estimates showed a 25% reduction in the complexity and time of developing a computing system compared to developing without using a unified computing environment. Moreover, the computing environment in the proposed computing module occupies no more than 5% of FPGA resources, the time spent analyzing the state of the input and output memory in the proposed computing module was reduced by 3 times, and the downtime of the computing cores was also halved for delays in their maintenance, resulting in increased computing system performance.

Thus, the above information allows us to conclude that the proposed computing module corresponds to the claimed technical result - reducing the complexity and development time and increasing productivity.

Claims (1)

The computing module contains a group of N computing cores 6 ₁ , ..., 6 _N , an interface unit 1, a task separation unit 2, a task header memory block 3, a task data memory block 4, a task arbiter 5, a group of N memory block numbers of computational core jobs 7 ₁ , ..., 7 _N , results multiplexers block 8, results arbiter 9, results headers memory block 10, results data memory block 11, external interface 12, with each computing core 6 ₁ , ..., 6 _N consisting of an input buffer memory 6-1, operating unit 6-2, output buffer memory 6-3 and control unit 6-4, and the external interface 12 is connected to the interface unit 1, the reset output 13 of which is connected to the corresponding reset inputs of the task separation unit 2, the memory of the titles of the titles of tasks 3, the memory block of the data of tasks 4, the arbiter of tasks 5 , blocks of computing cores 6 ₁ , ..., 6 _N , memory blocks of job numbers 7 ₁ , ..., 7 _N , arbiter of results 9, memory block of headers of results 10 and memory block of data of results 11, also with interface block 1 with code bus for reading results 14 connected to result arbiter 9, other common parameters 15 is connected to all the operating units 6-2 cores 6 _1, ... 6 _N, assignments recording mode code bus 16 is connected to the arbiter 5 jobs, job streaming write bus 17 is connected to the job separation unit 2, the amount of code assignments bus 18 is connected to the output of the block of memory of the headers of tasks 3, the bus of requests for writing tasks 19 and the bus of requests to read the results 20 is connected to the outputs of all the computational cores 6 ₁ , ..., 6 _N , the bus of the status code 21 is connected to the output of the block of memory of the block of the headers of results 10 and output common feature "Empty" 21 'of the block of multiplexers of results 8, a bus for streaming reading data of results 24 is connected to the output of the memory block of data for results 11, a bus for streaming reading of headers of results 25 is connected to the output of the block of memory of headers of results 10, and the output of the signal for reading data of results 22 is connected to the corresponding input of the data block of the data of the results of 11 and the output of the signal for reading the headers of the results 23 is connected to the corresponding input of the memory block of the headers of the results 10, the unit for separating tasks 2 bus write of the second job headers 42 is connected to the corresponding input of the job header memory block 3 and the bus of recorded job data 43 is connected to the corresponding input of the job data memory block 4, the job header memory block 3 is the bus of the read job headers 26 and the output of the “Empty” sign of the job memory is connected to the corresponding the inputs of the task arbiter 5, the output of which by the control bus for reading the titles of the tasks 27 is connected to the corresponding input of the memory block of the titles of the tasks 3, the arbiter of the tasks 5 by the write control bus 31 is connected to the second input buffer memory 6-1 corresponding cores 6 _1, ... 6 _N on lines 31 _1, ..., 31 _N recording jobs and is connected to memory units 7 job numbers _1, ..., _N 7 of the tire 31 _'1 , ..., 31 ' _N , in addition, the task arbiter 5 is connected via bus 32 ₁ , ..., 32 _N to the corresponding inputs of the memory blocks of task numbers 7 ₁ , ..., 7 _N via the bus of the recorded task numbers 32, the corresponding input of the task arbiter 5 is connected to bus for requests for recording tasks 19, including the outputs of requests for recording tasks from computing cores 19 ₁ , ..., 19 _N , as well as the arbiter of tasks 5, the control bus for reading the data of tasks 29 is connected to the corresponding input by the data block of tasks 4, the output of which is connected via the bus of the read data of tasks 30 to the corresponding inputs of the input buffer memories 6-1 of the corresponding computing cores 6 ₁ , ..., 6 _N , the corresponding outputs of the control units 6-3 computing cores 6 ₁ , ..., 6 _N with the result buses 33 ₁ , ..., 33 _{N are} connected to the corresponding inputs of the unit of multiplexers of results 8, the corresponding output of which is connected via the results bus of the selected computing core 33 with the corresponding input of the results data memory block 11, in addition, the corresponding outputs of the reading of the result packets 34 ₁ , ..., 34 _N of the control units 6-3 of the computational cores 6 ₁ , ..., 6 _{N are} connected to the corresponding inputs of the results multiplexer block 8, the corresponding output reading results closure package 34 which is connected to the corresponding inputs results arbiter 9, the storage unit 10 and results of header memory block 11, the results corresponding to outputs closure tasks 35 _1, ..., 35 _N blocks councils eniya 6-3 cores 6 _1, ... 6 _N are connected to respective inputs of the storage units 7 job numbers _1, ..., _N, and 7 are connected to respective inputs of multiplexers results 8 block corresponding output job closure 35 which is connected to the corresponding inputs of the storage unit headers of results 10, the corresponding outputs of the blocks of memory of the numbers of tasks 7 ₁ , ..., 7 _N with the buses of the read numbers of the tasks 36 ₁ , ..., 36 _{N are} connected to the corresponding inputs of the block of multiplexers of results 8, the corresponding output of which is via the read bus the current job number 36 is connected to the corresponding input of the block of memory of the headers of the results 10, the corresponding outputs of the arbiter of the results 9 are the outputs of the signals of reading the results 37 ₁ , ..., 37 _{N are} connected to the corresponding inputs of the blocks of the output buffer memory 6-3 of the corresponding computing cores 6 ₁ , ..., 6 _N , as well as the corresponding outputs of the arbiter of results 9 via bus 38 of the code, the numbers of the selected computing core are connected to the control inputs of the block of multiplexers of results 8, and through the bus of the number of words in the packet of results 39 s to the corresponding inputs of the memory block of the headers of the results 10, the output of the overflow sign 41 of which is connected to the corresponding input of the arbiter of the results 9, the corresponding input of which is connected to the output 40 of the sign of overflow of the memory of the results 11.

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