RU2634199C1 - Parallel logic multicontroller - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to the construction of switching facilities for multiprocessor computing and control systems, subscriber communication systems with decentralized control and information and measurement systems.

EFFECT: increased speed of the execution of barrier synchronization of the parallel program regions running in various modules of the logic multicontroller, controllers, by increasing the switching speed between synchronization layers by parallel propagation of "waves" of clock pulses from one angled module through the entire structure to another angled module and simultaneously in reverse direction.

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Description

The invention relates to automation and computer technology and may find application in the construction of distributed software control systems and multiprocessor systems of a wide class.

A microcontroller network is known, containing M * N of the same type of modules combined into a matrix structure, where N is the number of modules in a row of the network matrix structure, M is the number of rows, each module of which includes a program memory block, address register, instruction register, logical condition multiplexer, address switch, synchronization unit, first through third OR elements, correspondence vector register, buffer register, first and second synchronization vertex number decoders, OR element block, first and second one-shots, delay element, Rupp block synchronization control module, a multiplexer synchronization channel configuration register, the first and second multiplexers, decoder synchronization channels, timing control signal generator, a first and a second group of AND gates (RF patent №2336556, ⁹ IPC G06F 9/28, G06F 15/173 , G06F 1/10; Declared April 17, 2007, published October 20, 2008, Bull. No. 29).

The disadvantage of this network is the low speed of performing barrier synchronization (and, as a consequence, its insufficient speed when implementing parallel control algorithms) due to the sequential nature of the activation of groups of blocks of synchronization control modules (groups of barriers).

The closest to the proposed parallel logical multi-controller in technical essence is a logical multi-controller with a distributed parallel-conveyor barrier synchronizer, containing M * N modules of the same type, combined into a matrix structure, where N is the number of modules in a row of the matrix structure, M is the number of lines, including a block program memory, address register, instruction register, logical condition multiplexer, address switch, synchronization unit, first to third elements OR, vector register respectively effects, buffer register, first and second decoders of the synchronization vertex number, block of OR elements, first and second single vibrators, first delay element, first and second groups of AND elements, group of synchronization control units (RF patent No. 2450328, MKP ⁹ G06F 9/00; Declared February 15, 2010, published May 10, 2012, Bull. No. 13).

The disadvantage of this device is the low number of synchronized parallel barriers, as well as the low speed of barrier synchronization of sections of parallel programs.

The technical task of the claimed invention is to expand the field of expedient use of the device, by increasing the maximum possible number of synchronized parallel barriers, as well as increasing the speed of performing barrier synchronization of sections of parallel programs running in various modules of the logical multicontroller (controllers), by reducing the switching time between synchronization layers by parallel propagation of “waves” of clock pulses from one angular module cutting the whole structure to another angular module and simultaneously in the opposite direction.

The technical problem is solved in that in each module of a parallel logical multicontroller containing M * N of the same type of modules combined into a matrix structure, where N is the number of modules in a row of the matrix structure of a parallel logical multicontroller, M is the number of lines including a program memory block, address register , command register, logical conditions multiplexer, address switch, synchronization block, first and second elements OR, buffer register, block OR elements, first and second one-shots, delay element, module synchronizer, and the input of the operation code of the module is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the output of which is connected to the address input of the program memory block, the output of which is connected to the information input of the command register, the first output of which is connected to the address input the logical condition multiplexer, and the second output with the second information output of the logical condition multiplexer, the first information output of which is connected to the logic input x conditions of the module, the third output of the instruction register is combined with the output of the logical conditions multiplexer and connected to the first input of the block of OR elements and to the information input of the buffer register, the output of which is connected to the second input of the block of OR elements, the output of which is connected to the second information input of the address switch, fourth the output of the command register is connected to the output of microoperations of the module, the fifth, sixth, seventh and eighth outputs of the command register are connected to the eighth, twelfth, ninth and fifteenth inputs of the module with synchronizer, respectively, the ninth output of the command register is connected to the third input of the synchronizer module, as well as to the input of the first one-shot, the output of which is connected to the third input of the synchronization unit, the first output of which is connected to the first input of the first OR element, the output of which is connected to the sync input of the address register, the second the output of the synchronization unit is connected to the input of the buffer register reset and the second input of the second OR element, the output of which is connected to the sync input of the command register, the tenth output of the command register it is connected to the control inputs of the address switch, the first information inputs from the first to the d-th (d is the number of controller measurements) of the synchronizer module are connected by the first outputs of the synchronizer modules of the neighboring modules from the first to the d-th, the second clock inputs from the first to the d-th are connected to the fifth outputs of the synchronizer modules of adjacent modules from the first to the d-th, the fifth and sixth inputs of the synchronizer module are connected to the coordinate inputs of the module, the seventh information inputs of the synchronizer module from the first to d-th are connected to the third outputs modules of synchronizers of neighboring modules from the first to the d-th, the tenth information input is connected to the input of the module matching vector, the eleventh information input is connected to the input of the maximum number of module barriers, the thirteenth control inputs of the synchronizer module from the first to the d-th are connected to the fourth outputs of the neighboring synchronizer modules modules from the first to the d-th, the fourteenth input of the synchronizer module is connected to the input of the clock pulses of the module, the first outputs of the synchronizer module from the first to the d-th are connected to the first information inputs of the synchronizer modules of neighboring modules from the first to the d-th, the second output of the synchronizer module is connected to the input of the second one-shot and the sync input of the buffer register, the output of which is connected to the reset input of the command register and the second inputs of the synchronization block, the third outputs of the synchronizer module from first to d are connected to the seventh information inputs of synchronizer modules of neighboring modules from the first to the d-th, fifth outputs of the synchronizer module from the first to the d-th are connected to the second inputs of the synchronization modules congestion of adjacent modules from the first to the d-th, the fourth outputs of the synchronizer module from the first to the d-th are connected to the thirteenth inputs of the synchronizer modules of the neighboring modules from the first to the d-th, the first input of the synchronization block is connected to the module start input, the module settings input is connected to the second input of the first OR element, the fourth input of the synchronizer module, and also with the input of the delay element, the output of which is connected to the second input of the second OR element, the synchronizer module contains from the first to fourth blocks of AND elements, a group blocks of OR-NOT elements from the first to the d-th, the first and second block of OR-NOT elements, the first and second block of the OR elements, the block of AND-NOT elements, from the first to the sixth AND element, from the first to the fourth OR element, a group of blocks buffer elements from the first to the rth (p = q / n, where q is the maximum number of barriers in the programs being implemented, and n is the number of physical bits of the parallel logic multicontroller), a block of buffer elements, from the first to the third trigger, the first and second blocks multiplexers, the first and second block of demultiplexers, from first to third decryptors, first and second single vibrators, the first and second register of the current physical discharge of the parallel logical multicontroller, the register of the maximum number of barriers in one physical discharge, the first and second register of the current barrier, the first and second counters, the register of the correspondence vector, the first and second comparators, the mounting block OR from the first to the rth, the first and second group of function value registers, and any block contains from the first to the n-th element, except for blocks of demultiplexers that contain from the first to n +1 demultiplexers, the first inputs of AND elements from the first block are connected to the first inputs of the synchronizer module so that the first bit of the first input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the first element AND in the first block, the second bit of the first input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the second AND element in the first block, and so on until the nth discharge of the first input from the group of first inputs of the synchronizer module, which The nth is connected to the first input from the group of first inputs of the nth element And in the first block, the remaining bits are connected in the same way as the nth from the first to the nth input of the group of first inputs of the synchronizer module, which is connected to the nth inputs from the group of first inputs a block of elements And, the outputs of which are connected to the information inputs of the first block of demultiplexers in such a way that the output of the first element And from the first block is connected to the information input of the first demultiplexer from the first block, the output of the second element And from the first block is connected n to the information input of the second demultiplexer from the first block, and the output of the nth element And from the first block is connected to the information input of the n-th demultiplexer from the first block, the first bits of the outputs of the demultiplexers from the first block are connected to the information input of the first register from the first group of value registers functions, the second bits of the outputs of the demultiplexers from the first block are connected to the information input of the second register from the first group of function value registers and so on until the rth discharge of the outputs of the demult plexors from the first block, which is connected to the information input of the r-th register from the first group of function value registers, the first bit of the n + 1st demultiplexer from the first block is connected to the clock input of the first register from the first group of function value registers, the second output is n + 1- of the first demultiplexer from the first block is connected to the second input sync input from the first group of function value registers and so on until the rth discharge of the n + 1st demultiplexer from the first block, which is connected to the rth register sync input from the first group py registers of function values, from the first to the n-th digits of the output of the first register of the first group of registers of function values are connected to the first bits of the information inputs from the first to the n-th multiplexers of the first block, respectively, from the first to the n-th digits of the output of the second register of the first group of registers function values are connected to the second bits of the information inputs from the first to the n-th multiplexers of the first block, respectively, and so on until the first to the n-th bits of the output of the r-th register of the first group of function value registers, which are connected to the r-bits of the information inputs from the first to the n-th multiplexers of the first block, respectively, the outputs from the first to the n-th multiplexers are connected to the first inputs from the first to the nth elements of the second block, respectively, as well as to the first and second inputs from the first to the n-th elements OR NOT the first block, respectively, the outputs of which are connected to the information inputs from the first to the n-th buffer elements of the first block, the outputs of which are connected to the first and second inputs of all elements OR NOT from the group of blocks of elements LITTLE, the group of second inputs of the third element And is connected to the group of second inputs of the synchronizer module, the output of the third element And is connected to the input of the first one-shot, the output of which is connected to the information input of the n + 1st demultiplexer of the first block of demultiplexers, to the input of the increment of the first counter, as well as to the second input of the third OR element, the output of which is connected to all outputs of the fifth group of outputs of the synchronizer module, the third input of the synchronizer module is connected to the clock input of the third trigger, the fourth input The synchronizer module is connected to all reset inputs of the first and second groups of all function value registers, the first trigger, the second trigger, the first and second register of the current physical discharge of the parallel logic multicontroller, the register of the maximum number of barriers in one physical discharge, the first and second register of the current barrier, the first and the second counter, the register of the correspondence vector, as well as the first input of the first OR element, the output of which is connected to the reset input of the third trigger, direct output which is connected to the first inputs of all AND elements of the third block of AND elements, to the first input of the second AND element, as well as to the first input of the first AND element, the output of which is connected to the control input of the second decoder, the installation input of the first trigger is connected to the fifth input of the synchronizer module, direct the output of the first trigger is connected to all control inputs of the buffer elements of the block of buffer elements, as well as to the first input of the sixth element AND, the output of which is connected to the first input of the fourth OR, the output of which is it is connected to all fourth outputs of the synchronizer module, the input of the installation of the second trigger is connected to the sixth input of the synchronizer module, the direct output of the second trigger is connected to the second inputs of all elements AND of the fourth block of elements AND, as well as the first input of the fifth element And, the output of which is connected to the first input of the third OR element, the group of blocks of elements OR-NOT connected to the group of seventh inputs so that the first block in the group of blocks of elements OR-NOT connected to the first input from the group of seventh inputs, and the first time the input poison is connected to the first and second input of the first element in the first block of the group of block blocks of elements OR NOT, the second bit of the input is connected to the first and second input of the second element in the first block of the group of blocks of elements OR NOT, and so on until the n-th bit of the input which is connected to the first and second input of the nth element in the first block of the group of blocks of elements OR-NOT, the remaining inputs of the blocks on the nth block of elements OR-NOT connected in the same way, the outputs of the group of blocks of elements OR-NOT connected to the block of elements AND- NOT in such a way that exits with the first to the nth first block in the group of blocks of elements OR are NOT connected to the first inputs from the first to the n-th elements of NAND in the block of elements AND-NOT, the outputs from the first to the nth second block in the group of blocks of OR NOT connected to the second inputs from the first to the n-th elements AND-NOT in the block of elements AND-NOT and so on, up to the n-th block in the group of blocks of elements OR-NOT, whose outputs from the first to the n-th are connected to n the inputs from the first to the n-th elements AND-NOT in the block AND-NOT elements, the outputs of which are connected to the information inputs of the second block of demultiplexers so that the output of the first AND-NOT element from the block is connected to the information input of the first demultiplexer from the block, the output of the second AND-NOT element from the block is connected to the information input of the second demultiplexer from the second block, and the output of the nth AND-NOT element from the block connected to the information input of the nth demultiplexer from the block, the first bits of the outputs of the demultiplexers from the second block are connected to the information inputs of the first register from the second group of value registers.  functions, the second bits of the outputs of the demultiplexers from the second block are connected to the information inputs of the second register from the second group of function value registers and so on until the rth category of the outputs of the demultiplexers from the second block, which is connected to the information inputs of the second register from the second group of function value registers , the first bit of the n + 1st demultiplexer from the second block is connected to the sync input of the first register from the second group of function value registers, the second n + 1st demultiplexer from the second block is connected to to the input terminal of the second register from the second group of function value registers and so on until the rth digit of the n + 1st demultiplexer from the second block, which is connected to the clock input of the rth register from the second group of function value registers, from the first to the n-th digit of the output the first register of the second group of function value registers are connected to the first bits of the information inputs from the first to the n-th multiplexers of the second block, respectively, the first to the n-th bits of the output of the second register of the second group of function value registers are connected to the second bits of information inputs from the first to the n-th multiplexers of the second block, respectively, and so on until the first to the n-th bits of the output of the rth register of the second group of function value registers, which are connected to the r-bit bits of information inputs from the first to n- of the second multiplexers of the second block, respectively, the outputs from the first to the n-th multiplexers of the second block of multiplexers are connected to the second inputs from the first to the nth elements of the third block of AND elements, to all third outputs of the synchronizer module, to the first and second inputs I will give from the first to the nth elements of the second block of OR elements, the outputs of which are connected to the first inputs from the first to the n-th elements of the fourth block of AND elements, the outputs of which are connected to the first inputs from the first to nth elements of the first block of OR elements the outputs of which are connected to the third inputs from the first to the nth elements of the first block of AND elements, the inverse output of the second trigger is connected to the second inputs from the first to nth elements of the first block of OR elements, as well as to the first input of the third AND element, information input first p the histogram of the current physical discharge of the parallel logic multicontroller is connected to the eighth input of the synchronizer module, the senior bit of the eighth input of the synchronizer module is connected to the clock input of the first register of the current physical discharge of the parallel logic multicontroller, the output of which is connected to the information input of the second decoder, the outputs of which are from the first to the nth connected to the second inputs from the first to the n-th elements of the second block of OR elements, the outputs of which are connected to the second inputs with the first by the nth elements of the first block of AND elements, the information input of the second register of the current physical discharge of the parallel logic multicontroller is connected to the ninth input of the synchronizer module, and the highest bit of the eighth input of the synchronizer module is connected to the clock input of the second register of the current physical discharge of the parallel logic multicontroller, the output of which is connected to the information input of the third decoder, the outputs of which from the first to the nth are connected to the third inputs from the first to the nth electronic elements of the third block of AND elements, the outputs of which are connected to the inputs of the second OR element, the output of which is connected to the second output of the synchronizer module, as well as to the input of the first OR element, the information input of the correspondence vector register is connected to the tenth input of the synchronizer module, and the senior bit of the tenth input of the module the synchronizer is connected to the sync input of the register of the correspondence vector, the outputs of which are connected to the information inputs of the group of blocks of buffer elements in such a way that from the first to the nth bit the first exit of the register of the correspondence vector is connected to the information inputs from the first to the nth buffer elements of the first block of the group of blocks of buffer elements, the second to the rth outputs of the register of the correspondence vector are connected to the information inputs from the second to the rth blocks of the group of blocks of buffer elements , the outputs of the group of blocks of buffer elements are switched by an OR block, the outputs of which from the first to the nth are connected to the second inputs from the first to the n-th element of the first block of AND elements, the information input is register The maximum number of barriers in one physical discharge is connected to the eleventh input of the synchronizer module, the highest bit of the eleventh input of the synchronizer module is connected to the clock input of the maximum number of barriers register in one physical discharge, the output of which is connected to the information input of the second counter, as well as the information input of the first counter, the output of which is connected to the information input of the first decoder, control inputs from the first to n + 1st demultiplexers of the first block of multiplexers, to the control inputs from the first to the n-th multiplexers of the first block of multiplexers, as well as to the first information input of the first comparator, the output of which is connected to the second input of the first element And, from the first to the rth output of the first decoder are connected to the control inputs from the first on the rth blocks of the group of blocks of buffer elements, the output of the second counter is connected to the control inputs from the first to n + 1-th demultiplexers of the second block of demultiplexers, to the control inputs from the first to n-th multiplexers of the second OK multiplexers, as well as to the second information input of the second comparator, the output of which is connected to the second input of the second element And, the output of which is connected to the control input of the third decoder, the information input of the first register of the current barrier is connected to the twelfth input of the synchronizer module, the senior bit of the eighth input of the module synchronizer is connected to the sync input of the first register of the current barrier, the output of which is connected to the second information input of the first comparator, a group of second inputs the fourth element And is connected to the group of thirteenth inputs of the synchronizer module, the output of the fourth element And is connected to the input of the second one-shot, the output of which is connected to the information input of the n + 1st demultiplexer of the second block of demultiplexers, to the input of the increment of the second counter, and also to the second input of the fourth element OR, the inverse output of the first trigger is connected to the first input of the fourth AND element, as well as to the second inputs from the first to the nth element of the second block of AND elements, the outputs of which are connected to all the outputs of the synchronizer module, the second inputs of the fifth and sixth element AND are connected to the fourteenth input of the synchronizer module, the information input of the second register of the current barrier is connected to the fifteenth input of the synchronizer module, and the highest bit of the fifteenth input of the synchronizer module is connected to the sync input of the second register of the current barrier, the output of which is connected the first information input of the second comparator, the logical unit signal is connected to the information input of the third trigger.

The invention is illustrated by drawings, where in FIG. 1 is a functional diagram of a parallel logic multicontroller module (PLMK), FIG. 2 shows a functional diagram of a synchronizer module; FIG. 3 shows a diagram of a synchronization unit; FIG. 4 is a structural diagram of the PLMK, in FIG. 5 shows the formats of (micro) instructions implemented by the PLMK; FIG. Figure 6 presents an illustrative example that explains the principles for implementing parallel algorithms (programs) in PLMK.

The PLMK module (Fig. 1) includes a program memory block 33, an address register 34, an instruction register 35, a logical condition multiplexer 36, an address switch 37, a synchronization block 39, a first 41, a second 42 OR elements, a buffer register 38, an OR 40 element block , the first 43 and the second 23 are single-vibrators, a delay element 44, a synchronizer module 45, the input 56 of the operation code of the module being connected to the first information input of the address switch 37, the output of which is connected to the information input of the address register 34, the output of which is connected to the address input of the memory unit 33 about a frame whose output is connected to the information input of the register of 35 commands, outputs 3.1 of the logical condition code and 3.2 of the modifiable bit of the address of the register of 35 commands are connected to the address and first information inputs of the multiplexer 36 of the logical conditions, the second information input of which is connected to the input 65 of the logical conditions of the module, the output 3.3 register 35 teams combined with the output of the multiplexer 36 logical conditions and is connected to the first input of the block of elements OR 40 and to the information input of the buffer register 38, the output of which is connected it is connected to the second input of the OR block of elements 40. the output of which is connected to the second information input of the address switch 37, the output 3.4 of the command register is connected to the output 58 of the module microoperations, the outputs 3.5, 3.6, 3.7 and 3.8 of the register 35 commands are connected to the eighth, twelfth, ninth and the fifteenth inputs of the synchronizer module 45, respectively, the output 3.9 of the command register is connected to the third input of the synchronizer module 45, as well as to the input of the single-vibrator 43, the output of which is connected to the third input of the synchronization block 39, the first output of which is connected to the first input of the OR element 41, the output of which is connected to the clock input of the address register 34, the second output of the synchronization unit 39 is connected to the reset input of the buffer register 38 and the second input of the OR element 42, the output of which is connected to the clock input of the register 35 commands, the output 3.10 of the command register 35 is connected to the control inputs of the address switch 37, the information inputs 59 from the first to the d-th synchronizer module 45 are connected by the outputs of the 51 synchronizer modules of the neighboring modules from the first to the d-th, clock inputs 60 from the first to the d-th are connected to the outputs of 54 modules with synchronizers of adjacent modules from the first to the d-th, the inputs 61 and 62 of the synchronizer module 45 are connected to the coordinate inputs of the module, the information inputs 46 of the synchronizer module 45 of the first to d-th are connected to the outputs of 52 synchronizer modules of neighboring modules from the first to d-th, the information input 47 of the synchronizer module 45 is connected to the input of the module correspondence vector, the information input 48 of the synchronizer module 45 is connected to the input of the maximum number of module barriers, the control inputs 49 of the synchronizer module 45 from the first to the dth are connected the outputs of 53 synchronizer modules of adjacent modules from the first to the d-th, the input 50 of the synchronizer module is connected to the input of the clock pulses of the module, the outputs 52 of the synchronizer module 45 of the first to d-th are connected to the information inputs of the 59 synchronizer modules of neighboring modules from the first to d-th , the second output of the synchronizer module 45 is connected to the input of the single-vibrator 23, the output of which is connected to the reset input of the command register 35 and the second inputs of the synchronization block 39, and the sync input of the buffer register 38, the outputs 52 of the synchronizer module 45 from the first to the d-th 46 are connected to the information inputs of 46 modules of synchronizers of neighboring modules from the first to the d-th, outputs 54 of the module 45 of the synchronizer from first to d are connected to the inputs of 60 modules of the 45 modules of synchronizers of neighboring modules from the first to d-th, outputs 53 of the module 45 of the synchronizer are from the first on the d-th are connected to the inputs of 49 modules of synchronizers of neighboring modules from the first to the d-th, the first input of the synchronization block 39 is connected to the input 57 of the start of the module, the input 55 of the module settings is connected to the second input of the OR element 41, the fourth input of the synchronizer module 45, and also with th delay element 44 whose output is connected to the second input of the OR gate 42.

The synchronizer module (Fig. 2) contains blocks 13, 10, 11, 12 of AND elements, block 21 of AND elements, elements of a group of 22 blocks of OR elements, NOT blocks 19, 20 of OR elements, blocks 11, 16 of OR elements , elements 14.1, 14.2, 29, 27, 31, 28 AND, elements 18, 24, 15, 25 OR, group 8 blocks of buffer elements, block 9 buffer elements, triggers 7.1, 7.2, 7.3, blocks 3.1, 3.2 multiplexers, blocks 2.1, 2.2 demultiplexers, decoders 5.1, 5.2, 5.3, single vibrators 30, 26, registers 1.6, 1.7 of the current physical discharge PLMK, register 1.4 of the maximum number of barriers in one physical discharge, registers 1.5, 1.8 current barrier, counters 4.1, 4.2, correspondence vector register 1.3, comparators 6.1, 6.2, mounting OR block 32, groups 1.1, 1.2 of function value registers, first inputs of AND elements from the first block of 13 elements AND are connected to the first inputs of the synchronizer module in this way that the first bit of the input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the And 13.1 element in block 13, the second bit of the first input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the element And 13.2 in block 13, and so on until the nth discharge of the first input from the group of first inputs of the synchronizer module, which is connected to the first input from the group of first inputs of the element And 13.n in block 13, the remaining bits are connected in the nth the first through the dth input of the group of first inputs of the synchronizer module, which is connected to the dth inputs from the group of first inputs of the block 13 of AND elements, the outputs of which are connected to the information inputs of block 2.1 of the demultiplexers in such a way that the output of the element And 13.1 from block 13 is connected to demulti information input lexor 2.1.1 from block 2.1, the output of element And 13.2 from block 13 is connected to the information input of the demultiplexer 2.1.2 from block 2.1, and the output of element And 13.p from block 13 is connected to the information input of the demultiplexer 2.1.p from block 2.1, the first the bits of the outputs of the demultiplexers from block 2.1 are connected to the information input of the register 1.1.1 from group 1.1 of the function value registers, the second bits of the outputs of the demultiplexers from block 2.1 are connected to the information input of the register 1.1.2 from the group 1.1 of the register of function values and so on until the rth digit exits dem the multiplexers from block 2.1, which is connected to the information input of register 1.1.p from group 1.1 of function value registers, the first bit of demultiplexer 2.1.n + 1 from block 2.1 is connected to the sync input of register 1.1.1 from group 1.1 of function value registers, the second output of demultiplexer 2.1 .n + 1 from block 2.1 is connected to the sync input of register 1.1.2 from group 1.1 of function value registers and so on until the rth discharge of the demultiplexer 2.1.n + 1 from block 2.1, which is connected to the sync input of register 1.1.p from group 1.1 of registers function values, from the first to the nth digits you the ode of the register 1.1.1 of the group 1.1 of the function value registers are connected to the first bits of the information inputs 3.1.1 to 3.1. of the multiplexers of the block 3.1, respectively, from the first to the n-th bits of the output of the register 1.1.2 of the group 1.1 of the function value registers 1.1 are connected to the second bits information inputs from 3.1.1 to 3.1.p of the multiplexers of block 3.1, respectively, and so on until the first to the n-th digits of the output of register 1.1.p of group 1.1 of function value registers that are connected to the r-th digits of information inputs from 3.1.1 to 3.1.p multiplexers of the block 3.1 respectively Of course, the outputs from 3.1.1 to 3.1.p of multiplexers are connected to the first inputs of AND elements from 10.1 to 10.p of block 10, respectively, as well as to the first and second inputs of OR-NOT elements from 19.1 to 19.p of block 19, respectively, the outputs which are connected to the information inputs of the buffer elements 9.1 through 9.p of block 9, the outputs of which are connected to the first and second inputs of all OR-NOT elements from the group of 22 blocks of OR-NOT elements, the group of the second inputs of the AND element 29 is connected to the group of the second inputs of the module synchronizer, the output of the element And 29 is connected to the input of the single vibrator 30, the output of which is connected to the information input of the demultiplexer 2.1.p block 2.1 of the demultiplexers, to the input of the increment counter 4.1, and also to the second input of the OR element 15, the output of which is connected to all outputs of the fifth group of outputs of the synchronizer module, the third input of the synchronizer module is connected to the trigger synchronization input 7.3 , the fourth input of the synchronizer module is connected to all reset inputs of group 1.1, 1.2 of the function value registers, trigger 7.1, trigger 7.2, registers 1.6, 1.7 of the current physical discharge of the PLMK, register 1.4 of the maximum number barriers in one physical category, registers 1.5, 1.8 of the current barrier, counters 4.1, 4.2, register 1.3 of the correspondence vector, as well as to the first input of OR element 18, the output of which is connected to the reset input of trigger 7.3, whose direct output is connected to the first inputs of all elements AND block 11 elements AND, the first input of the element And 14.2, as well as the first input of the element And 14.1, the output of which is connected to the control input of the decoder 5.2, the input of the trigger setting 7.1 is connected to the fifth input of the synchronizer module, the direct output of the trigger 7.1 is connected to all with the control inputs of the buffer elements of block 9 of the buffer elements, as well as with the first input of the AND element 28, the output of which is connected to the first input of the OR element 25, the output of which is connected to all the fourth outputs of the synchronizer module, the trigger input 7.2 is connected to the sixth input of the synchronizer module, the direct output of trigger 7.2 is connected to the second inputs of all AND elements of block 12 of AND elements, as well as the first input of AND 31, the output of which is connected to the first input of OR element 15, the group of 22 blocks of OR elements is NOT connected to the load seventh inputs in such a way that block 22.1 in group 22 of the block of elements OR-NOT connected to the first input from the group of seventh inputs, the first bit of the input connected to the first and second input of element 22.1.1 in block 22.1 of group 22 of the block of elements OR-NOT , the second bit of the input is connected to the first and second input of the element 22.1.2 in the block 22.1 of the group 22 of the blocks of elements OR-NOT, and so on until the n-th digit of the input, which is connected to the first and second input of the element 22.1.n in the first block 22.1 groups of 22 blocks of elements OR NOT, the remaining inputs of the blocks on the block 22.a1 elem nts OR are NOT connected in the same way, the outputs of group 22 of the blocks of elements OR are NOT connected to the block 21 of elements AND NOT in such a way that the outputs from the first to the n-th block 22.1 in group 22 of blocks of elements OR are NOT connected to the first inputs of the elements AND -NOT in block 21 of AND-NOT elements from 21.1 to 21.n, outputs from the first to n-th block 22.2 in the group of blocks of OR-NOT elements are connected to the second inputs of AND-NOT elements in block 21 of AND-NOT elements from 21.1 to 21.p and so on, until block 22.y in the group of 22 blocks of OR-NOT elements, in which the outputs from the first to the nth are connected to the d-th inputs of the AND-NOT elements from 21.1 to 21.n in the block of AND-NOT elements 21, the outputs of which are connected to the information inputs of the demultiplexer unit 2.2 so that the output of the AND-21.1 element from block 21 is connected to the information input of the demultiplexer 2.2.1 from block 2.2, the output of the element NAND 21.2 from the block is connected to the information input of the demultiplexer 2.2.2 from block 2.2, and the output of the NAND 21.n element from block 21 is connected to the information input of the demultiplexer 2.2.n from block 2.2, the first bits of the outputs of the demultiplexers from block 2.2 are connected to the information inputs of the register 1.2.1 from the group 1.2 registers of function values, the second bits of the outputs of the demultiplexers from block 2.2 are connected to the information inputs of register 1.2.2 from group 1.2 of the registers of values of functions, and so on, until the r-th category of the outputs of demultiplexers from block 2.2, which is connected to the information inputs of register 1.2.р from groups 1.2 of function value registers, the first bit of the demultiplexer 2.2.n + 1 from block 2.2 is connected to the clock input of register 1.2.1 from group 1.2 of the registers of function values, the second demultiplexer 2.1.n + 1 from block 2.1 is connected to the clock input of register 1.2.2 from the group There are 1.2 function value registers and so on up to the nth discharge of the 2.2.n demultiplexer from block 2.2, which is connected to the clock input of register 1.2.p from group 1.2 of the function value registers, from the first to the nth bit of the output of register 1.2.1 of group 1.2 function value registers are connected to the first bits of the information inputs of the multiplexers 3.2.1 to 3.2.n of block 3.2, respectively, from the first to the n-th bits of the output of register 1.2.2 of group 1.2 of the function value registers are connected to the second bits of the information inputs of the multiplexers from 3.2.1 according to 3.2.p block 3.2 corresponds and so on, until the first to the n-th digits of the output of register 1.2.p of group 1.2 of the function value registers 1.2, which are connected to the r-bits of the information inputs of the multiplexers 3.2.1 through 3.2.p of the second block, respectively, the outputs of the multiplexers 3.2. 1 through 3.2.p are connected to the second inputs of the elements 11.1 to 11.n of the block of 11 elements AND, to all third outputs of the synchronizer module, to the first and second inputs from the elements 20.1 to 20.n of the block of 20 elements OR NOT, the outputs of which are connected to the first inputs of the elements from 12.1 to 12.n of the block of 12 elements And, the outputs of which I connect are connected to the first inputs of the elements 16.1 to 16.n of the block 16 of the OR elements, the outputs of which are connected to the third inputs of the elements 13.1 to 13.n of the block 13 of the AND elements, the inverse output of the trigger 7.2 is connected to the second inputs of the elements from 16.1 to 16.n block 16 of the OR elements, as well as to the first input of the element And 31, the information input of the register 1.6 of the current physical discharge of the PLMK is connected to the eighth input of the synchronizer module, the senior bit of the eighth input of the synchronizer module is connected to the clock input of the register 1.6 of the current physical discharge of the PLMK connected to the information input of the decoder 5.2, the outputs of which from the first to the nth are connected with the second inputs of the elements from 17.1 to 17.n of the block of 17 elements OR, the outputs of which are connected to the second inputs of the elements from 13.1 to 13.n of the block of 13 AND elements, the information input of the register 1.7 of the current physical discharge of the PLMK is connected to the ninth input of the synchronizer module, and the senior bit of the eighth input of the synchronizer module is connected to the sync input of the register 1.7 of the current physical discharge of the PLMK, the output of which is connected to the information input of the decoder 5.3, whose outputs from the first to the nth are connected to the third inputs of the elements 11.1 to 11.n of the block of 11 AND elements, the outputs of which are connected to the inputs of the OR element 24, the output of which is connected to the second output of the synchronizer module, as well as to the input of the element OR 18, the information input of the register 1.3 of the correspondence vector is connected to the tenth input of the synchronizer module, and the highest bit of the tenth input of the synchronizer module is connected to the clock input of the register 1.3 of the correspondence vector, the outputs of which are connected to the information inputs of group 8 s of buffer elements in such a way that from the first to the n-th bit of the first output of the register 1.3, the correspondence vector is connected to the information inputs of the buffer elements from 8.1.1 to 8.1. block 8.1 of the group of 8 blocks of buffer elements, from the second to the rth outputs of the register correspondence vectors are connected to the information inputs of a group of 8 blocks from 8.2 to 8.p of buffer elements in the same way, the outputs of a group of 8 blocks of buffer elements are switched by a mounting OR block 32, the outputs of which are connected to the second inputs of elements 13.1 through 13.n of a block of 13 AND elements, info the rotation input of the register 1.4 of the maximum number of barriers in one physical discharge is connected to the eleventh input of the synchronizer module, and the highest bit of the eleventh input of the synchronizer module is connected to the clock input of register 1.4 of the maximum number of barriers in one physical discharge, the output of which is connected to the information input of counter 4.2, as well as the information the input of the counter 4.1, the output of which is connected to the information input of the decoder 5.1, the control inputs of the demultiplexers from 2.1.1 to 2.1.n of the block 2.1 demul typelexers, to the control inputs of the multiplexers 3.1.1 to 3.1.n of the block 3.1 of multiplexers, as well as to the first information input of the comparator 6.1, the output of which is connected to the second input of the element And 14.1, from the first to the rth output of the decoder 5.1 are connected to the control inputs blocks from 8.1 to 8.p of group 8 blocks of buffer elements, the output of counter 4.2 is connected to the control inputs of demultiplexers 2.2.1 to 2.2.n of block 2.2 of demultiplexers, to the control inputs of multiplexers from 3.2.1 to 3.2.n of block 3.2 of multiplexers, and also to the second information input to omparator 6.2, the output of which is connected to the second input of AND 14.2, the output of which is connected to the control input of the decoder 5.3, the information input of register 1.5 of the current barrier is connected to the twelfth input of the synchronizer module, and the highest bit of the eighth input of the synchronizer module is connected to the clock input of register 1.5 of the current barrier, the output of which is connected to the second information input of the comparator 6.1, the group of second inputs of the And 27 element is connected to the group of thirteenth inputs of the synchronizer module, the output of the And 27 element is connected is connected to the input of the one-shot 26, the output of which is connected to the information input of the demultiplexer 2.2.n + 1 of the block 2.2 of the demultiplexers, to the input of the increment of the counter 4.2, as well as to the second input of the OR element 25, the inverse output of the trigger 7.1 is connected to the first input of the And element, and to the second inputs from the first to the n-th element of the second block of elements And 29, the outputs of which are connected to all the first outputs of the synchronizer module, the second inputs of the elements And 15 and 25 are connected to the fourteenth input of the synchronizer module, the information input of the register 1.8 of the current b Riera coupled to a fifteenth input synchronizer unit, the most significant bit of the fifteenth input synchronizer module is connected to the clock terminal of register 1.8 of the current barrier, the output of which is connected to the first data input of the comparator 6.2, to the information input 7.3 is connected trigger signal logic one.

The structure of the synchronization unit 39 (Fig. 3) does not differ from the prototype.

General features of the functional organization of the proposed PLMK are as follows.

PLCM is formed from many similar modules (controllers), combined into a matrix structure (Fig. 4). Each PLMK module contains a programmable program memory and has many input and output channels for connecting to other similar modules and exchanging control information. The modules are identified by coordinate numbers of the form ij, where i and j make sense, respectively, of the row and column numbers of the matrix structure (hereinafter, the module with the number ij is referred to as the ij-th module or module m _ij ).

PLMK is used to manage complex objects whose behavior is described by a set of programs and involves the parallel flow of processes. The software package implemented by PLMK is divided into many parallel and sequential sections (branches) that are distributed between different modules. Each module implements a subset of the plots.

During the execution of program sections, the PLMK modules process two types of commands: operational and communication. Operational teams that have the format F ₂ (see Fig. 5) provide the issuance of control actions on the control object and initiate the execution of the required micro-operations. Communication teams having the format F ₃ (see Fig. 5) are used to organize the interaction and coordination of various modules, including the launch of branches assigned to other modules (inter-module transfer of control), and barrier synchronization.

(где е - порядковый номер этого участка для i.j-ого модуля, а k - номер программы) этому участку ставится в соответствие номер предшествующему ему барьера a_t; а если активизируемому участку предшествует только один участок программы, то барьер a_t считается фиктивным. Запуск участка

происходит после достижения барьера всеми модулями, т.е. когда модули завершили выполнение предшествующих барьеру участков программы.As in the prototype, in the PLMK under consideration, the intermodular control transfer is absent explicitly, in fact, only the synchronization procedure is performed. In this case, the launch of program sections executed by various modules occurs subject to the corresponding synchronization rules. For example, the launch of sections immediately following the set of other (parallel) sections is impossible without the completion of all sections of this set (condition for reaching the barrier). When starting sections following only one section, the termination of this section is a condition. To set the moment of activation of a certain section

(where e is the serial number of this section for the ij-th module, and k is the program number) this section is associated with the number of the barrier a _t preceding it; and if only one section of the program precedes the activated section, then the barrier a _t is considered fictitious. Site Launch

occurs after the barrier is reached by all modules, i.e. when the modules completed the execution of the program sections preceding the barrier.

начала следующего (е+1-ого) участка, закрепленным за модулем m_i.j, указывается в последней команде предыдущего участка программы, закрепленным за этим же модулем m_i.j. Для задания адресов начальных участков модулей

используются команды настройки формата Ф₁ (фиг. 5), где «НРМ» означает номер разряда модуля, т.е. номер физического разряда модуля ПЛМК, в котором находится барьер, а «НБ» - непосредственно номер барьера. Таким образом номер барьера задается двумя значениями: номером разряда и номером барьера. Это происходит потому, что модуль может выполнять несколько барьеров одновременно. За каждым модулем ПЛМК закрепляется Q таких команд, Q - число программ реализуемых ПЛМК(число программ в реализуемом комплексе). Каждая из q команд настройки определяет адрес

первый команды, т.е. адрес первого участка, закрепленного за модулем m_i.j. Следует заметить, что если m_i.j не участвует в процессе выполнения k-й программы, то команда Ф₁ полностью состоит их нулей. Команды Ф₁ размещаются в блоке 1 памяти программ (фиг. 1) по начальным адресам от 1 до Q включительно. Команда настройки, а следовательно, и реализуемая программа однозначно задается адресом при обращении к блоку 1.As in the prototype, in the proposed PLMK, control reception addresses are generated directly by the modules that implement the triggered sections (control receiver modules) as a result of self-tuning. Address

the beginning of the next (e + 1st) section assigned to the module m _ij is indicated in the last command of the previous section of the program assigned to the same module m _ij . To set the addresses of the initial sections of the modules

commands for setting the format Ф _{1 are used} (Fig. 5), where "НРМ" means the discharge number of the module, i.e. the number of the physical discharge of the PLMK module in which the barrier is located, and "NB" is the barrier number itself. Thus, the barrier number is set by two values: the discharge number and the barrier number. This is because the module can execute several barriers at the same time. Each module of the PLMK is assigned Q such commands, Q is the number of programs implemented by the PLMK (the number of programs in the implemented complex). Each of the q configuration commands defines an address

first team i.e. the address of the first section assigned to the module m _ij . It should be noted that if m _{ij is} not involved in the execution of the k-th program, then the command Ф ₁ consists entirely of zeros. Commands Ф ₁ are located in block 1 of the program memory (Fig. 1) at the starting addresses from 1 to Q inclusive. The configuration command, and therefore the program being implemented, is uniquely set by the address when accessing block 1.

The synchronization process of parallel sections in the proposed PLMK consists in the distribution and interrogation of signals to complete many parallel sections. Each such signal propagates in a separate synchronization channel, which corresponds to one barrier. The synchronization channel is a set of elements (synchronizer modules) of various PLMK modules and corresponding links that ensure the synchronization process of a certain set of parallel sections.

As in the prototype, in the considered PLMK synchronization channels are divided into groups. However, unlike the prototype, in which only one group of channels is active at a time, within which the signals propagate independently and in parallel, in the proposed technical solution, two groups of channels can work simultaneously at once. Changing channel groups occurs cyclically.

где

n_k - число барьеров в k-й программе.To ensure synchronization of arbitrary sets of parallel sections, a vector is assigned to each PLMK module, which sets the correspondence between the set of program barriers and this module. The multicontroller module m _ij , in the general case, corresponds to Q different vectors, each of which corresponds to a certain program. The correspondence vector for the module m _ij and the kth program has the form

Where

n _k is the number of barriers in the k-th program.

, если за модулем m_i.j закреплен некоторый участок программы, завершающийся q-м барьером;

если модуль m_i.j не реализует ни одного участка, завершающегося q-м барьером, или q-й барьер отсутствует в k-й программе (что возможно при n_k<q)The value of the component of the vector S ^ij (k) is determined as follows:

if the module m _{ij is} assigned a certain section of the program ending with the qth barrier;

if the module m _ij does not realize a single segment ending with the qth barrier, or the qth barrier is absent in the kth program (which is possible with n _k <q)

, завершающихся q-м барьером, осуществляется на основе распространения сигнала d_q в q-м канале синхронизации. Сигнал d_q формируется модулем m_1.1 (левым верхним). В исходном состоянии d_q=0 (параллельные участки не завершены) и, следовательно,

Multiple Site Sync

ending with the qth barrier is based on the propagation of the signal _q d in the qth synchronization channel. Signal d _q is generated by module m _1.1 (upper left). In the initial state, d _q = 0 (parallel sections are not completed) and, therefore,

The process of barrier synchronization includes two phases, the formation of a sign of completion of synchronized sections and the transfer of this sign to all PLMK modules.

от модуля m_1.1 вниз вправо через все модули ко всем крайним правым и крайним нижним модулям вплоть до модуля m_M.N (см. фиг. 3).The first of these phases begins with signal propagation.

from the module m _1.1 down to the right through all modules to all the rightmost and lowermost modules up to the module m _MN (see Fig. 3).

через модуль m_i.j происходит следующим образом. Если

то появление единичных сигналов

на верхнем и левом входах модуля m_i.j обуславливает формирование единичного сигнала на его выходе. Если

, то формирование сигнала

на выходе модуля m_i.j происходит только при условии завершения участка

, сходящегося в q-м барьере и реализуемого модулем m_i.j.Signal propagation

through the module m _ij occurs as follows. If

then the appearance of single signals

on the upper and left inputs of the module m _ij causes the formation of a single signal at its output. If

then signal generation

at the output of the module m _ij occurs only if the section is completed

converging in the qth barrier and implemented by the module m _ij .

определяется значением сигнала

если участок

завершен;

в противном случае. В случае если участок

не завершен, на выходе модуля m_i.j устанавливается нулевой сигнал. Данный сигнал формирует нулевые сигналы на выходах всех модулей, расположенных не выше и не левее модуля m_i.j. На входе модуля m_M.N (правого нижнего, см. фиг. 3), соответственно, также будет нулевой сигнал. Как только происходит завершение участка

единичный сигнал

передается на выход модуля m_i.j и поступает в модули m_i+1.j и m_i.j+1.Site Condition

determined by the value of the signal

if the plot

completed;

otherwise. In case the site

not completed, at the output of the module m _ij a zero signal is set. This signal generates zero signals at the outputs of all modules located not higher and not to the left of the module m _ij . At the input of the module m _MN (lower right, see Fig. 3), respectively, there will also be a zero signal. As soon as the completion of the site

single signal

is transmitted to the output of the module m _ij and enters the modules m _{i + 1.j} and m _{i.j + 1} .

пройдет на входы модуля m_M.N и будет передан в остальные модули, расположенные выше правее. Таким образом, формируется сигнал d_q=1, сообщающий об окончании синхронизируемых параллельных участков. На этом первая фаза завершается.After completion of all parallel sections of the set B _{q, a} single signal

will pass to the inputs of the module m _MN and will be transferred to the remaining modules located above to the right. Thus, a signal d _q = 1 is generated, reporting the end of synchronized parallel sections. This completes the first phase.

The second phase of synchronization begins with the appearance of a single signal d _q at the output of the module m _MN . This signal propagates (Fig. 3) from the module m _MN up and left through the PLMK to all the leftmost and leftmost and uppermost modules to the module m _1.1 . During the propagation process, the signal d _q = 1 starts the modules waiting for the completion of the set B _q . The second phase and the synchronization process as a whole fail after the appearance of a zero signal at the output of module m _1.1 .

принадлежность которых определенному модулю задается верхним индексом i.j. В рассматриваемый алгоритм входят барьеры а₁, а₂, …, а₁₀; барьеры а₈, а₉, а₁₀ являются фиктивными, поскольку им предшествует только один участок программы. Пары барьеров а₂ и а₈, а₃ и а₄, а₅ и а₉, а₁₀ и а₆ являются параллельными и синхронизируются независимо. ПЛМК, реализующий данный алгоритм, имеет вид матрицы с конфигурацией 3×3 модуля.The principles of organizing intermodular control and synchronization transfer in the proposed PLMK are illustrated by an example of the implementation of the parallel logic control algorithm shown in FIG. 5a. The algorithm includes 20 parallel and sequential sections

the belonging of which to a certain module is given by the superscript ij. The considered algorithm includes barriers a ₁ , a ₂ , ..., a ₁₀ ; barriers a ₈ , a ₉ , and ₁₀ are fictitious, since they are preceded by only one section of the program. The pairs of barriers a ₂ and a ₈ , ₃ and a ₄ , ₅ and a ₉ , ₁₀ and a ₆ are parallel and synchronize independently. The PLMK implementing this algorithm has the form of a matrix with a configuration of 3 × 3 modules.

а также номера барьеров a_t, после достижения которых должен быть обеспечен запуск соответствующих модулей, представлены на фиг. 6б. В соответствии с данной таблицей запуск модулей m_1.1, m_3.2 и m_3.3 происходит после выполнения барьера а₁, т.е. после завершения участка

запуск модуля m_1.2 осуществляется после достижения барьера а₈, т.е. после завершения участка

и т.д. Модуль m_2.2 активизируется непосредственно в момент запуска ПЛМК независимо от состояния других модулей, поскольку реализует начальный последовательный участок алгоритма

Module configuration table that defines the addresses of the initial sections

as well as the numbers of barriers a _t , after reaching which the launch of the corresponding modules must be ensured, are presented in FIG. 6b. In accordance with this table, the launch of the modules m _1.1 , m _3.2 and m _3.3 occurs after the execution of the barrier a ₁ , i.e. after completion of the site

module m _{1.2 is} launched after reaching barrier a ₈ , i.e. after completion of the site

etc. Module m _{2.2 is} activated immediately at the time of launching the PLCM, regardless of the state of other modules, since it implements the initial sequential section of the algorithm

модуль m_1.2 - участки, сходящиеся в барьерах a₂, a₅ и а₆

и т.д.The table of correspondence vectors for the considered algorithm is shown in FIG. 6c. According to this table, module m _1.1 implements sections ending in barriers a ₂ , a ₅ and

module m _1.2 - sections converging in the barriers a ₂ , a ₅ and a ₆

etc.

The processes of synchronization and launching parallel sections are described in more detail below when considering the operation of the PLMK.

The purpose of the elements and blocks of the logical multicontroller module (Fig. 1) 38, 40, 37.41, 34, 35, 33, 36, 42, 44, 39, 43, 23 does not differ from the prototype.

The purpose of the remaining elements and blocks is as follows.

The synchronizer module 45 serves to implement synchronization of parallel sections.

The purpose of the elements of the synchronizer module 45 is as follows.

Triggers 7.1 and 7.2 are designed to store values of coordinate attributes. The state of these triggers is determined during the initialization of the modules and stored throughout the entire time.

Trigger 7.3 serves to fix a status sign of a parallel branch executed by the current module. Trigger 7.3 is set to one whenever the branch completes, and the moment the current module is activated after waiting for the completion of the barrier is reset to zero.

Register 1.3 bit matching vector is used to store the matching vector. The contents of register 1.3 remain unchanged throughout the entire execution of programs.

Register 1.4 of the maximum number of barriers in one physical category is intended to store the maximum number of barriers in one physical category of PLMK.

Registers 1.5 and 1.8 of the current barrier are designed to store barrier numbers in the first and second phase of synchronization, respectively.

Blocks of demultiplexers 2.1 and multiplexers 3.1 provide the connection of certain bits of the block of registers 1.1 at the time of writing / reading the values of the corresponding function in the first phase of synchronization.

The blocks of demultiplexers 2.2 and multiplexers 3.2 similarly commute the bits of the block of registers 2.2 in order to write / read the value of the corresponding function in the second phase.

Counters 4.1 and 4.2 with a programmable conversion factor are introduced to organize sequential enumeration of all possible barrier numbers and store their current numbers in the first and second phases of synchronization, respectively.

The decoder 5.1, together with a group of 8 blocks of buffer elements and a block of 32 elements "mounting OR" allows you to generate the value of the components of the correspondence vector.

Comparator 6.1 is used to compare the number of the barrier being performed with the number of the barrier being checked in the first phase of synchronization.

Comparator 6.2 is used to compare the number of the barrier being performed with the number of the barrier being checked in the second phase of synchronization.

Element And 11, together with a single vibrator 23 and element OR 24, serve to form a sign of completion of the program section.

в первой фазе синхронизации.The group of registers 1.1 is used to store the current values of the signals

in the first phase of synchronization.

The group of registers 1.2 is used to store the current values of the signals d _q in the second phase of synchronization.

Registers 1.6, 1.7 of the current physical discharge are intended for fixing the number of the physical discharge of the PLMK, which contains the barrier in the first and second phases of synchronization, respectively.

Decoder 5.2 is used to convert the number of the current physical discharge in the first phase of synchronization.

Decoder 5.3 is used to convert the number of the current physical discharge in the second phase of synchronization.

Block 9 of the buffer elements is intended for switching the output of the block of 19 elements OR NOT with the seventh inputs of the synchronizer module.

Block 10 elements And serves to generate output values of the signals d _q .

Block 13 elements AND element OR 17 are designed to organize the distribution of signals polling the status of the sets of parallel sections from neighboring modules above and to the left of the current.

Element And 14.1 serves to control the operation of the decoder 5.2. Element And 14.2 serves to control the operation of the decoder 5.3.

Block 20 elements OR NOT together with block 12 elements AND, block 16 elements OR are designed to prevent the beginning of the first phase of synchronization before the completion of the second in the previous section of the program.

The OR element 18 is used to generate a trigger reset signal 7.3.

A group of 22 blocks of AND-NOT elements together with a block of 21 AND-NOT elements for organizing the distribution of module start signals awaiting completion of the corresponding sets of parallel sections from neighboring modules to the right and bottom of the current one.

The OR element 15, the And elements 29, 31 and the one-shot 30 are designed to generate clock pulses propagating in the first phase of synchronization.

The OR element 25, the And elements 27, 28 and the single vibrator 26 are used to form clock pulses propagating in the second phase of synchronization.

Consider the process of functioning of PLMK in detail.

Initially, the memory elements (registers, triggers and counters) of all LMC modules are in a state of logical zero. The only exception is register 35, at the output 3.10 of which there is a single signal level, and trigger 62 of synchronization block 39 (Fig. 4). Based on the indicated state of the memory elements, synchronization blocks 39 of all modules are turned off, switches 37 are configured to receive information from inputs 56, and logic zero signals are located at all outputs of the modules.

Before starting work, the PLMK is configured. To this end, a signal of a logical unit is supplied to the input 61 of the module m _MN (Fig. 1). This signal is recorded on the trailing edge of the trigger 7.1 (Fig. 2). The zero signal from the direct output of trigger 7.1 in all other modules turns off the block 9 of the buffer elements, disconnecting the output of the block of 19 elements OR NOT from the group of inputs 46 of the module (Fig. 1). In the module m _MN , on the contrary, block 9 (Fig. 2) is turned on by a single signal from the direct input of trigger 7.1 and the output of block 19 is switched with the group of inputs 46 of the module (Fig. 1). Due to this (and since all the registers of group 1.1 (Fig. 2) are in the zero state) in the module m _MN , units from the block 19 of the OR-NOT elements (Fig. 2) pass to the group of inputs 46 (Fig. 2), which ensures the appearance of units at the output of the block of 21 elements AND NOT. In turn, a single signal from the inverted output of flip-flop 7.1 in all modules except module m _MN opens block 10 of AND elements, making it possible to transfer the values of state functions from block 3.1 of multiplexers to the group of outputs 51 of the module (Fig. 1). Since all the registers of group 1.1 (Fig. 2) are in the zero state, opening the block of 10 elements And at this stage does not affect the state of the outputs of 1 modules (Fig. 1). The zero signal from the inverse output of trigger 7.1 (Fig. 2) in module m _MN closes block 10 of AND elements, blocking the transfer of values of state functions to group 1 of the module outputs (Fig. 1). Since all outputs of group 1 of the module have a zero signal level, blocks of 13 AND elements in all modules give zeros. The zero signal from the direct output of trigger 7.3 blocks the elements And 14.1, 14.2, thereby disabling the decoders 5.2 and 5.3. The same zero signal closes all the elements of the block 11 of AND elements, as a result of which at the output of the OR element 24 a zero signal level is also formed.

Simultaneously with the described actions, a single signal is supplied to the input 62 of the module m _1.1 and recorded in trigger 7.2 (Fig. 2). Since all the registers of group 1.2 are still set to zero, the outputs of the block of multiplexers 3.2 will also be zeros; accordingly, on the outputs of the block of 20 elements OR will NOT appear units. Thus, regardless of the state of trigger 7.2, the block 16 of the OR elements will produce units (at this stage, this state is not significant).

At input 48, the code p _{k of the} number of the maximum number of barriers in one physical discharge is supplied. The value of p _k depends on the number q _{k of} barriers in the programs being implemented and on the number n of physical discharges of PLMK (p _k = q _k / n). The value of p _{k is} recorded in the register 1.4 of the number of the maximum number of barriers in one physical category (Fig. 2) along the trailing edge of the pulse of the highest level of input 48 (Fig. 1). From register 1.4 (Fig. 2), the value of p _k is fixed in the counters 4.1 and 4.2.

(адреса первой команды), а также к определению номера барьера a_t, после достижения которой должен осуществляться запуск модуля m_i.j.Upon completion of the configuration, the configuration of the PLMK modules for the execution of the required (k-th) program begins. Setting the module m _ij to execute the k-th program comes down to setting the address

(addresses of the first command), as well as determining the barrier number a _t , after which the module m _ij should be launched.

The process of configuring the modules for the execution of the k-th program begins with the input to the input 56 of the module m _ij (Fig. 1) operation code (CPC). The CPC, which is the code of the program number (k), is fed through the switch 37 to the information input of the register 34. At the same time, a tuning pulse is supplied to the input 55 of the module. The specified pulse through the element OR 41 is fed to the clock input of the register 34 and the trailing edge fixes the CPC in this register. Next, the CPC from the output of the register 34 is fed to the address input of block 1 and generates at its output a configuration command Ф ₁ (Fig. 5) corresponding to the k-th program.

а на выходах 3.7 и 3.8 формируется коды номеров физического разряда ПЛМК, в котором находится барьер, и барьера непосредственно a_t. На остальных выходах регистра 35 устанавливаются нулевые сигналы. Нулевой сигнал с выхода 3.10 регистра 35 перенастраивает коммутатор 37 на прием информации с выхода блока элементов ИЛИ 40. Поскольку на выходе 3.1 регистра 35 присутствует нулевой код (проверка логических условий в ходе настройки не производится) адрес

без изменений проходит через блок элементов ИЛИ 40. Далее этот адрес передается через коммутатор 37 и устанавливается на информационном входе регистра 34.At the same time, the tuning pulse through the delay element 44 and the OR element 42 (Fig. 1) is transmitted to the sync input of the register 35 and the trailing edge writes the command read from block 1 to the register 35. After fixing the command on the outputs 3.2 and 3.3 of the register 35, the address is formed

and at the outputs 3.7 and 3.8, codes of the numbers of the physical discharge of the PLMK, in which the barrier is located, and of the barrier directly a _{t are} generated. The remaining outputs of the register 35 are set to zero signals. The zero signal from the output 3.10 of the register 35 reconfigures the switch 37 to receive information from the output of the block of elements OR 40. Since the output 3.1 of the register 35 contains a zero code (verification of logical conditions during the configuration is not performed) address

without changes passes through the block of elements OR 40. Next, this address is transmitted through the switch 37 and is installed on the information input of the register 34.

At the same time, the barrier code from the outputs 3.7 and 3.8 is fed to the information inputs of the registers 1.7 and 1.8 (Fig. 2), where they are fixed by the leading edge of the special signal in the high order of the code. For the PLCM module, which implements the initial section of the k-th program, setting the code of the barrier number is not required, since this module starts the program execution immediately at the time of starting the PLCM, regardless of synchronization conditions. Therefore, at the outputs 3.7 and 3.8 of the register 35 (Fig. 1) of the module in question, a zero code is set.

(устанавливается соответствия между модулем) m_i.j и множеством барьеров k-й программы). Вектор подается на вход 47 модуля и заносится в регистр 1.3 (фиг. 2) по переднему фронту специального импульса старшего разряда входа 47 модуля. На этом процесс настройки модуля m_i.j на выполнение k-й программы завершается.Along with the steps described above, the code of the correspondence vector is written

(the correspondence between the module) m _ij and the set of barriers of the k-th program is established). The vector is fed to the input 47 of the module and entered in the register 1.3 (Fig. 2) along the leading edge of the special pulse of the senior bit of the input 47 of the module. This completes the process of tuning the module m _ij to the execution of the k-th program.

The process of setting up the remaining PLMK modules proceeds in a similar way, and the setting of various modules is performed simultaneously. At the inputs 56 of all modules the same CPC is supplied; correspondence vectors for different modules are generally different. As a result of the configuration of each module, the moment of its launch when the k-th program is executed by the network is determined, the corresponding address (the address of the first command) is set, and, in addition, a subset of the barriers of the k-th program is established, in which the sections realized by the module are completed.

After the configuration is completed, the PLMK is launched. To start the network to the input 57 of the module that implements the initial section of the k-th program, a start pulse is applied (Fig. 1). Suppose that the specified module has the number ij (in the example in Fig. 6, this is the module m _2.2 ). The start pulse from the input 57 of the module m _ij is transmitted to the first input of the synchronization unit 39.

Further, this pulse passes through the element OR 59 (Fig. 3), acting on the input of the installation of the trigger 60, translates it into a single state. A single signal from the direct input of the trigger 60 is fed to the input of the generator 61 and allows the formation of a sequence of pulses at its input.

The first pulse from the output of the generator 61 passes through the element And 63 to the first output of the synchronization block (element 63 is opened by a single signal from the direct output of the trigger 62). On the trailing edge of the same pulse, the trigger 62 switches to the zero state and, as a result, blocks the And 63 element, while opening the And 64 element. The next pulse from the output of the generator 61 passes through the And 64 element to the second output of the synchronization block. The third pulse again passes to the first output of the synchronization unit, the fourth to the second, etc. Thus, at the outputs of the synchronization unit 39, two sequences of synchronization signals t ₁ and t _{2 are} shifted relative to each other.

поступающий с выхода коммутатора 37. Адрес

с выхода регистра 34 адреса поступает на вход блока 33 памяти программ и формирует на его выходе первую команду k-й программы.The first pulse t ₁ from the first output of the synchronization block 39 (Fig. 1) through the OR element 41 acts on the clock input of the address register 34, thereby writing the address into it

coming from the output of the switch 37. Address

from the output of the register 34, the address goes to the input of the program memory block 33 and generates the first command of the k-th program at its output.

The first pulse t ₂ from the second output of the synchronization unit 39 passes through the OR element 42, arriving at the clock input of the register 35 commands. The command is recorded from the output of the program memory block 33 to the command register 35. At the same time, the same pulse is fed to the reset input of the buffer register 38 and confirms its zero state. Thus, the module m _ij and the network as a whole begin to execute the k-th program.

завершающийся барьером a_q. Кроме того, будем считать, что одновременно с m_i.j модулем могут функционировать и некоторые другие модули ПЛМК (остальные модули находятся в состоянии ожидания).Further work of the PLCM will be considered under the assumption that the module m _ij performs some (in the general case, not the initial) section of the kth program

ending with a _q barrier. In addition, we assume that at the same time as the m _ij module, some other PLMK modules can function (the rest of the modules are in a standby state).

модуль m_i.j может обрабатывать команды форматов Ф₂, Ф₃ и Ф₄ (фиг. 5). Обработка команды формата Ф₂ соответствует собственно режим выполнения участка программы (Режим А), команда формата Ф₃ определяет режим завершения участка (режим В), а команда Ф₄ задает режим завершения программы в целом (режим С). Рассмотрим работу модуля в приведенных режимах.During the execution of the site

module m _ij can process commands of the formats Ф ₂ , Ф ₃ and Ф ₄ (Fig. 5). Processing a command of format F ₂ corresponds to the actual execution mode of the program section (Mode A), a command of format F ₃ determines the mode of completion of the section (mode B), and command F ₄ sets the mode of completion of the program as a whole (mode C). Consider the operation of the module in the above modes.

Mode A. The command recorded in register 3 has the format Ф ₂ (Fig. 5). In this case, the microoperation code (MO) is generated at the output of 3.4 register 35 (Fig. 1), at the outputs 3.2 and 3.3 the address of the next A _{command is generated} (at the output 3.3 the non-modifiable part, and at the output 3.2 - a modifiable bit of the address of the next command, modifiable at the branch points of programs), at the output 3.1, the code of the interrogated logical condition (LU) is set, and at outputs 3.5-3.10, logical zero signals.

The MO code from the output 3.4 of the register 35 is transmitted to the output 58 of the module and, coming further to the input of the control object, initiates the execution of the required micro-operations. Zero signals from outputs 3.5-3.8 are recorded in the corresponding bits of the registers 1.6, 1.7, 1.5, 1.8 (Fig. 2), respectively. The zero signal from the output 3.9 of the register 35 (Fig. 1) is supplied to the control inputs of the switch 37 and sets it to receive the address of the next command from the output of the block of elements OR 40.

Simultaneously with the operations described is the formation of the next instruction effective address specified address is formed from the next instruction address A _slab modifiable by replacing (younger) discharge interviewee value LU. A new low-order value is generated at the output of the multiplexer 36. The process of generating this value proceeds as follows. A modifiable bit (A _m ) of address A _sl from output 3.2 of register 35 is fed to the first information input of multiplexer 36, and the LN code from output 3.1 is fed to the address input of multiplexer 36. If the LU code is different from zero, then the value of the corresponding LU with input 65 of the module. If the LU code is zero, then the output of the multiplexer 36 receives the value of А _m from the output of 3.2 register 35. The value from the output of the multiplexer 36 in combination with the non-modifiable (senior) part of the address of the next command (A _n ) from the output 3.3 of register 35 form the executive address of the following teams

через блок элементов ИЛИ 40 и открытый коммутатор 37 проходит на информационный вход регистра 34. Очередной импульс синхронизации t₁ с первого выхода блока 39 синхронизации фиксирует адрес

в регистре 34. Адрес

с выхода регистра 34 поступает на адресный вход блока 33 и обеспечивает считывание из блока 33 очередной команды k-й программы. Следующий импульс t2 со второго выхода блока 29 синхронизации через элемент ИЛИ 42 полается на синхровход регистра 35 и записывает в регистр считанную команду.Address

through the OR block 40 and the open switch 37 passes to the information input of the register 34. The next synchronization pulse t ₁ from the first output of the synchronization block 39 fixes the address

in register 34. Address

from the output of the register 34 it goes to the address input of block 33 and provides reading from block 33 of the next command of the k-th program. The next pulse t2 from the second output of the synchronization unit 29 through the OR element 42 is sent to the clock input of the register 35 and writes the read command to the register.

This completes the operation of the module m _ij in mode A. The read command can again be in the format F ₂ or it can be a command in the format F ₃ or F ₄ .

производит самонастройку на выполнение очередного участка k-й программы и переходит в состояние ожидания. В ходе самонастройки модуль m_i.j устанавливает адрес

начала очередного ((е+1)-ого) участка

(здесь е - порядковый номер участка

для модуля m_i.j) и фиксирует номер (t) барьера a _t (после достижения которого должен осуществляться запуск модуля m_i.j).Mode B. The command recorded in the register 35 has the format F ₃ (Fig. 5). In this case, the module m _ij completes the execution of a certain section

performs self-tuning to execute the next section of the k-th program and goes into a standby state. During self-tuning, the module m _ij sets the address

beginning of the next ((e + 1) -th) section

(here e is the serial number of the plot

for the module m _ij ) and fixes the number (t) of the barrier a _t (after reaching which the module m _ij should be launched).

на выходе 3.1 образуется код ЛУ, а на выходах 3.4 и 3.10 устанавливаются сигналы логического нуля. В тоже время на выходе 3.5 регистра 35 формируются номер физического разряда модуля, в котором находится барьер a _q, а на выходе 3.6 регистра 35 номер (q) барьера a _q, завершающий выполненный модулем участок программы

На выходе 3.7 регистра 35 формируются номер физического разряда модуля, в котором находится барьер a _t, а на выходе 3.8 номер (t) барьера a_t, определяющий момент запуска модуля m_i.j (допустимым является случай, когда t=q).At the output 3.9 of register 35, a single mark of the end of the program section (M _ku ) appears, initiating the format of the read command, at the outputs 3.2 and 3.3 of register 35, an address is generated

at the output 3.1, the LU code is generated, and at outputs 3.4 and 3.10, logic zero signals are set. At the same time, at the output of register 3.5, the number of the physical discharge of the module containing the barrier a _{q is formed} , and at the output of register 3.6, the number (q) of the barrier a _q , which completes the program section executed by the module

At the output 3.7 of register 35, the number of the physical discharge of the module in which the barrier a _t is located is formed, and at the output 3.8, the number (t) of the barrier a _t that determines the moment the module m _ij starts (the case when t = q is acceptable).

на выходе 3.6 регистра 35 модуля m_2.2 будет установлен номер барьера а ₁, а на выходе 3.5 физический разряд модуля, в котором выполняется синхронизация барьера a ₁ На выходе 3.8 регистра 35 модуля m_2.2 будет установлен номер барьера а ₂, за которым следует очередной участок

выполняемый модулем m_2.2. На выходе 3.7 регистра 35 будет установлен физический разряд модуля, в котором выполняется синхронизация барьера а ₂. Адрес начала этого участка

будет зафиксирован на выходах 3.2 и 3.3 регистра 35. После завершения участка

на выходе 3.6 регистра 35 модуля m_2.2 будет установлен номер барьера а ₄, а на выходе 3.5 физический разряд модуля, в котором выполняется синхронизация барьера а ₄. На выходе 3.8 регистра 35 модуля m_2.2 будет установлен номер барьера а ₇, за которым следует очередной участок

выполняемый модулем m_2.2. На выходе 3.7 регистра 35 будет установлен физический разряд модуля, в котором выполняется синхронизация барьера а ₇. Аналогичным образом происходит самонастройка других модулей.In the example of FIG. 6 after completing the site

at the output 3.6 of the register 35 of the module m _2.2 , the barrier number a ₁ will be set, and at the output 3.5 the physical discharge of the module in which the barrier is synchronized a ₁ At the output 3.8 of the register 35 of the module m _{2.2 the} number of the barrier a ₂ will be set, followed by the next section

performed by module m _2.2 . At the output 3.7 of register 35, the physical discharge of the module in which the synchronization of barrier a ₂ is performed will be set. Start address of this site

will be fixed at outputs 3.2 and 3.3 of register 35. After completion of the section

the output register 35 of the module 3.6 m _2.2 is set as the number of the barrier _4, and the output 3.5 Physical discharge unit, wherein the barrier synchronization is executed and _4. At the output 3.8 of register 35 of module m _2.2 , the barrier number a ₇ will be set, followed by the next section

performed by module m _2.2 . At the output 3.7 of register 35, the physical discharge of the module in which the synchronization of barrier a ₇ is performed will be set. Similarly, the self-tuning of other modules occurs.

The code numbers and the barrier ₇ with 3.6 exit register 35 is supplied to an information input of the register 1.5 (FIG. 2), where the fixed single special signal MSB of the code on the leading edge. At the same time, the code of the physical discharge of the module in which the barrier a _{q is} synchronized, from the output 3.5 of the register 35 (Fig. 1) is supplied to the information input of the register 1.6 (Fig. 2), where it is similarly fixed by a single signal of a special high order of this code along the front to the front. In turn, the barrier number code a _t from the output 3.8 of register 35 (Fig. 1) is fed to the information input of register 1.8 (Fig. 2), where it is fixed by a single signal of a special high-order bit of this code on the leading edge. At the same time, the code of the physical discharge of the module in which the barrier a _{t is} synchronized, from the output 3.7 of register 35 (Fig. 1) is fed to the information input of register 1.7 (Fig. 2), where it is similarly fixed by a single signal of the special high order of this code along the front to the front.

At the same time, the zero signal from the output 3.10 of the register 35 (Fig. 1) configures the switch 37 to receive information from the output of the block of elements OR 40, and the positive difference in signal level that occurs at the output 3.9 of the register 35 acts on the single-shot 43 and forms on it output impulse. This pulse is supplied to the third input of the synchronization block 39 and, then passing to the reset input of the trigger 60 (Fig. 3), switches this trigger to the state of logical zero. The zero signal from the direct trigger 60 turns off the generator 61 and thereby stops the process of generating synchronization pulses t ₁ and t ₂ at the outputs of the synchronization unit 39. Thus, the process of reading commands from block 33 is temporarily stopped (the module enters the standby state).

путем модификации его младшего разряда (A_M) значением логического условия с входа 65 модуля (фиг. 1). Процесс формирования исполнительного адреса протекает так же, как и при работе модуля в режиме А (см. выше). Полученный исполнительный адрес (обозначим его как

поступает на информационный вход буферного регистра 38, а также через блок элементов ИЛИ 40 и коммутатор 37 проходит на информационный вход регистра 34.Simultaneously with the described actions, the executive address of the next command is formed (the address from which the actual start of the module m _ij will occur after reaching the barrier t). The specified address is formed from the address

by modifying its low order (A _M ) with the value of the logical condition from the input 65 of the module (Fig. 1). The process of forming the executive address proceeds in the same way as when the module was in mode A (see above). Received Executive Address (Denote it as

arrives at the information input of the buffer register 38, and also through the block of elements OR 40 and the switch 37 passes to the information input of the register 34.

сходящихся в барьере q.This completes the operation of the module in mode B. Similarly, the completion of other sections of the k-th program, including sections

converging in the barrier q.

, сходящихся в барьере a _q. Будем считать, что участки

распределены между модулями ПЛМК произвольным образом.Consider the work of PLMK in the synchronization mode of a group of parallel sections, as well as the process of starting modules during synchronization. For definiteness, we will consider a specific group of sites

converging in the barrier a _q . We assume that the plots

randomly distributed between the PLCM modules.

The synchronization process of parallel sections converging in the barrier q begins with the generation of waves of clock pulses of the synchronization phase, propagating in straight fronts from module m _1.1 to module m _MN , in module m _1.1 . The signals from the outputs of trigger 7.2 block the And 29 element and open the And 31 element. As a result, a series of clock pulses, which is fed to the input 50 of the module, starts through the And 31, OR 15 elements through the group of outputs 54 (Fig. 1) to the neighboring modules. In the remaining modules, the And element 31 (Fig. 2) will be blocked by the zero state of trigger 7.2 and pulses applied to the input 50 (Fig. 1) of the module will not be accepted. At the same time, the And 29 element (Fig. 2) in these modules will be open. As a result, as soon as all the inputs of the group of inputs of the 60 module (Fig. 1) from the neighboring modules will receive clock pulses, the output of the And 29 element (Fig. 2) the signal level from zero will go to unity and the one-shot 30 will give a new impulse. This pulse through the element OR 15 passed to the group of outputs 54 (Fig. 1) and, similar to that described above, propagate into neighboring modules. This generation of pulses using a single vibrator 30 (Fig. 2) eliminates the influence of random delays in the propagation of clock pulses.

Similarly, the nucleation and propagation of waves in the recovery phase occurs. In this case, the wave source is the module m _MN , and all functions are performed by elements 25-28, taking into account the state of trigger 7.1. The generated pulses are transmitted to the group of outputs 53 of the module (Fig. 1) and propagate in the direction of the module m _1.1 .

The appearance of pulse waves in the phase of synchronization does not yet lead to any changes. Since the zero state of register 1.4 prohibits the operation of counter 4.1, this counter does not respond to pulses at its counter input and at its outputs all zeros are stored. As a result, the blocks of demultiplexers 2.1 and multiplexers 3.1 in all modules receive a zero code at the address input. Passing through the group of demultiplexers 2.1 to the sync input of registers 1.1.1 in all modules, the pulses confirm the zero state of these registers and, accordingly, the zero signal level at the output of the block of multiplexers 3.1.

At the same time, the pulse waves in the recovery phase, acting through the demultiplexer unit 2.2 on the sync inputs of the registers 1.2.1 in all modules, cause a sequential (in the direction from the m _MK module to the m _1.1 module) filling of these registers with units (for further correct operation of the PLMK the state of the register group 1.2 will not be an obstacle). As a result, the signal level is formed at the outputs of the OR-NOT 20 block of all modules. As a result, zeros appear at the outputs of the AND block of 12 elements of all modules. At the outputs of the block of elements OR 16, at the same time, in all modules except m _1.1 , a unit signal level is previously determined due to the zero state of trigger 7.2. In module m _1.1, because of a single trigger 7.2, zeros appear on the outputs of the block of elements OR 16, which confirm the blocking of the block of elements AND 13.

Consider the operation of the module in the indication mode of the end of the parallel branch.

Immediately after executing the last command of format Ф ₃ (Fig. 5) of a parallel branch B _q ending with some barrier a _q , the mark of the end of the program section in the form of a single signal from the output 3.9 of register 35 (Fig. 1) is fed to the trigger sync input 7.3 (Fig. 2 ), thereby translating it into a single state. A single signal from the direct output of this trigger opens the elements And 14.1 and 14.2 and the block of elements And 11. As the value of the counter 4.1 becomes equal to the barrier number of the register 1.5, the comparator 6.1 gives a single signal. This signal passes through the open element And 14.1 and allows the operation of the decoder 5.2. Then, at the output of the decoder, which corresponds to the physical discharge in which the barrier is located, one appears. This unit passes through the corresponding element of the block of elements OR 17 to the element of the same element AND 13. Before the appearance of the unit, at the outputs of the block of elements OR 17 there was a zero signal level taken through the block of buffer elements 8.i from the corresponding discharge of register 1.3.

In all modules, except m _{1.1, the} indicated element of the block of elements And 13 unconditionally opens, which ensures unhindered passage of a single value from the inputs 59 of the synchronizer module (Fig. 1). In the module m _{1.1, the} block of elements AND 13 (Fig. 2) is additionally blocked by the signal from the outputs of the block of elements OR 16 until the block of multiplexers 3.2 in the corresponding discharge produces a zero value.

Now consider the operation of the module in startup mode after the end of the parallel branch.

In this mode, the trigger 7.3 is still in a single state, therefore, the element And 14.2 and the block of elements And 11 are open. As soon as the comparator 6.2 establishes a match between the value of the counter 4.2 and the number of the barrier, which is transmitted from the output of the register 1.8, a signal of a logical unit is generated at its output. This signal through the element And 14.2 acts on the decoder 5.3 and allows its operation. As a result, the discharge number of the PLMK, which contains the barrier coming from register 1.7, is converted to the corresponding unitary code, which leads to the opening of the corresponding element in the block of elements And 11. Since from the corresponding register of group 1.2, through the corresponding multiplexer of block 3.2, the same element block of elements And 11 a unit arrives, block 11 gives a non-zero value and the element OR 24 forms a single signal level, preparing one-shot 23 for operation (Fig. 1).

With the advent of the next wave pulse in the recovery phase at the output of the single-shot 26 (Fig. 2), the registers of group 1.2 switch to a new state corresponding to the barrier number. If at the same time the category of registers corresponding to the current physical category of the PLMK and the barrier number being checked (counter value 4.2) switches to the zero state, then this module received function values from the neighboring modules, which mean that the restoration condition is fulfilled. In this case, at the output of the block of elements AND 11, a zero value appears again and the signal level at the output of the element OR 24 becomes zero. As a result, the one-shot 23 (Fig. 1) will give a start pulse to the module. At the same time, the negative difference at the output of the OR element 24 propagates to the sync input of the buffer register 38 and fixes in this register the module start address generated by the module at the end of the program section (see mode B). The address from the output of the register 38 confirms the information at the output of the block of elements OR 40. In addition, this pulse will reset trigger 7.3 (Fig. 2), blocking the elements And 14.1, 14.2 and the block of elements And 11.

At the same time, the pulse from the output of the one-shot 23 (Fig. 1) is supplied to the second input of the synchronization unit 39 and, passing through the OR element 46 (Fig. 3) to the installation input of the trigger 60, includes a generator 61. Thus, at the outputs of the synchronization block 39 the formation of synchronization pulses t ₁ and t ₂ resumes.

поступающий с выхода регистра 38. Соответственно, указанный адрес сохраняется на информационном входе регистра 34.At the same time, the pulse from the output of the single-shot 23 (Fig. 1) is fed to the reset input of the register 35 and sets it to zero. At all outputs of the register 35, zero signals are generated. As a result, zeros are written to the registers 1.5-1.8 (Fig. 2). The address code at the first input of the block of elements OR 40 (Fig. 1) also becomes zero. However, the output of the block of elements OR 40 still stores the address

coming from the output of the register 38. Accordingly, the specified address is stored on the information input of the register 34.

Адрес с выхода регистра 34 подается на адресный вход блока 33 и обеспечивает считывание первой команды участка е+1. Первый импульс t₂ со второго входа блока 39 синхронизации сбрасывает буферный регистр 38 и, поступая одновременно через элемент ИЛИ 42 на синхровход регистра 35, фиксирует в этом регистре считанную из блока 33 команду. Таким образом, модуль m_i.j приступает к выполнению участка е+1 программы k. Записанная в регистр 35 команда может иметь форматы Ф₂, Ф₃ или Ф₄ (фиг. 5). Соответственно модуль m_i.j может перейти в один из трех возможных режимов - А, В или С.Next, the first pulse t ₁ from the first output of the synchronization block 39 through the OR element 41 is fed to the clock input of the register 34 and writes a address into it

The address from the output of the register 34 is fed to the address input of block 33 and provides the reading of the first command of the section e + 1. The first pulse t ₂ from the second input of the synchronization block 39 resets the buffer register 38 and, simultaneously arriving through the OR element 42 to the sync input of the register 35, fixes the command read from the block 33 in this register. Thus, the module m _ij starts to execute the section e + 1 of the program k. The command recorded in the register 35 may have the formats Ф ₂ , Ф ₃ or Ф ₄ (Fig. 5). Accordingly, the module m _ij can go into one of three possible modes - A, B or C.

Let us consider in more detail the distribution of the values of the indicator functions that determine the state of the module relative to the barrier through the module in the synchronization and recovery phases.

In the synchronization phase, the values of the indicator functions are distributed through the modules along the circuits formed by the block of elements AND 13, the block of demultiplexers 2.1, the group of registers 1.1, the block of multiplexers 3.1 and the block of elements AND 10. In the module m _MN , the block of elements OR-NOT 19 is connected to this process and the block of buffer elements 9, and the block of elements And 10, on the contrary, is closed and does not participate in the transfer of values of indicator functions.

At each moment of time, the registers of group 1.1 contain a set of current values of indicator functions in the synchronization phase for all active barriers, and these values may differ in different modules. So, if in the module m _{ij the} value of the function in a certain category of a certain register is 1, then this means that all modules located no further from the origin than (i: j), including the module m _{ij itself} , have already completed the branches converging in barrier with the corresponding number, or are not at all participants in this barrier. If the value of the function is 0, then this means that the module m _{ij itself} or any module among those located no farther from the origin than m _ij has not yet completed the branches converging in the barrier with a certain number, which is in this physical category PLMK. It is also possible that the value of the function has not yet arrived in the module.

The recording of a new value of the indicator function in the corresponding category of registers 1.1 occurs along the leading edge of the next clock pulse of the wave in the synchronization phase. This pulse from the output of one-shot 30 passes through the demultiplexer 2.1.n + 1 to the sync input of that register of group 1.1, which corresponds to the value of counter 4.1, and fixes in this register a new value of the indicator function, formed by the block of elements 13. 13. This pulse switches the counter 4.1 to interrogation of the next barrier, for which the formation of indicator functions has already begun according to the data from the modules of the previous direct front.

Having reached the module m _MN , the values of the indicator functions in the synchronization phase are inverted by the block 19 and thereby are converted into the corresponding values of the indicator functions in the recovery phase. The obtained values through the block of buffer elements 9 are fed back to the module m _MN to the group of inputs 7 and are used later in the recovery phase.

In the recovery phase, the values of the indicator functions are distributed through the modules along the circuits formed by the AND-NOT 21 element block, the OR-NOT 22 element block group, the demultiplexer block 2.2, the register group 1.2, and the multiplexer block 3.2. In the module m _1.1 , the block of elements OR-NOT 20, the block of elements AND 12, the block of elements OR 16 is connected to this process, and the further distribution of the values of the indicator functions stops and closes to the block of elements AND 13.

At each moment of time, the registers of group 1.2 contain a set of current values of indicator functions in the recovery phase for all active barriers. As soon as in the module m _{ij the} value of the unit changes to zero, this means that the recovery condition (allowing the continuation of the next parallel branch) has reached the current module (see operation of the module in startup mode after the end of the parallel branch).

Writing a new value of the indicator function in the recovery phase to the corresponding category of registers of group 1.2 occurs along the leading edge of the next clock pulse of the wave in the recovery phase. This pulse from the output of one-shot 26 passes through the demultiplexer 2.2.n + 1 to the sync input of the register of group 1.2, which corresponds to the value of counter 4.2, and fixes in this register a new value of the indicator function, formed by the block of elements AND-NOT 21. This pulse switches the counter 4.2 to survey the next barrier, for which the formation of indicator functions has already begun according to the data from the modules of the previous reverse front.

Thus, the transfer of the values of the indicator functions in the phases of synchronization and recovery is carried out according to the conveyor scheme, the steps of which are determined by the forward and reverse fronts. Since n values are simultaneously transmitted at each clock cycle, this circuit is actually parallel to the conveyor, which allows combining a significantly larger number of operations in time.

Mode C. In this mode, the module goes after writing to the register 35 (Fig. 1) a command format F ₃ (Fig. 5). The operation of the module in mode C is reduced to indicating the completion of the k-th program and the transition to a passive state. At the output 3.10 of register 35 (Fig. 1), a single signal is formed - the end of the program mark (M _cp ), at the output 3.9, as in mode B, a single mark of the end of the section M _ku appears. At all other outputs of register 35, a zero signal level is formed, except for special bits for recording in registers 1.5-1.8 (Fig. 2).

Zero signals from the outputs 3.5-3.8 of register 35 (Fig. 1) are fixed by a single signal of a special high-order bit along the leading edge in registers 1.5-1.8 (Fig. 2). A single label M _CP from the output 3.9 of the register 35 (Fig. 1) is fed to the control inputs of the switch 37 and configures it to receive the next CPC from the input 56 of the module.

Simultaneously, the transition of the signal at the output 3.9 of the register 35 excites a pulse at the output of the single-shot 43. This pulse is supplied to the third input of the synchronization block 39, puts the trigger 60 (Fig. 3) to the zero state and thereby prevents the formation of synchronization pulses t ₁ and t ₂ at the outputs block 39 synchronization (Fig. 1). Reading commands from block 33 is terminated.

In a similar way, the operation of other PLMK modules is completed. The execution of the k-th program as a whole ends after the transition to the passive state of the last of the modules. After that, PLMK can proceed to the next program.

Claims (1)

Parallel logic multicontroller,  containing M * N modules of the same type,  combined into a matrix structure,  where N is the number of modules in the row of the matrix structure of the parallel logical multicontroller,  M is the number of rows  including program memory block,  address register  command register  logic condition multiplexer,  address switch  synchronization unit  first and second elements OR,  buffer register  block of elements OR,  first and second single vibrators,  delay element  moreover, the input of the operation code of the module is connected to the first information input of the address switch,  the output of which is connected to the information input of the address register,  the output of which is connected to the address input of the program memory block,  the output of which is connected to the information input of the command register,  the first output of which is connected to the address input of the logic condition multiplexer,  and a second output with a second information output of the logical conditions multiplexer,  the first information output of which is connected to the input of the logical conditions of the module,  the third output of the instruction register is combined with the output of the logical conditions multiplexer and connected to the first input of the OR block of elements and to the information input of the buffer register,  the output of which is connected to the second input of the block of elements OR,  the output of which is connected to the second information input of the address switch,  the fourth output of the command register is connected to the output of the microoperations of the module,  the output of the first one-shot is connected to the third input of the synchronization unit,  the first output of which is connected to the first input of the first OR element,  the output of which is connected to the sync input of the address register,  the second output of the synchronization unit is connected to the reset input of the buffer register and the second input of the second OR element,  the output of which is connected to the sync input of the command register,  the tenth output of the command register is connected to the control inputs of the address switch,  the output of the buffer register is connected to the reset input of the command register and the second inputs of the synchronization block,  the first input of the synchronization unit is connected to the start input of the module,  the module settings input is connected to the second input of the first OR element,  as well as with the input of the delay element,  the output of which is connected to the second input of the second OR element,  characterized in  that in each module an additional synchronizer module is introduced,  containing the first to fourth blocks of elements And,  a group of blocks of elements OR-NOT from first to d-th,  the first and second block of elements OR NOT,  the first and second block of OR elements,  block of elements AND NOT,  first to sixth element And,  first to fourth element OR,  group of blocks of buffer elements from the first to the pth (p = q / n,  where q is the maximum number of barriers in implemented programs,  and n is the number of physical bits of the parallel logical multicontroller),  block buffer elements  first to third trigger,  the first and second block of multiplexers,  the first and second block of demultiplexers,  first to third decoders,  first and second single vibrators,   the first and second register of the current physical discharge of the parallel logical multicontroller,  register of the maximum number of barriers in one physical category,  first and second register of the current barrier,  first and second counters,  match vector register,  first and second comparators,  mounting block OR from first to pth,  the first and second group of function value registers,  moreover, any block contains from the first to the nth element,  except demultiplexer blocks,  which contain from the first to n + 1 demultiplexers,  the first inputs of the elements And from the first block are connected to the first inputs of the synchronizer module in such a way  that the first bit of the first input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the first AND element in the first block,  the second digit of the first input from the group of first inputs of the synchronizer module is connected to the first input from the group of first inputs of the second AND element in the first block and so on until the n-th digit of the first input from the group of first inputs of the synchronizer module,  which is connected to the first input from the group of first inputs of the nth AND element in the first block,  similarly, the remaining bits are connected along the nth from the first to the dth input of the group of the first inputs of the synchronizer module,  which is connected to the d-th inputs from the group of the first inputs of the block of elements And,  the outputs of which are connected to the information inputs of the first block of demultiplexers in this way  that the output of the first element And from the first block is connected to the information input of the first demultiplexer from the first block,  the output of the second element And from the first block is connected to the information input of the second demultiplexer from the first block,  and the output of the nth element And from the first block is connected to the information input of the nth demultiplexer from the first block,  the first bits of the outputs of the demultiplexers from the first block are connected to the information input of the first register from the first group of function value registers,  the second bits of the outputs of the demultiplexers from the first block are connected to the information input of the second register from the first group of function value registers and so on until the p-th category of the outputs of the demultiplexers from the first block,  which is connected to the information input of the p-th register from the first group of function value registers,  the first bit of the n + 1st demultiplexer from the first block is connected to the clock input of the first register from the first group of function value registers,  the second output of the n + 1st demultiplexer from the first block is connected to the second input register clock from the first group of function value registers and so on until the pth bit of the n + 1st demultiplexer from the first block,  which is connected to the p-register clock input from the first group of function value registers,  from the first to the nth bits of the output of the first register of the first group of function value registers are connected to the first bits of the information inputs from the first to the nth multiplexers of the first block, respectively,  from the first to the nth bits of the output of the second register of the first group of function value registers are connected to the second bits of the information inputs from the first to the nth multiplexers of the first block, respectively, and so on to the first to the nth bits of the output of the pth register of the first group of registers function values  which are connected to the p-th bits of the information inputs from the first to the n-th multiplexers of the first block, respectively,  the outputs from the first to the n-th multiplexers are connected to the first inputs from the first to the n-th elements AND of the second block, respectively,  as well as to the first and second inputs from the first to the n-th elements OR NOT the first block, respectively,  the outputs of which are connected to the information inputs from the first to the nth buffer elements of the first block,  whose outputs are connected to the first and second inputs of all OR-NOT elements from the group of OR-NOT element blocks,  the group of second inputs of the third element And is connected to the group of second inputs of the synchronizer module,  the output of the third element And is connected to the input of the first one-shot,  the output of which is connected to the information input of the n + 1st demultiplexer of the first block of demultiplexers,  to the input of the increment of the first counter,  as well as to the second input of the third OR element,  the output of which is connected to all the outputs of the fifth group of outputs of the synchronizer module,  the third input of the synchronizer module is connected to the sync input of the third trigger,  the fourth input of the synchronizer module is connected to all reset inputs of the first and second groups of all function value registers,  first trigger  second trigger  the first and second register of the current physical discharge of the parallel logical multicontroller,  register of the maximum number of barriers in one physical category,  first and second register of the current barrier,  first and second counter,  match vector register,  as well as to the first input of the first OR element,  the output of which is connected to the reset input of the third trigger,  the direct output of which is connected to the first inputs of all elements AND of the third block of AND elements,  to the first input of the second element And,  as well as to the first input of the first element And,  the output of which is connected to the control input of the second decoder,  the installation input of the first trigger is connected to the fifth input of the synchronizer module,  the direct output of the first trigger is connected to all control inputs of the buffer elements of the block of buffer elements,  as well as with the first input of the sixth element And,  the output of which is connected to the first input of the fourth OR,  the output of which is connected to all fourth outputs of the synchronizer module,  the installation input of the second trigger is connected to the sixth input of the synchronizer module,  the direct output of the second trigger is connected to the second inputs of all the elements AND of the fourth block of AND elements,  as well as the first entry of the fifth element And,  the output of which is connected to the first input of the third OR element,  the group of element blocks is NOT connected to the group of seventh inputs in such a way  that the first block in the group of blocks of elements OR is NOT connected to the first input from the group of seventh inputs,  moreover, the first bit of the input is connected to the first and second input of the first element in the first block of the group of blocks of elements OR-NOT,  the second bit of the input is connected to the first and second input of the second element in the first block of the group of blocks of elements OR-NOT,  and so on until the nth digit of the input,  which is connected to the first and second input of the nth element in the first block of the group of blocks of elements OR-NOT,  other block inputs on the d-th block of elements OR NOT connected in the same way,  the outputs of the group of element blocks OR are NOT connected to the block of elements AND NOT in such a way  that the outputs from the first to the n-th first block in the group of blocks of elements OR NOT connected to the first inputs from the first to the n-th elements AND NOT in the block of AND elements,  the outputs from the first to the n-th second block in the group of blocks of elements OR NOT connected to the second inputs from the first to the n-th elements AND NOT in the block of elements AND NOT, and so on,  to the d-th block in the group of blocks of elements OR NOT,  whose outputs from the first to the nth are connected to the d-th inputs from the first to the nth AND-NOT elements in the block of AND-NOT elements,  the outputs of which are connected to the information inputs of the second block of demultiplexers in this way  that the output of the first AND-NOT element from the block is connected to the information input of the first demultiplexer from the block,  the output of the second AND-NOT element from the block is connected to the information input of the second demultiplexer from the second block,  and the output of the nth AND-NOT element from the block is connected to the information input of the nth demultiplexer from the block,  the first bits of the outputs of the demultiplexers from the second block are connected to the information inputs of the first register from the second group of function value registers,  the second bits of the outputs of the demultiplexers from the second block are connected to the information inputs of the second register from the second group of function value registers and so on until the p-th category of the outputs of the demultiplexers from the second block,  which is connected to the information inputs of the p-th register from the second group of function value registers,  the first bit of the n + 1st demultiplexer from the second block is connected to the clock input of the first register from the second group of function value registers,  the second bit of the n + 1th demultiplexer from the second block is connected to the sync input of the second register from the second group of function value registers and so on until the pth bit of the n + 1th demultiplexer from the second block,  which is connected to the p-register clock input from the second group of function value registers,  from the first to the nth bits of the output of the first register of the second group of function value registers are connected to the first bits of the information inputs from the first to the nth multiplexers of the second block, respectively,  from the first to the nth bits of the output of the second register of the second group of function value registers are connected to the second bits of the information inputs from the first to the nth multiplexers of the second block, respectively, and so on to the first to the nth bits of the output of the pth register of the second group of registers function values  which are connected to the p-th bits of the information inputs from the first to the n-th multiplexers of the second block, respectively,  the outputs from the first to the n-th multiplexers of the second block of multiplexers are connected to the second inputs from the first to the n-th elements of the third block of AND elements,  to all third outputs of the synchronizer module,  to the first and second inputs from the first to the nth elements of the second block of elements OR NOT,  the outputs of which are connected to the first inputs from the first to the nth elements of the fourth block of AND elements,  the outputs of which are connected to the first inputs from the first to the nth elements of the first block of OR elements,  the outputs of which are connected to the third inputs from the first to the nth elements of the first block of AND elements,  the inverse output of the second trigger is connected to the second inputs from the first to the n-th elements of the first block of OR elements,  as well as to the first input of the third element And,  the information input of the first register of the current physical discharge of the parallel logical multicontroller is connected to the eighth input of the synchronizer module,  and the senior bit of the eighth input of the synchronizer module is connected to the sync input of the first register of the current physical discharge of the parallel logical multicontroller,  the output of which is connected to the information input of the second decoder,  whose outputs from the first to the nth are connected to the second inputs from the first to the nth elements of the second block of OR elements,  the outputs of which are connected to the second inputs from the first to the nth elements of the first block of AND elements,  the information input of the second register of the current physical discharge of the parallel logical multicontroller is connected to the ninth input of the synchronizer module,  and the senior bit of the eighth input of the synchronizer module is connected to the sync input of the second register of the current physical discharge of the parallel logical multicontroller,  the output of which is connected to the information input of the third decoder,  whose outputs from the first to the nth are connected to the third inputs from the first to the nth elements of the third block of AND elements,  the outputs of which are connected to the inputs of the second OR element,  the output of which is connected to the second output of the synchronizer module,  as well as the input of the first OR element,  the information input of the register of the correspondence vector is connected to the tenth input of the synchronizer module,  and the senior bit of the tenth input of the synchronizer module is connected to the clock input of the register of the correspondence vector,  the outputs of which are connected to the information inputs of a group of blocks of buffer elements in such a way  that from the first to the n-th digit of the first output of the register of the correspondence vector is connected to the information inputs from the first to the n-th buffer elements of the first block of the group of blocks of buffer elements,  from the second to the pth outputs of the register of the correspondence vector are connected to the information inputs from the second to the pth blocks of the group of blocks of buffer elements in the same way  the outputs of the group of blocks of buffer elements are switched by a mounting OR block,  the outputs of which from the first to the nth are connected to the second inputs from the first to the nth element of the first block of AND elements,  the information input of the register of the maximum number of barriers in one physical category is connected to the eleventh input of the synchronizer module,  moreover, the senior bit of the eleventh input of the synchronizer module is connected to the clock input of the register of the maximum number of barriers in one physical category,  the output of which is connected to the information input of the second counter,  as well as to the information input of the first counter,  the output of which is connected to the information input of the first decoder,  control inputs from the first to n + 1st demultiplexers of the first block of demultiplexers,  to the control inputs from the first to the n-th multiplexers of the first block of multiplexers,  as well as to the first information input of the first comparator,  the output of which is connected to the second input of the first AND element,  from the first to the pth output of the first decoder are connected to control inputs from the first to the pth blocks of the group of blocks of buffer elements,  the output of the second counter is connected to the control inputs from the first to n + 1st demultiplexers of the second block of demultiplexers,  to the control inputs from the first to the n-th multiplexers of the second block of multiplexers,  as well as to the second information input of the second comparator,  the output of which is connected to the second input of the second AND element,  the output of which is connected to the control input of the third decoder,  the information input of the first register of the current barrier is connected to the twelfth input of the synchronizer module,  moreover, the senior bit of the eighth input of the synchronizer module is connected to the clock input of the first register of the current barrier,  the output of which is connected to the second information input of the first comparator,  the group of second inputs of the fourth element And is connected to the group of thirteenth inputs of the synchronizer module,  the output of the fourth element And is connected to the input of the second one-shot,  the output of which is connected to the information input of the n + 1st demultiplexer of the second block of demultiplexers,  to the input of the increment of the second counter,  as well as to the second input of the fourth OR element,  the inverse output of the first trigger is connected to the first input of the fourth element And,  as well as to the second inputs from the first to the n-th element of the second block of AND elements,  the outputs of which are connected to all the first outputs of the synchronizer module,  the second inputs of the fifth and sixth element AND are connected to the fourteenth input of the synchronizer module,  the information input of the second register of the current barrier is connected to the fifteenth input of the synchronizer module,  moreover, the senior bit of the fifteenth input of the synchronizer module is connected to the clock input of the second register of the current barrier,  the output of which is connected to the first information input of the second comparator,  a signal of a logical unit is connected to the information input of the third trigger,  fifth one  sixth,  the seventh and eighth outputs of the command register are connected to the eighth,  the twelfth  the ninth and fifteenth inputs of the synchronizer module, respectively,  the ninth output of the command register is connected to the third input of the synchronizer module,  as well as the input of the first one-shot,  the first information inputs from the first to the d-th (d is the number of controller measurements) of the synchronizer module are connected by the first outputs of the synchronizer modules of adjacent modules from the first to the d-th,  the second clock inputs from the first to the d-th are connected to the fifth outputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the fifth and sixth input of the synchronizer module are connected to the coordinate inputs of the module,  the seventh information inputs of the synchronizer module from the first to the d-th are connected to the third outputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the tenth information input of the synchronizer module is connected to the input of the correspondence vector of the module,  the eleventh information input of the synchronizer module is connected to the input of the maximum number of module barriers,  the thirteenth control inputs of the synchronizer module from the first to the d-th are connected to the fourth outputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the fourteenth input of the synchronizer module is connected to the input of the clock pulses of the module,  the first outputs of the synchronizer module from the first to the d-th are connected to the first information inputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the second output of the synchronizer module is connected to the input of the second one-shot and the sync input of the buffer register,  the third outputs of the synchronizer module from the first to the d-th are connected to the seventh information inputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the fifth outputs of the synchronizer module from the first to the d-th are connected to the second inputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the fourth outputs of the synchronizer module from the first to the d-th are connected to the thirteenth inputs of the synchronizer modules of the neighboring modules from the first to the d-th,  the first input of the synchronization unit is connected to the fourth input of the synchronizer module.  

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