RU2631976C2 - Tunable digital filter with programmable structure - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: tunable digital filter with a programmable structure contains an external tuner, a filter type code storing unit, a filter structure code storing unit, a clock generating unit, and a filtering unit. In addition, a pulse frequency identifying unit and a filter code converting unit are introduced.

EFFECT: decreasing the distortion of the digital filter characteristics.

3 cl, 7 dwg, 2 app

Description

The invention relates to the field of digital control of objects of aeronautical engineering, technology for processing and transmitting discrete information in such systems, and can be most effectively used to create digital filters of various types and structures, perform digital filtering, generate flows with certain properties, and also when constructing digital circuits continuous objects management.

It is known that in equipment of discrete automation, computer technology and information transmission technology, autoregressive digital filters and filters with finite impulse response (KIO) are widely used, which are implemented on register structures and signal adders with certain weight coefficients, the location and inclusion of which determine the type of digital filter , with a structure defined by a difference equation or a Z-transfer function [1, p. 45]. However, when the frequency f0 of the periodic input of the processed input information changes during operation, the frequency properties of the filter change, and with a significant change, such filtering can lead to unsatisfactory results, if you do not change it, rebuild the parameters of the digital filter.

Autoregressive filters and filters with finite impulse response (KIO filters), which are known and implemented as separate devices, have a rigid structure, determined by the type of filter and the "filtering" polynomial, which remain unchanged for filters. In relation to second-order filters, the device [3] shows the implementation of a programmable digital filter that allows changing the filter properties, in particular, providing the device with the properties of a low-pass filter, a high-pass filter, and a notch filter. The closest technical solution is a digital filter with a programmable structure, comprising, in series, an external tuner, a filter type code storage unit and a filter unit, the output of an external tuner connected to the input of the filter structure code storage unit, and through a second pulse generating unit, to a second the input of the filtering unit [2] - PROTOTYPE. The specified prototype allows you to implement digital filters for various purposes and with various properties, such as autoregressive filters, filters with finite impulse response (KIO), etc.

относительно расчетной

частоты поступления входной информации, свойства фильтра, в частности частотные характеристики меняются, а при значительном изменении частоты фильтр может потерять требуемые функциональные свойства. В замкнутой цифровой системе управления непрерывным объектом это может привести к уменьшению запасов устойчивости и ухудшению качества процессов управления, а при определенном изменении

возможна даже потеря устойчивости системы. Это можно показать на простейшем примере цифрового фильтра 1 порядка, описываемого z-передаточной функцией вида:

,However, if there is an off-design change in the actual frequency during operation

relatively estimated

the frequency of input information, filter properties, in particular, the frequency characteristics change, and with a significant change in frequency, the filter may lose the required functional properties. In a closed digital control system for a continuous facility, this can lead to a decrease in stability margins and a deterioration in the quality of control processes, and with a certain change

even a loss of system stability is possible. This can be shown on the simplest example of a first-order digital filter described by a z-transfer function of the form:

,

where a 0, b0, C are the numerical parameters of the link.

This Z - transfer function corresponds to difference equations connecting the input X and the output U of the digital filter:

where a0, b0, C are filter parameters.

- расчетная частота и

- измененная частота, где параметр N определяет изменение частоты. При этом разностные уравнения и соответствующая программа реализации фильтра, будут одинаковыми, но моменты квантования разными - соответственно

и

Частотная характеристики такого фильтра для частоты квантования

имеет вид:Let this digital control algorithm (digital filter) be implemented with different frequencies:

- estimated frequency and

- the changed frequency, where the parameter N determines the change in frequency. In this case, the difference equations and the corresponding filter implementation program will be the same, but the quantization moments will be different, respectively

and

The frequency response of such a filter for the quantization frequency

has the form:

определится выражением:and for the modified quantization frequency

defined by the expression:

,

,

those. as the quantization frequency changes, the frequency properties of the filter change substantially with respect to the calculated properties D0 * (j⋅ω). So, with a ₀ = -0.97, b ₀ = 0.3, the amplitude-frequency characteristic can differ by half at certain frequencies.

In order to eliminate these disadvantages of the known filter, the proposed technical solution is characterized in that the tunable digital filter with a programmable structure further comprises a pulse frequency identification unit and a filter code conversion unit, the output of the filter structure code storage unit through the filter code conversion unit is connected to the third input of the filter unit , and the output of the clock pulse generation unit through the pulse frequency identification unit - with the second input of the filter code conversion unit, ok pulse frequency identification contains a T-trigger, a first pulse generator and a pulse counter, and the input of the pulse frequency identification block is connected via series-connected T-trigger, the first pulse generator and a pulse counter with the output of the pulse frequency identification block, and the second output of the T-trigger is connected with the second input of the first pulse generator, in addition, the filter code conversion unit contains an adder, a relay with a first switch, a memory element block, a calculator of conversion parameters, a register multiplier, multiplexer, counter-switch, multiplier, accumulator-accumulator, parameter vector memory, second pulse generator, second switch, second input of the filter code conversion unit is connected to the relay input through the adder, and through the first switch connected in series, the conversion parameter calculator, multiplexer , multiplier, accumulator-accumulator, parameter vector memory and a second switch with the output of the filter code conversion unit, the output of the memory element block through the register of the multiplier is connected from the second m of the multiplier input, the second output of the calculator of the conversion parameters is connected through the second pulse generator to the input of the counter-switch, and the first, second third and fourth outputs of the counter-switch are connected respectively to the input of the block of memory elements, the second inputs of the multiplexer, adder-drive and vector memory block parameters, the fifth output of the counter-switch is connected to the second input of the second switch, the third input of which is connected to the first input of the filter code conversion unit.

In FIG. 1 shows the structure of a tunable digital filter with a programmable structure, FIG. 2 shows the structure of a pulse frequency identification unit; FIG. 3 shows a structure of a filter code conversion unit, FIG. 4 is a structure of an implementation of a calculator of conversion parameters, FIG. 5 shows a structure of an implementation of a filtration unit, FIG. 6 is a structure implementation of a switching unit, FIG. 7 - an example implementation of a counter-switch, where the following notation:

1 - Block storage code type filter,

2 - Block storage code structure of the filter,

3 - Block forming clock pulses,

4 - Pulse frequency identification unit

5 - Block recount filter code,

6 - Filtration unit,

7 - T-trigger

8 - The first pulse generator,

9 - pulse counter

10 - adder,

11 - Relay

12 - Blocks of memory elements,

13 - Calculator parameters conversion,

14 - Register of the multiplier,

15 - Multiplexer,

16 - Counter-switch,

17 - Multiplier,

18 - adder drive

19 - Memory parameter vector

20 - The second switch,

21 - The first switch

22 - The second pulse generator,

23 - Switching unit,

24 - The first vector multiplier,

25 - Second vector multiplier

26 - The first drive register,

27 - The second register-drive

28 - Memory function values,

29 - The first multiplier,

30 - The second multiplier,

31 - Nth multiplier,

32 - External configuration device.

Implementation of a tunable digital filter with programmable structure.

The essence of the tunable digital filter is as follows.

и частотной характеристики (исходного) линейного цифрового фильтра, описываемого z-передаточной функцией видаLet it be required to ensure the proximity of the frequency response of the digital filter at a changed frequency

and frequency response of the (initial) linear digital filter described by a z-transfer function of the form

- период дискретности, A0(z) и B0(z) - многочлены от z.Where

is the period of discreteness, A0 (z) and B0 (z) are polynomials in z.

The filter described by the transfer function (1) is called the reference digital filter (OTsF) - it corresponds to the desired functional properties. The frequency response (CH) of such a filter is determined by the expression [1]:

where the symbol * will denote the frequency response of the discrete system. Such a characteristic is a transcendental function of ω and has periodic properties [1, p. 59]:

, использование старой передаточной функции опорного фильтра приведет к измененной ЧХ вида:In the case when the quantization frequency has changed

, the use of the old transfer function of the reference filter will lead to a modified frequency response of the form:

.

.

который в N раз меньше, чем у исходной (N>1). В силу этого, подобрать «подобный фильтр», т.е. некоторый цифровой фильтр DN (z, T0⋅N) такого же порядка, как опорный, но который полностью повторял бы свойства опорного ЦФ, при измененной частоте

невозможно.Note that this frequency response has other properties: it is scaled along the frequency axis relative to the reference, and most importantly, has a repetition period

which is N times less than the original (N> 1). Because of this, choose a "similar filter", i.e. some digital filter DN (z, T0⋅N) of the same order as the reference one, but which would completely repeat the properties of the reference DF at a changed frequency

impossible.

. Для этого нужно выбирать параметры подобного ЦФ так, чтобы псевдочастотные характеристики ОЦФ при исходной частоте квантования

и псевдочастотные характеристики подобного фильтра при частоте квантования

были близки в указанном диапазоне. Такой критерий может дать очень близкое совпадение характеристик подобного и опорного фильтров в полосе реальных частот

However, it is possible to form a digital filter that ensures repetition of the frequency response of the reference filter in a limited frequency band, in particular in the main frequency band of a digital system

. For this, it is necessary to choose the parameters of such a DF so that the pseudofrequency characteristics of the DFT at the initial quantization frequency

and pseudo-frequency characteristics of such a filter at a quantization frequency

were close in the indicated range. Such a criterion can give a very close coincidence of the characteristics of a similar and a reference filter in the band of real frequencies

[1, стр. 61], и приравнивая характеристики ОЦФ и ПФ в W-области, запишем:This follows from the fact that the absolute pseudofrequency ∧ [1, p. 61] and the real frequency coincide fairly close in the indicated range. Using the transition to the W-region, where W is the bilinear transformation parameter

[1, p. 61], and equating the characteristics of the OTsF and PF in the W-region, we write:

whence we get for a similar filter the transfer function in the W region in the form:

:Knowing the transfer function DN (W) from (2) a similar filter in the W region, we pass to its z-transfer function taking into account the changed frequency

:

DN (z, T0⋅N) = DN (W, T0⋅N) when replacing

Let the reference digital filter be described by a z-transfer function of the form:

Using expression (2), after the transformations we get:

, получим z-передаточную функцию фильтра в виде:Substituting the inverse w-transformation formula into the expression obtained, where

, we obtain the z-transfer function of the filter in the form:

, в дальнейшем называемый параметром пересчета, связанный с изменением частоты квантования (R=0 при неизменной частоте f0), и преобразуем DN(z) к следующему виду:To simplify the expression, we introduce the coefficient

, hereinafter referred to as the conversion parameter, associated with a change in the quantization frequency (R = 0 at a constant frequency f0), and transform DN (z) to the following form:

From expression (3) we obtain an algorithm for calculating the numerator coefficients at powers of z using representations of the polynomial in the form of a Horner scheme:

We denote the polynomials in square brackets as M1 (z), and the polynomials in parentheses as M2 (z). Moreover, the dimension of polynomials varies from 1 to n, the elements of polynomials are coefficients at powers of z. From Horner's scheme follows the rule for calculating the following polynomials M1 and M2 (z):

M1 (z) = M1 (z) ⋅ (z + R) + a _i ⋅ M2 (z).

Initial polynomials:

M2 (z) = (z⋅R + 1),

M1 (z) = ( a ₀ + a ₁ ⋅ R) ⋅ z + ( a ₁ + a ₀ ⋅ R),

The calculation of polynomials ends at step i = n, and the coefficients of the resulting polynomial M1 are the desired coefficients of the numerator.

Similarly, but for the coefficients b _i , the denominator DN (z) can also be calculated. The table given in APPENDIX 1 contains specific values of the polynomials of the numerator and denominator in the function of the recalculation parameter R for similar ones, i.e. recalculated, low order filters. Similar relations can be obtained for any fixed filter order according to (4). In the drawing given in APPENDIX 2, the dashed line shows the frequency characteristics of such a first-order digital filter, the parameters of which are calculated by relations (4). As can be seen from the drawing, the restructuring of the parameters of the digital filter allows to achieve a significant proximity of the frequency response of the filter to the characteristics of the reference digital filter with a significant change in T0.

It is convenient to set the recalculation formulas in the form of matrix relations, which, using the known parameters of the reference algorithm { a 0 _i , b0 _i } and the values of the actual quantization period T0 * N, or the parameter R, recalculate the values of the parameters of such a filter according to the following relation:

where A0, B0-n + 1 - dimensional vectors of the parameters of the reference digital filter,

AN, BN-n + 1 - dimensional vectors of parameters of such a digital filter,

Q (R) - (n + 1) × (n + 1) - matrix of transformations, or recalculation.

Representing (5) for the individual components a N _J , bN _J , we obtain:

We represent the conversion matrix Q in the form of the product Q = QN⋅T, where

- нормирующая матрица (n+1)⋅(n+1)

is the normalizing matrix (n + 1) ⋅ (n + 1)

- нормированная матрица пересчета.

- normalized translation matrix.

So, for example 2 orders of the matrix QN and T will take the form:

Consider the structure of the matrix QN recalculation in its normalized form. It is easy to see that the Jth column of the matrix is a set of coefficients of the polynomial

moreover, the (J-1) roots of the polynomial is 1 / R, and the remaining (n-J + 1) roots are equal to R. Then the line with number I will determine the coefficient of n-I + 1 degrees z of the polynomial (6): the first line is degree n, the second - n-1, ..., the last - degree 0. Thus, we can formulate a simple rule for calculating the coefficients of the normalized conversion matrix QN for tuning the filter parameters when the quantization frequency changes.

,The element of the translation matrix QN [I, J] = the sum of all possible combinations of products (I-1) of different roots:

,

and there are only two values of different roots: -R and -1 / R.

The Jth column of the original Q [I, J] matrix can be expressed as a series

For example, for n = 4, the translation matrix in the function R is expressed as follows:

In this regard, to store the vectors G _{J, K} that determine the translation matrix, you can use the memory for (n + 1) * (n + 1) * (n + 1) integers. In this case, the general algorithm for computing the vectors QJ [1] for any J takes the form:

Formula (8) allows you to calculate the vectors that make up the conversion matrix for the known vectors G _{J, K} and the current values of R ⁿ , R ^n-1 ... R,

Thus, to calculate the translation matrix, it is necessary to use memory blocks Пk containing vectors G _{J, K} in the following form:

The reduced matrix из from (9) contains (n + 1) * (n + 1) * (n + 1) integers that do not depend on the filter parameters, but are determined only by its order. Obtaining the conversion matrix Q (R) for a specific value of R can be done by multiplying P by (n + 1) ² × (n + 1) - a matrix P of the form:

where RG = [R ⁿ R ^n-1 ... R 1] ^T , T is the sign of transposition.

Moreover, it is characteristic that the vectors G _{J, K} contain a large number of zeros and integers - binomial coefficients or their compositions, and therefore the number of multiplications in calculating the matrix Q is at least two to three times less than the nominal number (n +1) ³ multiplications.

Given that we do not need the conversion matrix itself, but we need its rows multiplied by a N _J and bN _J , from (5 *) we get:

Thus, we obtain for calculating the parameters a N _i , bN _{i a} relationship of the form:

Opening (11), we obtain:

In a compact form, we write the expression as follows:

дискретности относительно опорной частоты

.It can be seen from expression (12) that the recalculated coefficients of the digital filter a N _i , bN _i can be calculated using the well-known, previously calculated vectors Dk and Uk, which depend on the order of the system, the known parameters a 0 _i , b0 _{i of the} reference filter, as well as the parameters recalculation of R, R ² , ..., R ⁿ , depending on the current frequency change

discreteness relative to the reference frequency

.

и подобного фильтра на частоте

будет выполняться на низких частотах, а на частотах в окрестности

и выше реальная частота может отличаться от псевдочастоты, и характеристика фильтра будет смещена на 10-15% относительно опорной. Для уменьшения смещения по частоте в указанном диапазоне частот удобно ввести компенсирующий множитель V=0,9-1,3 и параметр пересчета R вычислять по формуле:

, где множитель V выбирается при проектировании цифрового фильтра так, что N>1 при

и V<1 при

.It should be noted that the good proximity of the characteristics of the reference filter at a frequency

and similar filter on frequency

will be performed at low frequencies, and at frequencies in the vicinity

and higher, the real frequency may differ from the pseudo-frequency, and the filter characteristic will be shifted by 10-15% relative to the reference. To reduce the frequency offset in the specified frequency range, it is convenient to introduce a compensating factor V = 0.9-1.3 and the conversion parameter R calculated by the formula:

, where the factor V is chosen when designing a digital filter so that N> 1 for

and V <1 for

.

квантования необходимо:Therefore, to ensure the constancy of the characteristics of the digital filter when the frequency changes during operation

quantization is necessary:

1. Previously, before using the digital filter, calculate the constant vectors G _{J, K} that determine the calculation of the translation matrix, for which:

a) calculate the conversion matrix as a function of the parameter R,

b) get a normalized translation matrix,

c) compose constant vectors Dk, Uk according to (12) for K = 0, 1, ..., n,

d) determine the minimum value eps of the change in the frequency of the discreteness, at which the tuning of the filter parameters is required.

2. Pre-place the data defining the vectors Dk, Uk in the memory blocks of the filtering device - 2 - (n + 1) ² numbers.

поступления информации.3. During the filtering process, periodically measure the frequency

receipt of information.

произвести оперативный пересчет параметров фильтра, для этого:4. In the case of a significant change in the filtering frequency

make an operational recount of filter parameters, for this:

, Rⁱ,a) calculate the current conversion parameters

, R ⁱ ,

b) using formula (12), calculate the parameters a N _i , bN _i for specific values of the conversion parameter R,

c) use the calculated parameters a N _i , bN _i in the current operation of the digital filter.

It is this method of ensuring the constancy of the characteristics of the digital filter that the device described below implements. The operation of the proposed device is as follows.

Выбранный тип структуры определяется порядком фильтра n, типом фильтра (КИО или авторегрессионный), а также конкретными параметрами - например коэффициентами фильтрующего полинома, или z-передаточной функции. Выбирается значение частоты

первого генератора импульсов 8, соответствующей соотношению

- фиксированное число. По расчетам и результатам моделирования процессов фильтрации при изменении частоты

на

определяются допустимые величины ε изменения частоты квантования по соответствующей величине

, где

- относительный текущий период квантования. Рассчитываются весовые векторы GJK, используемые при вычислении К-х векторов Dk, Uk, данные векторы размещаются в 2⋅(n+1)² ячейках блока элементов памяти 12 блока перестройки кода фильтра 5. Соответствующие данные по параметрам опорного цифрового фильтра в виде числовых параметров заносятся в блок 2 хранения кода структуры фильтра. Данные параметры помещаются в память опорных параметров фильтра - блоки регистров, где каждый регистр определяет один из 2n+1 параметров фильтра.Preliminarily, at the design stage, the structure of a digital filter operating at a certain quantization frequency is selected

The selected type of structure is determined by the order of the filter n, the type of filter (KIO or autoregressive), as well as specific parameters - for example, the coefficients of the filtering polynomial, or z-transfer function. Frequency value is selected

the first pulse generator 8 corresponding to the relation

is a fixed number. According to the calculations and simulation results of filtering processes when the frequency changes

on

permissible values ε of the quantization frequency change are determined from the corresponding value

where

- relative current quantization period. The weight vectors GJK used to calculate the Kth vectors Dk, Uk are calculated, these vectors are placed in 2⋅ (n + 1) ² cells of the block of memory elements 12 of the filter code adjustment block 5. The corresponding data on the parameters of the reference digital filter are in the form of numerical parameters recorded in block 2 of the storage code filter structure. These parameters are placed in the memory of the filter reference parameters - register blocks, where each register defines one of 2n + 1 filter parameters.

в процессе работы производится идентификация периода дискретности поступления информации. Для этого в блоке идентификации частоты квантования 4 по переднему фронту тактового импульса запускается Т-триггер 7 и своим первым выходом запускает первый генератор импульсов 8, частота которого в 100-200 раз больше расчетной частоты квантования

Счетчик импульсов 9 фиксирует число Nt импульсов с первого генератора импульсов 8 за период квантования. По переднему фронту следующего импульса генератор 8 отключается по сигналу со второго - инвертирующего выхода Т-триггера 7.When the tunable digital filter is working, the signal from an external device starts the pulse shaper 1, which provides synchronous input to the filtering unit 6 of a continuous filtered data sequence. Occasionally, for example, with a period

in the process of identification of the discreteness period of the receipt of information. To do this, in the quantization frequency identification unit 4, a T-trigger 7 is launched on the leading edge of the clock pulse and, with its first output, launches the first pulse generator 8, whose frequency is 100-200 times the calculated quantization frequency

The pulse counter 9 captures the number Nt of pulses from the first pulse generator 8 during the quantization period. On the leading edge of the next pulse, the generator 8 is turned off by a signal from the second inverting output of the T-trigger 7.

All of the above devices can be implemented on commercially available integrated circuits (ICs). So, for example, the T-trigger 7 is implemented on KM555TM2 or K155TM2 [4, p. 76, 75], the first pulse generator 8 is K555AG3 (K155AG3) [4, p. 190], the pulse counter 9 can be implemented on one or several chips of the decimal binary decimal counter K155IE9 [4, p. 97]. So, on the indicated page the connection of four such microcircuits to a synchronous 16-bit counter (from 0 to 64000) is given. For the described device, it is sufficient to use the three indicated microcircuits (12 bits, counting up to 4096).

, реле 11 не срабатывает, первый переключатель 21 не передает сигнал, перестройка не выполняется, второй переключатель 20 передает на цифровой фильтр 6 опорные параметры из блока хранения кода фильтра 2. Если изменение dN относительного периода велико

, срабатывает специальное реле 11, построенное соединением компаратора и порогового элемента, так что компаратор сравнивает

и ε и формирует логический сигнал 1 в случае

а пороговый элемент формирует переключения. Реализация компаратора может выполняться на базе соединения компараторов К555СП1 или К561ИП2 [4, стр. 277, рис 2.68]. На данном рисунке представлено соединение трех 4-разрядных компараторов К561ИП2, реализующих 12-разрядный компаратор. Пороговый элемент можно реализовать триггером Шмидта (К155ТЛ1), возможно, при низких частотах

использование усилителя и электромеханического реле, замыкающего переключатель, включающий устройства, выполняющие пересчет параметров фильтра.The value of the parameter Nt is transmitted to the second input of the filter code conversion unit 5. Next, in the adder 10, the difference dN between the measured Nt and the given N0 value of the number of pulses is calculated. The result of the operation is considered modulo as a positive number. This operation for 12-bit numbers can be implemented by three adder-subtractor microcircuits, for example K555IM7, containing 4 sequential adders [4, p. 162], without taking into account the sign discharge at the output. If the change in dN of the relative period Nt does not exceed the threshold

, the relay 11 does not work, the first switch 21 does not transmit a signal, tuning is not performed, the second switch 20 transfers to the digital filter 6 the reference parameters from the filter code storage unit 2. If the change in dN of the relative period is large

, a special relay 11, built by connecting the comparator and the threshold element, is activated, so that the comparator compares

and ε and generates a logical signal 1 in the case

and the threshold element forms a switch. The implementation of the comparator can be performed on the basis of the connection of the comparators K555SP1 or K561IP2 [4, p. 277, Fig. 2.68]. This figure shows the connection of three 4-bit comparators K561IP2, implementing a 12-bit comparator. The threshold element can be implemented by a Schmidt trigger (K155TL1), possibly at low frequencies

the use of an amplifier and an electromechanical relay that closes the switch, which includes devices that recount filter parameters.

т.е. N0=200, и идентификация текущей частоты

по подсчету значения Nt счетчиком импульсов 9 дает ошибку в 0.5% (1/200). Пусть требуется удовлетворительная работа цифрового фильтра при изменении частоты в 10 раз, т.е. 20<Nt<2000. Следовательно, для размещения всевозможных значений R(Nt) достаточно памяти на 2000 слов. Если каждое слово задает 16-разрядное число (1 знаковый разряд), то объем памяти для размещения нелинейной функции составит 4 кбайта, при этом точность вычислений R составит 1/2¹⁵=0.003%. Если под слово отводить 1 байт, то потребуются 2 кбайта памяти и точность вычислений составит 1/2⁷=0.8%, что также вполне достаточно. Такая память может реализовываться на матрицах запоминающих элементов PROM К155РЕ3 (32×8, бит) или микросхемах серии К556, имеющих информационную емкость до 64 кбит [5, стр. 198, 200]. Обращение к памяти может выполняться по значению целого Nt. Структура такой реализации вычислителя параметров пересчета 13 представлена на фиг. 4. Характерно, что данная реализация вычислителя нелинейной функции R(Nt) может существенно упростить приборную реализацию за счет исключения сумматоров и делителя. Заполнение памяти значениями R(Nt) должно производиться на предварительном этапе подготовки цифрового фильтра. Для вычисления произведений R⋅R, R²⋅R, R³⋅R, …, R^n-1⋅R можно использовать умножитель. Такие умножители могут реализовываться на ИМС К1802ВП5, возможно использование перемножителя К555ИП9 и сумматора К555ИМ7 [4, стр. 165, 162]. Данные, полученные с вычислителя параметров пересчета 13, используются для вычисления отдельных i-х элементов вектора параметров. Для этого вычислитель параметров пересчета 13 по выполнению всех умножений формирует сигнал на запуск второго генератора импульсов 22, приводящего в действие счетчик-коммутатор 16. Период импульсов второго генератора 22 должен быть таким, чтобы за это время могли осуществиться операции извлечения из памяти и умножения. Реализация второго генератора импульсов 22 аналогична описанной выше реализации блока 8 - ИМС К555АГ3 (К155АГ3) [4, стр. 190]. По сигналам второго генератора импульсов 22, подаваемым на вход счетчика-коммутатора 16, начинает работать счетчик-коммутатор 16, управляющий работой блока элементов памяти 12, мультиплексора 15, сумматора накопителя 18 и обеспечивающий очередность перемножения R^K⋅DK[i]. Для этого на входы умножителя 17 поочередно передаются из i-го блока элементов памяти 12 и вычислителя параметров пересчета 13 множители для К-й компоненты R^K⋅DK[i] (К=0, 1, 2, …, n) скалярного произведения

Множители для каждой компоненты поступают в умножитель через регистр множителя 14 и мультиплексора, которыми управляет счетчик-коммутатор 16, приводимый в действие тактирующими импульсами. Данный счетчик поочередно выдает на своем первом выходе значения 0, 1, … (n+1)²-1 (для КИО фильтра), подаваемые на блок элементов памяти 12, по которым из блока 12 считывается число и подается на регистр множителя 14, передающий число на умножитель 17. Соответствующие последовательности данных чисел, извлекаемых из памяти 12, имеют вид: D0[i], D1[i], …, Dn[i]. На втором выходе счетчика-коммутатора 16, связанном со вторым адресным входом мультиплексора 15, формируется последовательность значений К=0, 1, …, n. По данной последовательности второй мультиплексор 15 передает на блок умножения 17 второй множитель, формируемый в вычислителе параметров пересчета 13. Последовательность сигналов на втором входе умножителя 17 при этом будет такой: 1, R, …, R^n-1, Rⁿ. Первоначально на счетчике-коммутаторе 16 устанавливается 0, что соответствует К=0, i=1, сумматор-накопитель обнуляется. В умножителе 17 осуществляется умножение 1⋅D0[1], результат пересылается в сумматор-накопитель 18. Далее по приходу задающего импульса счетчик-коммутатор 16 сдвигается на 1 и вычисляется следующее произведения R⋅D1[1], которое складывается в сумматоре-накопителе 18 с предыдущим, затем для нового состояния счетчика вычисляется R², для нового состояния счетчика вычисляется R^n-2⋅D2[i] и т.д. до К=n. В результате n+1 перемножений и сложений получается один элемент aN₀, составляющий вектор AN. После вычисления второй выход счетчика-коммутатора 16 обнуляется, счетчик-коммутатор 16 подает на второй вход блока 19 сигнал записи в память вектора параметров 19 содержимого вектора накопителя 18, который затем обнуляется.The actual tuning of the parameters of the digital filter is carried out by applying the transformation matrix Q (R) to the reference parameters stored in the filter structure code storage unit 2 and supplied to the input of the filter code tuning unit 5. Initially, by the signal Nt on the first switch 21 in the calculator of the conversion parameters 13 are calculated the conversion parameter R = (Nt⋅V-N0) / (Nt⋅1 / + N0), as well as its degree R ² ... R ⁿ , i.e. the calculator calculates the parameter R according to the nonlinear function R (Nt), then calculates the degrees using successively the multiplications R⋅R, R ² ⋅R, R ³ ⋅R, ..., R ^n-1 ⋅R, and upon completion of the calculations generates a start signal the second pulse generator 22, clocking the counter-switch 16. A convenient way to calculate R in block 13 can be to use memory blocks to calculate the nonlinear function R (Nt) [5, p. 219, 220]. Considering that the parameter Nt is an integer with a limited range, each value of № as an address can be associated with a number R (Nt) and the calculation of a nonlinear function can be replaced by extracting a previously calculated result from the memory for a specific Nt value. For concreteness, we assume that the first pulse generator 8 generates a frequency 200 times higher

those. N0 = 200, and identification of the current frequency

by calculating the Nt value, the pulse counter 9 gives an error of 0.5% (1/200). Let satisfactory operation of the digital filter be required when the frequency changes 10 times, i.e. 20 <Nt <2000. Therefore, to accommodate all kinds of R (Nt) values, enough memory for 2000 words is enough. If each word specifies a 16-bit number (1 sign digit), then the amount of memory to accommodate the nonlinear function will be 4 kbytes, while the calculation accuracy R will be 1/2 ¹⁵ = 0.003%. If you assign 1 byte to a word, then 2 kbytes of memory will be required and the accuracy of the calculations will be 1/2 ⁷ = 0.8%, which is also quite enough. Such memory can be implemented on PROM K155RE3 storage element arrays (32 × 8, bits) or K556 series microcircuits having an information capacity of up to 64 kbit [5, p. 198, 200]. Memory access can be performed by the value of the integer Nt. The structure of such an implementation of the calculator of the conversion parameters 13 is shown in FIG. 4. It is characteristic that this implementation of the calculator of the nonlinear function R (Nt) can significantly simplify the instrument implementation by eliminating the adders and the divider. Filling the memory with the values of R (Nt) should be carried out at the preliminary stage of preparation of the digital filter. To calculate the products R⋅R, R ² ⋅R, R ³ ⋅R, ..., R ^n-1 ⋅R, you can use the multiplier. Such multipliers can be implemented on the K1802VP5 IC; it is possible to use the K555IP9 multiplier and the K555IM7 adder [4, p. 165, 162]. The data obtained from the calculator of the conversion parameters 13 are used to calculate the individual i-elements of the parameter vector. To do this, the calculator of the recalculation parameters 13, after performing all the multiplications, generates a signal to start the second pulse generator 22, which drives the counter-switch 16. The pulse period of the second generator 22 must be such that during this time operations can be performed from the memory and multiplication. The implementation of the second pulse generator 22 is similar to the above implementation of block 8 - IC K555AG3 (K155AG3) [4, p. 190]. According to the signals of the second pulse generator 22 supplied to the input of the counter-switch 16, the counter-switch 16 starts operating, controlling the operation of the block of memory elements 12, the multiplexer 15, the accumulator adder 18 and ensuring the sequence of multiplication R ^K ⋅ DK [i]. To do this, multipliers for the Kth component R ^K ⋅ DK [i] (К = 0, 1, 2, ..., n) of the scalar product are successively transferred to the inputs of the multiplier 17 from the i-th block of memory elements 12 and the calculator of the conversion parameters 13

The multipliers for each component enter the multiplier through the register of the multiplier 14 and the multiplexer, which are controlled by the counter-switch 16, driven by clock pulses. This counter alternately gives on its first output the values 0, 1, ... (n + 1) ² -1 (for the filter KIO), fed to the block of memory elements 12, by which a number is read from block 12 and fed to the register of the multiplier 14, transmitting the number per multiplier 17. The corresponding sequences of these numbers, extracted from the memory 12, are of the form: D0 [i], D1 [i], ..., Dn [i]. At the second output of the counter-switch 16 associated with the second address input of the multiplexer 15, a sequence of values K = 0, 1, ..., n is formed. According to this sequence, the second multiplexer 15 transmits to the multiplication block 17 a second multiplier generated in the calculator of the conversion parameters 13. The sequence of signals at the second input of the multiplier 17 will then be: 1, R, ..., R ^n-1 , R ⁿ . Initially, 0 is set on the counter-switch 16, which corresponds to K = 0, i = 1, the accumulator-drive is reset. In the multiplier 17, 1⋅D0 [1] is multiplied, the result is sent to the adder-accumulator 18. Then, upon the arrival of the driving pulse, the counter-switch 16 is shifted by 1 and the next product R⋅D1 [1] is calculated, which is added to the adder-accumulator 18 with the previous one, then R ^{2 is} calculated for the new counter state, R ^n-2 ⋅ D2 [i] is calculated for the new counter state, etc. to K = n. As a result of n + 1 multiplications and additions, we get one element a N ₀ that makes up the vector AN. After the calculation, the second output of the counter-switch 16 is reset, the counter-switch 16 supplies the second input of block 19 with a write signal to the memory of the parameter vector 19 of the contents of the vector of the drive 18, which is then reset.

The calculation of the values of the other components a N _{i of the} vector AN for other values of i is carried out similarly, but using the new elements of the memory block 12. Using similar procedures, all elements of the vector AN are calculated, which are located in the memory of the parameter vector 19. After calculating all the components of the vector AN, BN is calculated, while if the digital filter 6 implements the filter KIO, the calculation of BN is not performed.

In the above operations, the following circuitry is possible on typical ICs or their combinations. Blocks of memory elements 12 can be implemented on the matrixes of storage elements PROM K155RE3 (32 × 8 bits) or chips of the K556 series [5, p. 198, 200]. The memory of parameter vector 19 can be implemented on K537RU8 microcircuits - 2 Kbytes of static RAM (8 bits each) or K155RU2 chipset (64 bit RAM) [4, p. 167], multiplier register 14 - K555IR8 [5, p. 121], multiplexer 15 - K555KP15 [4, p. 154], multipliers 17, 29-31 - K555IP9 [4, p. 165] or 1802 VP5. The counter switch 16 must form at the first output a sequence of 0, 1, ..., (n + 1) ² -1 and at the second output 0, 1, 2, ..., n, 0, 1, 2, ... n, ... 0, 1, 2, ... n. Such a device can be formed from the schemes of standard binary decimal counters KP1533IE2 [5, p. 160], which include sections with modules 2 and 5, and when clock pulses are applied to the input, they can provide a counting module M = n + 1 (number of states) up to 10 , and when building several ICs and more. By resetting the counter when M-1 is reached by applying a signal from the output to the RESET input, it is possible to realize the desired sequence 0, 1, 2, ... n, 0, 1, 2, ... n, ... 0, 1, 2, ... n for the second controls the multiplexer 15 and the formation of the recording signal in the memory of the vector of parameters 19 and the reset signal of the adder-drive 18 after recording. By passing 1 at the time of reset to the exact same circuit, we get the output sequence with module (n + 1) ² for controlling reading from the block of memory elements 12 and generating, after the end of this sequence, a signal to switch 20 in the case of an KIO filter. For an autoregressive filter, after calculating the parameters a N _{i, the} parameters bN _i are likewise calculated - another (n + 1) ² clock cycle of the same calculations. Similarly, you can use the IC-K155IE9 [4, p. 97, Fig. 1.70] - where the connection of four microcircuits to a fast 16-bit counter is presented. An example of the implementation of these functions of the counter-switch is shown in FIG. 7. The adder-drive 18 can be implemented by the composition of several K555IM6 (adder for two 4-bit words).

Upon completion of the calculation of the parameter vectors AN and BN, the counter-switch 16 through the second switch 20 switches the filter parameters from the reference parameters to the recalculated parameters from the parameter vector memory 19. This is accomplished by supplying inhibit and enable signals to the corresponding memory registers. Further, the parameters from block 19 are directly involved in the filtering process. It should be noted that all the described calculations for recalculating the filter parameters are performed once or occasionally with a change in the quantization frequency, in connection with this, the temporal characteristics of the calculations are not significant for filtering, in contrast to the calculations in the filtering unit, which are performed at each quantization step and are limited rigid time relationships.

Estimated time of TV calculations, without taking into account the operations of addition, fetch from memory and write to memory during rebuilding will be determined for the filter as follows:

Tv = Tumn * 2⋅ (n + 1) ² , where Tumn is the time of implementation of the multiplication of numbers.

The filtering process itself consists in forming at the output of the filtering unit 6 the sum of the coordinates of the state of the digital filter with certain weights generated by the filter parameter tuning unit 5. This standard operation can be implemented by various known devices, for example from [1] or from [2].

With another approach to organizing this process, in the filtering unit 6, memory cells are used that form a homogeneous medium, and a switch 23 is implemented on a ring register-counter that counts clock pulses 1, 2 ... n, 1, 2, ... - FIG. 5. The switch organizes periodic connections of the cell outputs and the input signal of the block to vector multipliers - blocks 24, 25. To explain the work, we consider some memory cells A1, A2, A3, A4, which contain numerical data characterizing the state of the filter. For example, suppose we have a fourth-order digital filter, described by the four coordinates of the state X1, X2, X3, X4, and at a certain time step, the state coordinate X1 is placed in A1, X2 in A2, X3 in A3, and X4 in A4. The digital filter is implemented by direct programming [3, p. 33], in which the equations of change of the state vector X and the scalar output Y have the form

where qI and cJ are the filter parameters — constants calculated in block 5 during the reconstruction, or constants from the storage block of the filter structure code 2 in the case when there is no reconstruction.

Upon receipt of a new input signal, the switch 23 transmits to the second group of inputs 5, 6, 7, 8 of the second vector block of the multiplier 24 the contents of cells A1, A2, A3, A4, as well as the input signal Z. In the block, the corresponding multiplication of coordinates by previously calculated in block 5 (or block 2 without tuning) constants and the output signal of the filtering block is formed in the form:

Y = c1 * X1 + c2 * X2 + c3 * X3 + c4 * X4 + d * Z.

The specified amount of works is formed in the first register-drive 26 and is sent to the output of the filter.

Next, the new values of the state coordinates according to the equations are recalculated and the placement of the state coordinates for the next calculation step is changed: the coordinate X4 (A4) becomes X3, X3 (A3) becomes X2, X2 (A2) becomes X1, and the X4 coordinate is calculated by the ratio:

X4 = q1 * X1 + q2 * X2 + q3 * X3 + q4 * X4 + v * Z.

The calculation is carried out in block 25, the summation of private works in the second register-drive 27, the result is recorded in A1. Thus, the coordinates of the state changed location: X1 (A2), X2 (A3), X3 (A4), X4 (A1), but the dubbing was done only in one cell A1. On the next clock, everything is repeated, but the inputs 5, 6, 7, 8 of the multiplication units must be fed with signals from memory cells in a different order: A2, A3, A4, A1, then A3, A4, A1, A2, then A4, A1, A2, A3 and, finally, A1, A2, A3, A4. All these offsets of the connections of the memory cells and the inputs of the multiplication units are organized by the switching unit 23, which can be implemented using a ring register-counter for 4 cycles (in general, n cycles) and multiplexers that switch the input of signals to the various inputs of the multiplication unit - Fig. 6. In particular, each of the 4 multiplexers transmits a signal to a specific input from the second group of inputs of the first vector multiplier 24 and the second vector multiplier 25. Signals from all cells, as well as signals from the first vector block of the multiplier 24, are fed to the information inputs of the multiplexer. the inputs of the various multiplexers 1, 2, 3, 4 are numbers from the various outputs of the ring register. Let addresses 1, 2, 3, 4, respectively, be sent to multiplexers 1, 2, 3, 4 at a certain quantization cycle. So, the 1st multiplexer receives address 1 and passes the signal from its input 1 to the input 5 of block 24, 2 multiplexer - signal from its input 2 to 6 input of block 24, 3rd multiplexer - signal from input 3 to 7 input of block 24, 4th multiplexer - signal from input 4 to 8 input of block 24. At the next clock, the ring register will shift the sequence addresses - it will change and become 2, 3, 4, 1, i.e. the first multiplexer receives address 2 and passes the signal at its 2 input to the 5th input of block 24, the second multiplexer receives address 3 and transmits a signal from 3 of its input, the third multiplexer receives address 4 and passes the signal from its 4 inputs to the 7th input of block 24, the fourth the multiplexer at address 1 will pass the signal from its first input to the 8 input of block 24. On the next clock, the sequence of addresses will be 3, 4, 1, 2, then 4, 1, 2, 3 and, finally, again 1, 2, 3, 4 At the same time, although the cell numbers for the state coordinates change at each step, the first and second vector th blocks of the multipliers 24, 25 perform constant signal processing operations.

по соотношению (12). Память для записи коэффициентов q может реализовываться микросхемой К537 РУ8 - ОЗУ объемом 2 Кбайта (8 бит) или набором микросхем К155РУ2 (ОЗУ 64 бит) [4, стр. 167], мультиплексоры - К555КП15 [4, стр. 154], умножители - К555ИП9 [4, стр. 165,] либо 1802ВП5, первый и второй регистры-накопители 26, 27 могут реализовываться композицией нескольких К555ИМ6 (сумматор на два 4-разрядных слова), кольцевой регистр-счетчик - К155ИЕ9 [4, стр. 97] или КР1533ИЕ2 [5, стр. 160], аналогично счетчики в блоках векторного умножения 24, 25.All blocks and devices included in the filtering unit 6 can also be implemented on commercially available ICs of various series or their simple connections. Such an implementation of adder multipliers, counters, multiplexers on specific elements was disclosed earlier in the description of the filter code conversion block 5, in particular, the procedure and implementation of vector multiplication that performs the operation

by relation (12). The memory for recording the q coefficients can be implemented with the K537 RU8 chip - 2 Kbytes RAM (8 bits) or the K155RU2 chipset (64 bit RAM) [4, p. 167], multiplexers - K555KP15 [4, p. 154], multipliers - K555IP9 [4, p. 165,] or 1802VP5, the first and second drive registers 26, 27 can be implemented by the composition of several K555IM6 (adder for two 4-bit words), a ring register-counter - K155IE9 [4, p. 97] or KR1533IE2 [5, p. 160], similarly, counters in blocks of vector multiplication 24, 25.

APPENDIX 2 shows the results of mathematical modeling of the implementation of adjustment processes for a fourth-order digital filter, taking into account the finite accuracy of the representation of numbers. As can be seen from the graphs obtained from the simulation results, the frequency characteristics of the reference and rebuilt digital filters are almost very close in the operating frequency range with a significant change in the sampling frequency: a decrease of 2.5 times and an increase of 2.5 times.

. Технический результат от использования изобретения заключается в уменьшении искажения характеристик цифрового фильтра, в частности обеспечении расчетных запасов устойчивости при изменении частоты дискретизации входного сигнала. Изобретательский уровень предложенного технического решения подтверждается отличительной частью формулы изобретения.Thus, the proposed tunable digital filter with a programmable structure allows, by introducing new blocks and organizing new connections between them, to provide improved filtering properties due to the constancy of the filtering characteristics when the quantization frequency changes

. The technical result from the use of the invention is to reduce the distortion of the characteristics of the digital filter, in particular, providing estimated stability margins when changing the sampling frequency of the input signal. The inventive step of the proposed technical solution is confirmed by the distinctive part of the claims.

Sources used

1. Shamrikov B.M. Fundamentals of the theory of digital control systems: Textbook for higher technical educational institutions. - M., Mechanical Engineering, 1985. - 286 with silt.

2. RF patent No. 2399152 - prototype.

3. RF patent No. 2037364 - analogue.

4. Shilo V.L. Popular digital circuits. Directory. - M., Radio and communications, 1989 - 352 p., With ill.

5. Ugryumov EP Digital circuitry. - SPb .: BHV-Petersburg, 2004 .-- 528 p., With silt.

ANNEX 1

APPENDIX 2

MATHEMATICAL MODELING OF THE FILTER.

When modeling, a fourth-order digital filter was considered, the analog prototype of which was described by a transfer function of the form:

.

.

The calculated quantization frequency corresponded to f 0 = 80 Hz, T0 = 0.0125 s.

The reference digital filter corresponding to a given frequency was described by a z-transfer function of the form:

,

,

where the coefficients { a _i , b _i } are determined by the following values:

a ₀ = 0, a ₁ = 0.483, and ₂ = -. 705, and ₃ = .368, and ₀ = 0.066;

b ₀ = 1, b ₁ = -1.329, and ₂ = .615, and ₃ = -0.076, and ₀ = 0.0028.

The translation matrix in the normalized representation has the form:

From where the GJK vectors are determined by the expressions:

The recalculated parameters { a N _i , bN _i } of the filter are determined using the conversion matrix in the following form:

The calculations performed in the filter parameter conversion unit for a specific example of a fourth-order digital filter were modeled on a computer program implemented in the MATKAD environment.

In this case, all the mathematical operations of recalculation were performed in the sequence in which they are given in the description of the device, but with a special restriction on the accuracy of the representation of numbers and the accuracy of the computational operations.

The parameter of limited accuracy of calculations was 4 decimal places, which corresponds to 14 binary digits, i.e. almost 2 bytes.

Below are the simulation results - the frequency characteristics of the original reference filter, the recalculated filter and the original when the frequency increases and decreases. The results confirm the efficiency of the presented solutions - the characteristics of the tuned digital filter are close to the characteristics of the reference filter in the working frequency range of the digital system 0 <ω <2 min ( f 0, ft ).

Claims (5)

1. A tunable digital filter with a programmable structure, comprising an external settings device, a filter type code storage unit and a filtering unit connected in series, the output of an external settings device is connected to the input of the filter structure code storage unit, and through the clock pulse generating unit, to the second input of the filtering unit characterized in that it further comprises a pulse frequency identification unit and a filter code conversion unit, an output of the filter structure code storage unit through the conversion unit and the filter code is connected to the third input of the filtering unit, and the output of the clock pulse generating unit through the pulse frequency identification unit is connected to the second input of the filter code conversion unit. 2. Tunable digital filter with programmable structure according to claim 1, characterized in that the pulse frequency identification unit comprises a T-trigger, a first pulse generator and a pulse counter, wherein the input of the pulse frequency identification unit is connected via series-connected T-trigger, the first pulse generator and a pulse counter with the output of the frequency identification block pulses, and the second output of the T-trigger is connected to the second input of the first pulse generator. 3. Tunable programmable digital filter according to claim 1, characterized in that the filter code conversion unit comprises an adder, a relay with a first switch, a memory element block, a calculation parameter calculator, a multiplier register, a multiplexer, a switch counter, a multiplier, an accumulator accumulator, a parameter vector memory, a second generator pulses, the second switch, the second input of the filter code conversion unit is connected to the relay input through the adder, and through the first switch in series, the calculator of the conversion parameters, multiplexer, multiplier, adder are connected in series the switch, the parameter vector memory and the second switch with the output of the filter code conversion unit, the output of the memory element block through the multiplier register is connected to the second input of the multiplier, the second output of the conversion parameter calculator is connected through the second pulse generator to the input of the counter-switch, and the first, second, third and the fourth outputs of the counter-switch are connected respectively to the input of the block of memory elements, the second inputs of the multiplexer, the adder-drive and the memory block of the parameter vector, the fifth output is the count ika-switch connected to the second input of the second switch, the third input of which is connected to the first input of the filter code conversion unit.

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