RU2621181C1 - Cycle synchronization method with dynamic addressing recipient - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: in the cycle synchronization method with the dynamic addressing the recipient on the transmitting side, a pseudo-random sequence of the maximum length is formed by specifying the formation law and the initial phase of this sequence. On the transmitting side, the pseudo-random code sequence is formed from two consecutive sections in such a manner that the initial phase of the first portion corresponds to the first half of the recipient address and the phase of the second portion is stepwise shifted by an amount corresponding to the second half of the recipient address, and on the receiving side, the address sequence is formed by searching the initial phase of the maximum length pseudo-random sequence according to the "scoring area" by the dual basis method.

EFFECT: reducing the addressing time and the recipient address synchronization by performing simultaneous synchronizing and addressing.

2 cl, 5 dwg

Description

The invention relates to telecommunication systems and computer technology and may find application in devices for receiving information from a transmission channel or reproducing information with a high level of errors.

Currently, cyclic synchronization (phasing) methods are used in practice, in which pseudorandom sequences of a maximum period (M-sequence) are used as synchronizing (phasing) combinations, to determine which, as a rule, selection in the test section is used.

A device for synchronizing a pseudo-random sequence with a function for correcting errors [see 1. Patent for the invention of the Russian Federation No. 2486682, IPC H04L 7/02, H04W 8/20, publ. 06/27/2013], which implements a method for synchronizing a pseudo-random sequence of a maximum period in comparison with that received from the communication channel of the memory bandwidth with the local memory bandwidth formed on the basis of the received frequency bandwidth from the communication channel The device contains a first single-channel delay line (OLZ) for one bit, a controlled inverter, a first key, a linear recurrence register (LRR), a comparison unit, a second OLZ for one bit, a second key, a decoder, a communication channel quality detector, an addition unit, an error counter , counter of zeros with coincidences, third key, inverter “1”, counter of zeros with (mc) matches, memory device for selecting the number of correctable errors. The first OLZ, a controlled inverter, the first key, LRR with feedback, the comparison unit, as well as the second second OLZ for one bit and the second key, the key output and the input of the second OLZ for one bit are connected respectively to the output from the communication channel, respectively, connected to LRR input and output with feedback, another LRR output with feedback is connected to the decoder input, while the input of the first OLS is one bit, the input signal is applied to the other input of the comparison unit and the quality detector of the communication channel, the output being projector of the link quality is connected to the entry adding unit, the outputs of which are respectively connected to the data input of the error counter input of the counter to "0" on coincidence, the information input of the third switch and the input of the inverter to "1". The control input of the error counter is connected to the output of the counter “0” for coincidence, and the output is connected to the reset inputs of the zero counts for s and (m-c) matches. The output of the counter "0" on coincidently connected to the reset input of the error counter, the input of the inverter "1" and the control input of the third key. The output of the third key is connected to the control input of the controlled inverter. The information input of the counter “0” for (m-c) matches is connected to the inverter “1”, and the output is connected to the control inputs of the first key and second key. The output of the device for selecting the number of correctable errors is connected to the control input of the error counter.

The synchronization method implemented in this device is as follows. The formation of the local bandwidth on the basis of the adopted one is carried out by passing the bandwidth from the communication channel through the first key to the LRR with feedback, where the local bandwidth is formed, which then goes to the comparison unit. At the same time, the PSP from the communication channel enters the other input of the comparison unit. In the comparison block, the received and local PSPs are compared and, when they coincide, zeros are output to the addition block, where the operation of logical addition of the results of the previous comparison with the signals from the communication channel quality detector is performed. If there are no signals of the communication channel quality detector, the zeros from the comparison block through the addition block are sent to the counter “0” for coincidence and after coincidences in the comparison block, the counter signal “0” for coincidence resets the error counter, turns on the inverter “1” and closes the third key, after which the counter “0” is filled in for (mc) matches. When the counter is full, it provides a control signal to the first and second keys, which respectively disconnect the LRR with feedback from the channel and transfer the formation of the local memory bandwidth to offline mode. The transition to the mode of autonomous formation of the local PSP entails the operation of extracting the phase start signal in the decoder, to which the PSP receives a parallel code from the LRR with feedback. In this case, the selection of phase start signals at the reception and transmission occurs synchronously. Thus, from coincidences in the comparison block, it means conditional undistorted filling of LRR with feedbacks, controlled by the quality detector of the communication channel, and when filling the counter “0” to (m-c) matches, unconditional synchronization of LRR with feedbacks. If the inputs of the addition unit receive signals “1” from the detector of the quality of the communication channel and the comparison unit, then the error is recorded by the error counter, and the signal “1” from the addition unit is fed to the control input of the controlled inverter, which corrects the error at this moment in the second OLZ for one bit. In the inverter “1”, the signal “1” is converted to “0” and fed to the counter “0” for (mc) matches, which ensures that after the arrival of (mc) zeros the signal is transmitted to the first and second keys and translates the formation local memory bandwidth offline. If the number of detected and corrected errors installed in the device for selecting the number of correctable errors exceeds the permissible threshold M, then the error counter generates a “Reset” control signal for counters of zeros with coincidence and (mc) coincidences and LRR with feedback in offline mode not happening. Thus, the operation of forming a local memory bandwidth in an autonomous mode is performed depending on the signals coming from both the comparison unit and the quality detector of the communication channel, thereby making it possible to perform this operation if there are errors in the GD section in the received memory bandwidth by correcting them provided that their number does not exceed a predetermined threshold value M. If signals of opposite values are received at the inputs of the addition unit from the quality detector of the communication channel and the comparison unit, then this leads to the prohibition of the operation of the SRP synchronization device and indicates a malfunction of the device elements.

The method implemented in this device is used only for synchronization and does not allow the use of pseudorandom sequences of the maximum period for addressing devices.

Also known is a method for dynamically addressing correspondents of a mobile radio network and a device for its implementation [see 2. Patent for the invention of the Russian Federation No. 2557451, IPC H03D 7/00, Н04В 1/10, H04J 13/10, H04W 12/06, publ. July 20, 2015], in which the combination of the functions of code division of channels, addressing, synchronization, modulation and demodulation of the radio frequency signal, as well as authentication (addressing) of subscriber devices and encoding of voice information directly in the radio channel (at the physical and channel levels of the radio network) is organized.

This method consists in the fact that at the initial stage of establishing a connection, any correspondent downloads a pseudo-random code sequence generator for his receiver with a start code corresponding to his own number (address) or generated according to a certain law (known to all subscribers) based on this own number (address) and starts the self-synchronization procedure with the correspondents who are currently calling it, whose transmitters generate cyclic code sequences about boundedness lengths generated based on the start code, which corresponds to the number (address) of the correspondent called, i.e. generating exactly the code that the receiver of the called correspondent is currently waiting for. After the self-synchronization of the calling and called correspondents is completed, the calling correspondent receives the opportunity to transmit his own number (address) to the called correspondent, and the called correspondent is able to generate and load into the pseudo-random sequence generator of his transmitter a new code consisting of (or formed on the basis of) address codes of the calling and called correspondents, then start the generation of cyclic bounded pseudorandom code sequences starting from this code, while the calling correspondent, for which this code is a priori known, because it is generated according to well-defined rules based on the codes (addresses) known to the calling correspondent, starts with this code, the process of self-synchronizing your receiver. Upon completion of the self-synchronization procedure, the called correspondent is able to transmit any data and commands (including digital voice stream) to the calling correspondent via the newly formed (reverse) virtual radio channel. In the future, for definiteness, the transmitter and receiver registers, in which start addresses (codes) are generated and stored during connection establishment, with which they are loaded and based on which pseudorandom code sequences are generated by pseudorandom code sequences generators, necessary for generating a radio signal in the transmitter and processing it in the receiver will be called dynamic addressing registers.

The main parts of the device that implements the described method are the addressing and synchronization subsystems. The result of the operation of the addressing and synchronization subsystems is the formation of the corresponding pseudorandom code sequences necessary for the operation of the transmitter modulator and receiver demodulator in the process of establishing a connection and transmitting information.

To ensure synchronization, it is necessary that the transmitting subscriber repeatedly (cyclically) transmit, and the receiver was ready to receive (process) the same repeatedly (cyclically) repeating code sequence, i.e. the starting pseudo-random code sequence generated by the transmitter and processed by the receiver using identical generators (with the same formation laws) with completely identical parameters (starting addresses). In the simplest case, pseudo-random code sequences can be generated using shift registers with linear and nonlinear feedbacks. Before starting work, the very law of generating a pseudo-random code sequence is determined by hardware methods (by introducing the appropriate feedbacks of such a “register”), and the “initial phase” of the generated pseudo-random code sequence can be set (defined) by one or another specific starting code combination (starting address) loaded into the start address registers of the pseudorandom code sequence generators of the transmitter and receiver of the subscriber set, respectively. If the starting combination and the law of generating pseudo-random code sequences for the transmitting and receiving subscribers coincide, the synchronization system based on the principle of correlation comparison of signals described earlier, during a certain period of time, called the synchronization time, will ensure that the subscriber-receiver is in communication with the subscriber-transmitter (a virtual radio channel will be formed), and therefore, subsequent reception of digital information via this virtual radio channel will be possible mation on which, in turn, will be possible reception codes (addresses and commands) and the subsequent control by the subscriber as a receiver, and control the actual process transceiving means of these special commands transmitted via the formed radio channel.

Thus, the subscriber synchronization subsystem must ensure that those subscribers who have the same digital code “loaded” into the start address registers of the pseudorandom code sequences of the transmitter and receiver are entered into the communication. The subscriber addressing subsystem should provide “loading”, at the right time, of the required codes to the start address registers of cyclic pseudo-random code sequences of complementary - receiving and transmitting - subscriber devices during their entry into communication (synchronization) and during the subsequent connection establishment (channel formation) procedure, transmitting and processing channel control commands (on the forward and reverse radio channels), as well as during the transmission of digital voice information.

This method is closest in technical essence to the claimed invention and is selected as a prototype.

However, in this method, the addressing and synchronization functions are separated, which leads to an increase in the time of their implementation. In addition, in the prototype, many recipients will be able to determine the end of the phasing sequence common to them and begin analyzing the incoming frame by highlighting the recipient’s address in a special field, which is often transmitted in clear text, which to some extent reduces the level of protection (recipient privacy).

The technical result of the invention is to reduce the addressing and synchronization time and increase the level of protection of the recipient address by simultaneously synchronizing and addressing.

The indicated technical result is achieved in the method of cyclic synchronization with dynamic addressing of the recipient, in which a maximum random code sequence of maximum length is formed on the transmitting side, setting the formation law and the initial phase of this sequence, characterized in that on the transmitting side a pseudo-random code sequence is formed of two consecutive sections such so that the initial phase of the first section corresponds to the first half of the recipient address, and the second phase th section is shifted stepwise by a value corresponding to the second half of the destination address and the reception side address sequence is formed by searching the initial phase of the pseudorandom sequence of the maximum length "section GOAL" method dual basis.

Moreover, the length of each of two consecutive sections of the pseudo-random code sequence can be equal to the period of the M-sequence.

The achievement of the specified technical result in the proposed method is provided as follows.

Since in the proposed method the decision to start can only be made by the recipient to whom the message is addressed, this provides increased security for starting the receiver. In this case, simultaneously with the selection of the end of the phasing composite sequence, the recipient address will be determined, which will allow this recipient to further receive and process the frame and combine the synchronization and addressing process. In the prototype, many recipients will be able to determine the end of the phasing sequence common to them and begin analyzing the incoming frame by highlighting the recipient’s address in a special field, which is often transmitted in clear form, which to some extent reduces the level of protection (recipient privacy) and also increases the synchronization time and addressing.

An additional advantage is that the allocation of "test sites" at the reception, in contrast to the prototype, is carried out by the dual basis method [O. Kognovitsky The dual basis and its application in telecommunications. Link, St. Petersburg, 2009]. This means that to identify the phase in the proposed method, it is necessary to allocate only to the elements, whereas in the prototype to identify the recurrent received sequence it is necessary to select at least (k + 1) element. This provides in the proposed method an additional contribution to reducing the time of synchronization and addressing.

The proposed method is illustrated by drawings, where in FIG. 1 and 2 are structural diagrams of the blocks of the transmitting and receiving sides of the device for implementing the proposed method, FIG. 3 shows the structure of a processing block of k-element sections based on a dual basis, FIG. 4 shows the structure of the allocation block of the “test section” of the first part of the linear recurrence sequence of the address-phasing combination (ROS), in FIG. 5 - the structure of the block allocation "test plot" of the second part of the linear recurrent sequence ROS. According to FIG. 1 on the transmitting side there are:

1 - sensor of the element of the field element C from GF (2 ^k );

2 - generator of direct field elements (HEPP) GF (2 ^k );

3 - block function calculation trace T (ε ⁱ ) - adder;

4 - decoder of the end of the I-th PSP;

5, 6 - blocks of key schemes I1 and I2, respectively;

7 - trigger;

8 - sensor of the element vector of the field D from GF (2 ^k );

9 - multiplier of the elements of the field GF (2 ^k );

10 - block key schemes I3;

11 - decoder of the end of the II-nd PSP and the entire ROS.

At the same time, the signal of setting the field element C and the “Start” command, respectively, are supplied to the first and second inputs of the sensor 1 of the field element vector of the field C from GF (2 ^k ), and the output of the sensor 1 is connected to the first input of the generator 2 of the direct field elements (HEP) GF ( 2 ^k ), to the second input of which the output of the multiplier of 9 elements of the field GF (2 ^k ) is connected, and the second input of the trigger 7 and the output of the decoder of the end of the second PSP and the entire addressing-phasing combination (AFK) are connected to the third input of the generator 2, the output generator 2 is connected to the inputs of the decoder 4 of the end of the I-th PSP, block 6 key m H2, block 10 key schemes I3 and block 3 function computing - track T (ε ⁱ⁾ (combiner) whose output is the output of the transmitter, the second input unit 6, the key circuit I2 is connected to the second input unit 5 control circuits I1, the output of the decoder 4 the end of the I-th SRP and the first input of the trigger 7, the output of which is connected to the second input of the block of key circuits I3, the output of which is connected to the input of the decoder 11 of the end of the II-rd SRP and the entire AFK, the first input of the block 5 of the key circuits I1 is connected to the output of the sensor 8 vector of an element of the field D from GF (2 ^k ).

According to FIG. 2 on the receiving side are:

12 - key;

13 - shift register for k bits;

14 is a block processing k-element sections of the recurrence sequence based on the dual basis;

15 - managed switch;

16 - block allocation "test plot" of the first part of the recurrence sequence;

17 - generator of direct elements of the field GF (2 ^k );

18 - decoder field element ε ^{N-k + 1} ;

19 - block allocation "test plot" of the second part of the recurrence sequence;

20 is a control diagram.

In this case, the input of the receiving part is the first input of the key 12, to the second input of which, as well as to the second input of the managed switch 15 and the first input of the block “highlighting section” 16 of the first part of the recurrence sequence, the “Start” signal is issued, the output of key 12 is connected to the input of the shift register 13 by k bits, the output of which is connected to the input of the block 14 for processing k-element sections of the recurrence sequence based on the dual basis, the output of which is connected to the first input of the managed switch 15, the third input which is connected to the second input of the block "allocation" of the test section of the first part of the recurrence sequence, and the output of the decoder 18 of the field element ε ^{N-k + 1} , the third input of block 19 is connected to the second input of the setting “0” of the generator 17 of the direct elements of the field GF (2 ^k ) and with the output of the control circuit 20, which is the installation output, the first input of the generator 17 is connected to the output of block 16, the second input of which is connected to the first output of the managed switch 15, the second output of which is connected to the first input of block 19, the output to the one associated with the input of the control circuit 20 is the output "End AFK" of the receiving part.

According to FIG. 3, the block 14 for processing k-element sections of a recurrence sequence based on a dual basis contains sequentially connected 14.1 - matrix multiplier in the field GF (2 ^k ) row vectors of k elements of the recurrence sequence by a column vector from the coefficients of the dual basis and 14.2 - multiplier of field elements GF (2 ^k ) per element C ^-1 .

According to FIG. 4, the block 16 allocation "test plot" of the first part of the linear recurrent sequence ROS contains:

16.1, 16.3 - devices for storing elements of the field GF (2 ^k );

16.2 - multiplier by a field element ε ∈ GF (2 ^k );

16.4 - comparator;

16.5 - counter for L consecutive matches;

16.6 is a key outline.

In this case, the signal from the first output of the managed switch 15 is sent to the input of the device 16.1 for memorizing the elements of the field GF (2 ^k ), the output of the device 16.1 is connected to the input of the multiplier 16.2 to the element of the field ε ∈ GF (2 ^k ) and one of the inputs of the comparator 16.4, to the other the input of which is connected to the first input of the key circuit 16.6 and the output of the device 16.3 for storing elements of the field GF (2 ^k ), the input of which is connected to the output of the multiplier 16.2, the start signal is supplied to the first output of the comparator 16.4 and the first input of the counter 16.5 of L-serial matches, and the second output of the comparator 16. 4 is connected to the second input of the counter 16.5, the output of which is connected to the second input of the key circuit 16.6, the output of which is the output of the block 16 allocation "test plot" of the first part of the linear recursive sequence ROS.

According to figure 5, the block 19 allocation "test plot" of the second part of the linear recurrent sequence ROS contains:

19.1 - multiplier of the elements of the field GF (2 ^k );

19.2 - generator of the inverse elements of the field GF (2 ^k );

19.3 - decoder element of the field D (second half of the recipient address);

19.4 - counter of the number of consecutive elements D with capacity L;

19.5 - field element decoder ε ^{- (Nk)} ;

19.6 - the key.

At the same time, input 1 of the multiplier of field elements 19.1 through the key circuit 15 receives k-element combinations in the form of elements of the field GF (2 ^k ) from the output of block 14 for processing k-element sections of the recurrence sequence based on the dual basis, and input 2 of multiplier 19.1 and the input of the decoder 19.5 of the element of the field ε ^{- (Nk)} receives the elements from the output of the generator of the inverse elements 19.2, into which when it was started, “1” was set by the signal from the output of the decoder 18 of the element of the field ε ^{N-k + 1} . The output of the multiplier 19.1 is connected to the input of the decoder 19.3 of the field element D (second half of the recipient address), the first output of which is connected to the first input of the counter 19.4 of the number of consecutive elements D of capacity L, the second output of the decoder 19.3 is connected to the second input of the counter 19.4, the output of which is connected to the first the key input 19.6, the second input of which is connected to the output of the decoder 19.5, and the output of the key 19.6 is the output of the “End AFK” signal, and the Reset to “0” signal is sent to the second input of the generator 19.2.

The proposed method is carried out in this device as follows.

In the transmitting part (Fig. 1) for the formation and transmission of the address-phasing sequence by the “Start” command, the first phase of the first part of the recurrence sequence (M-sequence) is recorded from the sensor 1 into the generator 2 as an element of the Galois field GF (2 ^k ) corresponding to the first half of the address of the recipient C, and clock-wise operation of the generator 2 of the direct elements of the field GF (2 ^k ) from the initial element C, which belongs to GF (2 ^k ), is allowed under the control of clock pulses coming from the clock generator (not azan on the diagrams). The arrival of each clock pulse of the sequence forms in the generator 2 field elements C, Cε, Cε ² , ..., where ε is the antiderivative field element (the root of the characteristic polynomial P (x) of the recurrence sequence (M-sequence). 2 field elements GF formed at the output of the generator (2 ^k ) in the form of k-element parallel binary combinations are sent to block 3 for calculating the trace function T (Cε ⁱ ), i = 0, 1, 2, ..., from the elements of the field C, Cε, Cε ² , ... The calculation results in in the form of sequential binary elements s _i = Т (Сε ⁱ ), representing p an ecurrent sequence (M-sequence) is sent to the “Output” of the transmission unit. In parallel, k-element combinations from the output of the generator 2 are sent to the decoder 4 of the end of the first part of the recurrence sequence and to blocks 6 and 10 of the key circuits that are opened by the signal from the output of the decoder 4 . At the same time, the k-element combination corresponding to the element of the field GF (2 ^k ), which is the second part of the address D, and to the second inputs of the multiplier 9 hours, enter the first inputs of the multiplier of 9 elements of the field GF (2 ^k ) Through key schemes 6, an element of the field ε ⁱ is supplied from generator 2 in the form of a parallel k-element combination. The product of these elements D⋅ε ⁱ in the form of a parallel k-element combination from the output of the multiplier 9 goes to the second (2) inputs of the generator 2, abruptly changing from that moment the phase of the generated field elements by D and, accordingly, shifting the phase formed at the output stepwise block 3 of the recurrence sequence.

Thus, after the operation of the decoder 4 from the output of block 3, the formation of the second part of the recurrence sequence begins, phase shifted relative to the first part of the recurrence sequence by an amount corresponding to the second half of the recipient address (C, D). At the same time, the signal from the output of the decoder 4 is set to the active state (in "1") trigger 7, opening the input block 2 of the key circuits 10 and thereby skipping the k-element combinations from the output of the generator 2 to the input of the decoder 11 at the end of the second part of the recurrence sequence. When the k-element combination corresponding to the end of the second part of the recurrence sequence appears at the output of generator 2, the decoder 11 will work, the signal from the output of which will reset the generator 2 and trigger 7 to the zero state, and will also be the output signal of the end of the addressing-phasing combination (ROS) and the beginning of the formation of the remaining fields of the channel level frame.

In the receiving part (Fig. 2), by the “Start” command, the block 16 for allocating the “test section” of the first recurrence sequence (M-sequence) of the address-phasing combination (AFK) is initialized, the output 1 of the switch 15 is connected to its input 1 and closes the key 12, connecting the input of the k-bit register 13 to the communication channel ("Input"). Under the action of clock pulses generated by the clock generator (not shown in the receiver unit diagram), the contents of the register cells 13 with each clock cycle are shifted to the right by one step and are simultaneously read to the output circuits of the register cells 13, arriving at the input circuits of the processing unit 14 k -element areas based on a dual basis. When sequentially filling shift register 13 with error-free k-element combinations, block 14, based on the dual basis, will each time generate output elements of field 1, ε, ε ² , ε ³ ... at its output, and a single element will be formed when register cells 13 there will be an initial k-element error-free combination of the first part of the recurrence sequence (s ₀ , s ₁ , ..., s _k-1 ), element ε - when in the register cells there will be a combination (s ₁ , s ₂ , ..., s _k ) and t .d.

The elements of the field GF (2 ^k ) thus formed from the output of block 14 through the switch 15 are fed to the input 2 of the block 16 for allocating an error-free “test section” of length m = k + L-1, where k is the number of cells in shift register 13, L is the capacity threshold counter in block 16. Upon receipt of m error-free binary elements of the first part of the recurrence sequence from the communication channel, starting, for example, from element s _i , at the output of block 14, L consecutive elements of the field GF (2 ^k ) ε ⁱ , ε ^{i + 1} , ..., ε ^{i + L-1} , as a result of which the threshold counter on L as part of block 16 is disabled it melts and ensures that the output of block 16 of the field element ε ^{i + L-1} , which is written to the generator 17 of the direct elements of the field GF (2 ^k ). The generator 17 under the action of clock pulses will start to generate in a standalone mode the sequential field elements ε ^{1 + L-1} , ε ^{i + L} , ε ^{i + L + 1} , ...,. The generation of consecutive field elements will continue in an autonomous mode until ε ^{N-k + 1 is} established in the generator 17. In this case, the decoder 18 is connected, connected to the output of the generator 17 direct field elements. The output signal of the decoder 18 enters the input 2 of the block 19 allocation "test plot" of the second part of the recurrence sequence, setting "1" in the cells of the generator of the inverse field elements in the block 19 and in parallel to the input 3 of the switch 15, thereby connecting the input 1 of the switch 15 with its output 2. From now on, under the influence of clock pulses, k-element combinations in the form of consecutive elements of the field GF (2 ^k ) from the output of block 14 through the switch 15 go to input 1 of block 19. If the device receives error-free input k-element sections of the second part of the recurrence sequence (v _i , v _{i + 1} , ..., v _{i + k-1} ), i = 0, 1, 2 ..., in block 19, based on the dual basis, the element D will be calculated, which is the second half of the recipient address (C, D). After selecting the “test section”, consisting of L consecutively selected D elements, the generator 19.2 of the inverse elements of the field GF (2 ^k ) as part of block 19 will go into stand-alone operation until the element ε ^{- ( Nk)} , where N is the length of the second part of the recurrence sequence. At the same time, at the output of block 19, the end signal of the address-phasing combination (ROS) will appear. The same signal will simultaneously be fed to the input of the control circuit 20, which will operate and its output signal will go to input 2 of the direct element generator of field 17 and set it to “0”, at the same time the same signal will be fed to input 3 of block 19 and reset to “0” the generator of the inverse elements of the field GF (2 ^k ) in the block 19. Thus, the receiving block will be restored to its original state.

In block 14 for processing k-element sections of the received recurrence sequence (Fig. 3), at each clock cycle of the receiving part of the device, the k-bit combination from the outputs of the cells of the shift register 13 is supplied by the parallel code to the input of the matrix multiplier 14.1, in which the multiplication in the extended field GF (2 ^k ) row vectors [s _i , s _{i + 1} , ..., s _{i + k-1} ] (or [v _i , v _{i + 1} , ..., v _{i + k-1} ]) per column vector from the coefficients of the dual basis

As a result of multiplication, the field element in the form of a k-bit vector will appear at the output of block 14.1, which will go to the input of block 14.2 of multiplying the received field element by a constant factor - a coefficient representing an element of the field C ^-1 , i.e. field element, inverse of element C. The result of multiplication will be sent to the output of block 14 in the form of a k-bit combination of elements of a simple field GF (2).

In block 16, the allocation of the "test section" of the first part of the recurrence sequence (Fig. 4) with each clock cycle of the receiving part of the device, a k-bit combination corresponding to a certain element ε ^{i of the} field GF (2 ^k ), from the output of block 14 for processing k-element sections the recurrence sequence through the switch 15 is fed to the input of the k-element combination memory device 16.1, which then goes in parallel to the input of the multiplier 16.2 to the element s of the field GF (2 ^k ) and to the input 1 of the comparator 16.4.

The result of the multiplication from the output of block 16.2 in the form of an element ε ^{i + 1 is} recorded in the storage device 16.3. With the next clock cycle, the memory element 16.1 will receive the element ε ^{i + 1} to the input 1 of the comparator 16.4, and the input 2 of the comparator 16.4 will receive a field element from the output of the memory device 16.3. If the values of the field elements at the inputs 1 and 2 of the comparator 16.4 are the same, then at the output 2 of the comparator 16.4 a signal +1 will appear, increasing by one the reading of the counter 16.5 by L consecutive matches. If the compared elements do not match, a signal will appear at the output 1 of the comparator 16.4, which, like the “Start” command, will set the counter 16.5 to the state “1”. When the counter (threshold element) 16.5 on L consecutive matches works, then a signal will appear on its output, which will go to input 2 of the key circuit 16.6 and allow the passage of the k-element combination in the form of an element of the field ε ^j to the output of circuit 16.6, i.e. to the output of block 16.

In block 19, the allocation of the "test plot" of the second part of the address-phasing recursive sequence (figure 5) to the input 1 of the multiplier of the elements of the field 19.1 through the key circuit 15 receives k-element combinations in the form of elements of the field GF (2 ^k ) from the output of the processing unit 14 k-element sections of the recurrence sequence based on the dual basis, and input 2 of the multiplier 19.1 receives elements from the output of the inverse element generator 19.2, into which, when it was started, it was set to “1” by the signal from the output of the field element decoder 18 ε ^{-N-k + 1} . In the case of error-free reception of k-element sections of the second part of the recurrence sequence at the output of the multiplier 19.1, an element D will be formed corresponding to the second half of the recipient address (C, D). This element D from the output of the multiplier 19.1 goes to the decoder 19.3 of the element D. If the decoder 19.3 receives the element D at its output 1, a signal will appear that goes to the counting input 1 of the threshold counter 19.4, counting L consecutive signals from the output of the decoder 19.3.

When the decoder 19.3 L is triggered consecutively, the counter 19.4 will fill up and give a constant signal at its output, which will keep the key 19.6 in the open state until the decoder 19.5, tuned to the field element ε ^{- (Nk)} , goes to the decoder input 19.5 from the output of the generator of the inverse elements of the field 19.2. The signal from the output of the decoder 19.5 enters through the public key 19.6 to the output of the device and will be the signal "End of the address-phasing sequence" and the beginning of the remaining fields of the channel level frame.

At the same time, the signal from the output of the key 19.6 is fed to the input of the control circuit 20, which will operate and generate a control signal at its output, fed to the input 2 of the generator 19.2 of the inverse field elements, setting it to “0”, and to the input 2 of the generator 17 of the direct elements of the field GF (2 ^k ), setting it to "0".

Note that in the case when a field element other than D arrives at the input of the decoder 19.3 and the counter 19.4 has not yet been filled, a signal will appear at the output 2 of the decoder 19.3, which will go to the input 2 of the counter 19.4 and zero it.

Elements of the device for implementing the proposed method can be performed either on the basis of standard logic elements (K155, KP1554 and KP1561 microcircuits), or on the basis of CPLD or FPGA FPGAs (for example, FPGAs manufactured by Altera and Xilinx).

Claims (2)

1. A method of cyclic synchronization with dynamic addressing of the recipient, in which a maximum random code sequence of maximum length is formed on the transmitting side, setting the formation law and the initial phase of this sequence, characterized in that a pseudo-random code sequence consisting of two consecutive sections is formed on the transmitting side, such so that the initial phase of the first section corresponds to the first half of the recipient address, and the phase of the second section is abruptly shifted by the value corresponding to the second half of the recipient’s address, and on the receiving side an address sequence is formed by searching for the initial phase of the pseudorandom sequence of maximum length in the “test section” using the dual basis method. 2. The method according to p. 1, characterized in that the length of each of two consecutive sections of the pseudo-random code sequence is equal to the period of the M-sequence.

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