RU2601829C2 - Sign-variable signals clipping device - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to radio engineering and serves for analogue alternating-sign signals converting into rectangular pulses. Device consists of three comparators, three triggers and logical element “AND”. of First comparator output is connected to D-trigger clock input, which D-input is logical unit fixed level input, second comparator output is connected to first and second RS-triggers resetting inputs, first RS-trigger setting input is connected to third comparator output, which direct input is connected to device input, second RS-trigger setting input is connected to “AND” element output. First input of which is connected to first RS-trigger output, and second input is connected with first comparator inverting output, second RS-trigger output is connected with D-trigger resetting input. First comparator inverting input is first threshold voltage input, third comparator inverting input is second threshold voltage input, second comparator direct input is third threshold voltage input.

EFFECT: technical result consists in producing undistorted duration pulses in absence of interferences and reduction of pulses distortions in presence of interferences, since device provides absence of hysteresis characteristic.

3 cl, 3 dwg

Description

The invention relates to radio engineering, is used to convert analog alternating signals into rectangular pulses and can be used to build digital signal processing tools and measure their parameters.

As a rule, an analog comparator is used as a device for clipping signals, an analog clipped signal is supplied to one of its inputs, and a threshold level equal to zero or close to it is applied to the other, see, for example, [Reference on nonlinear circuits / Ed. . D. Sheingold. - M .: Mir, 1977, pp. 20-22]. A well-known disadvantage of such a device is its low noise immunity. The presence of interference at the input of the comparator leads to a series of short false pulses near the edges of the output pulse, which is explained by the multiple crossing of the threshold level by the input signal in areas where its instantaneous values are close to the threshold level. To eliminate the appearance of false pulses, two of the most common methods are used. The first one provides for the formation, in response to the first actuation of the comparator, of a “clean” pulse, the duration of which is given by a single-vibrator introduced into the circuit and connected to the output of the comparator. This approach provides effective suppression of false pulses, but it is also of limited use, since only the information about the moments when the signal crosses the threshold level when it passes through zero with only one sign of the derivative (when changing the sign of instantaneous values in one direction) is stored in the output pulse sequence, and information about the half-wavelengths of clipped signals is lost. More information can save a second method comprises administering to the switching characteristics of the hysteresis device, that is the task switching level U _ITP and level off U _ITN, for which the following condition: U _ITP> U _ITN [Avanesyan GR Digital integrated circuits. Reference manual. - M .: Radio engineering, 2008, p. 93-93, fig. 2.19]. In this case, when the noise level is determined by the width of the artificially created hysteresis loop, false pulses can be avoided, but the duration of the output pulse is distorted. If threshold levels have the same sign, the duration is reduced. Moreover, the output pulse will be distorted both in the presence of interference, and in their complete absence or insignificant level, not leading to repeated trips of the comparator. An example of such a device, which provides the ability to control threshold levels (levels of response), is the technical solution described in [Pat. RU 2007855. Publ. 02.15.1994], taken as a prototype. The specified device contains two comparators and a D-trigger, the output of which is the output of the device, and the input is the combined direct input of the first comparator and the inverting input of the second comparator, the inverting input of the first comparator is the input of the first threshold voltage, the direct input of the second comparator is the input of the second threshold voltage, the output of the second comparator is connected to the clock input of the D-trigger, the output of the first comparator through a differentiating chain is connected to the input of the asynchronous installation in the unit of the D-trigger An era whose D-input is connected to its inverse output.

The technical result achieved when using the present invention consists mainly in the possibility of obtaining pulses of undistorted duration in the absence of interference and to reduce distortion of pulses in the presence of interference.

The technical result is achieved by the fact that in the device for clipping alternating signals containing two comparators and a D-trigger, the output of which is the output of the device, and the input is the combined direct input of the first comparator and the inverting input of the second comparator, according to the invention, a third comparator, two RS -trigger and element And, the output of the first comparator is connected to the clock input of the D-trigger, the D-input of which is an input of a fixed level of a logical unit, the output of the second comparator is connected to zero input inputs of the first and second RS-flip-flops, the installation input of the first RS-flip-flop is connected to the output of the third comparator, the direct input of which is connected to the input of the device, the installation input of the second RS-flip-flop is connected to the output of the element And, the first input of which is connected to the output of the first RS- trigger, and the second input with the inverse output of the first comparator, the output of the second RS-trigger is connected to the zeroing input of the D-trigger, the inverting input of the first comparator is the input of the first threshold voltage, inverting the input of the third a comparator input of the second threshold voltage, the direct input of the second comparator is input to the third threshold voltage.

The invention is illustrated by graphic material. In FIG. 1 shows a functional diagram of the device, FIG. 2 is a timing diagram explaining the principle of operation of the device, and in FIG. 3 are graphs illustrating a reduction in clipping errors.

The functional diagram of FIG. 1 contains three analog comparators 1, 2, 3, D-flip-flop 4, two RS-flip-flops 5, 6 and logic element 7. 7. The input u (t) of the device is the combined direct inputs of the comparators 1, 2 and the inverting input of the comparator 3, the output comparator 1 is connected to the clock input of the D-flip-flop 4, the D-input of which is an input of a fixed level of a logical unit, the output of the comparator 3 is connected to the zeroing inputs of the RS-flip-flops 5, 6, the installation input of the RS-flip-flop 5 is connected to the output of the comparator 2, the installation input RS-trigger 6 is connected to the output of the element And 7, the first input to which is connected to the output of the RS-trigger 5, and the second input to the inverse output of the comparator 1, the output of the RS-trigger 6 is connected to the zeroing input of the D-trigger 4, the inverting input of the comparator 1 is connected to the zero potential bus, the inverting input of the comparator 2 is the threshold input voltage U _ITP , the direct input of the comparator 3 is the input of the threshold voltage U _ITN .

Timing diagrams (Fig. 2) contain an input u (t) sinusoidal signal without interference (left in the graph) and enriched with interference (right), as well as pulses:

- at the output of the comparator 1 - x1;

- at the inverted output of the comparator 1 - x1-1;

- at the output of the comparator 2 - x2;

- at the output of the comparator 3 - x3;

- at the output of the RS-trigger 5 - x4;

- at the output of the RS-trigger 6 - R;

- at the output of the device.

In the graphs of FIG. Figure 3 shows three cases of the dependence of the error τ on the voltage U _ITP for sinusoidal signals with a period of 0.5 ms, 1 ms, and 2 ms.

, срабатывает компаратор 1 (на выходе x1 устанавливается высокий логический уровень), и по переднему фронту импульса на его выходе D-триггер 4 переходит в состояние логической единицы на выходе (формируется передний фронт выходного импульса). Далее, в момент равенства входного напряжения u(t) пороговому напряжению включения U_ITP, срабатывает компаратор 2 (на выходе х2 устанавливается высокий логический уровень), в связи с чем RS-триггер 5 переходит в состояние логической единицы на выходе (выход х4) - таким образом фиксируется признак того, что входной сигнал превысил некоторый заданный пороговый уровень U_ITP, превышающий уровень помех. В момент перехода сигналом u(t) нулевого уровня, при смене положительного знака на отрицательный (

), на инверсном выходе компаратора 1 появляется высокий логический уровень, который через элемент И 7 передается на установочный вход RS-триггера 6, переводящий последний в состояние логической единицы на выходе (выход R). Появившийся в результате указанного распределения уровней высокий логический уровень R на выходе RS-триггера 6 поступает на вход асинхронного обнуления D-триггера 4, который переходит в исходное состояние, формируя таким образом отрицательный фронт выходного импульса. Далее, при u(t)<0, в момент наступления равенства u(t)=U_ITN срабатывает компаратор 3, обнуляющий RS-триггеры 5, 6 и формирующий таким образом задний фронт импульса обнуления.The device operates (see Fig. 1) as follows. Upon the input of an analog alternating signal u (t), for example, sinusoidal, as shown in FIG. 2 on the left, at the moment it intersects the zero level, that is, for u (t) = 0 and

, comparator 1 is triggered (at the output x1 a high logic level is set), and on the leading edge of the pulse at its output, D-trigger 4 switches to the state of the logic unit at the output (the leading edge of the output pulse is formed). Further, at the moment the input voltage u (t) is equal to the switching on voltage U _ITP , comparator 2 is triggered (high logic level is set at the output x2), and therefore the RS-trigger 5 switches to the state of the logic unit at the output (output x4) - thus, a sign is detected that the input signal has exceeded some predetermined threshold level U _ITP , exceeding the interference level. At the moment of transition by signal u (t) of the zero level, when changing the positive sign to the negative (

), a high logic level appears at the inverted output of comparator 1, which is transmitted through the And 7 element to the installation input of the RS-trigger 6, which transfers the latter to the state of the logic unit at the output (output R). The high logical level R that appeared as a result of the indicated distribution of levels at the output of the RS flip-flop 6 is fed to the input of the asynchronous zeroing of the D-flip-flop 4, which goes into the initial state, thereby forming a negative edge of the output pulse. Further, with u (t) <0, at the moment of equality u (t) = U _ITN, the comparator 3 is triggered, zeroing the RS-triggers 5, 6 and thus forming the trailing edge of the zeroing pulse.

The described operation of the device occurred under the assumption that there was no interference at the input, and a pure sinusoidal signal was subjected to clipping. From the shown, including the content of the left side of the time diagrams corresponding to the sinusoidal input action, it is easy to see that the fronts of the output pulse were formed strictly at the moments of transition by a signal of zero level, i.e., clipping occurred without distortion, while maintaining the pulse duration equal to the duration of the positive half-wave of the input signal.

, срабатывает компаратор 1 и D-триггер 4 переходит в состояние высокого логического уровня на выходе - происходит формирование переднего фронта выходного импульса. Следующие случайные пересечения нулевого уровня, вызванные возвратом сигнала в отрицательную область и выходом из нее, на состоянии выхода устройства не отражаются, так как ложные импульсы в окрестности переднего фронта выходного импульса уже не могут оказать влияние на состояние D-триггера 4. С ростом входного напряжения, при v(t)=U_ITP, срабатывает компаратор 2, в связи с чем на выходе RS-триггера 5 (выход х4) появляется высокий логический уровень, и схема переходит в режим ожидания первого пересечения нулевого уровня при

. При наступлении равенства v(t)=0, появившийся на инверсном выходе компаратора 1 первый положительный перепад напряжений (выход x1-1) переводит RS-триггер 6 в состояние высокого логического уровня на выходе (выход R). Таким образом, с первым коротким импульсом из серии ложных импульсов в окрестности отрицательного фронта импульса на выходе компаратора 1 происходит обнуление D-триггера 4 и завершение формирования импульса на выходе устройства. Однако снятие активного уровня обнуления с обнуляющего входа D-триггера 4 произойдет только после того, как случайная составляющая сигнала v(t) не сможет вернуть D-триггер 4 в состояние высокого логического уровня на выходе. Это обеспечивается заданием такого значения напряжения отключения U_ITN, при котором изменения мгновенных значений n(t) уже не переведут сигнал v(t) в положительную область. Для этого U_ITN выбирают исходя из условия:Let us further consider the case of the input of the signal v (t) = u (t) + n (t), which is the sum of the sinusoidal useful signal u (t) and the noise n (t), as shown in the right part of the time diagrams of FIG. 2. At the first crossing of the zero level by the signal v (t) in the region corresponding to the condition

, comparator 1 is triggered and D-flip-flop 4 enters a state of high logic level at the output - the leading edge of the output pulse is formed. The following random intersections of the zero level, caused by the return of the signal to the negative region and exit from it, are not reflected in the output state of the device, since false pulses in the vicinity of the leading edge of the output pulse can no longer affect the state of D-trigger 4. With increasing input voltage , when v (t) = U _ITP , comparator 2 is triggered, and therefore, a high logic level appears at the output of the RS flip-flop 5 (output x4), and the circuit goes into standby mode at the first crossing of the zero level at

. When equality v (t) = 0 occurs, the first positive voltage drop that appears on the inverted output of comparator 1 (output x1-1) puts the RS-flip-flop 6 into a state of high logic level at the output (output R). Thus, with the first short pulse from a series of false pulses in the vicinity of the negative pulse front at the output of the comparator 1, the D-trigger 4 is zeroed and the pulse formation is completed at the output of the device. However, the removal of the active level of zeroing from the zeroing input of the D-trigger 4 will occur only after the random component of the signal v (t) cannot return the D-trigger 4 to the state of a high logic level at the output. This is ensured by setting such a value of the shutdown voltage U _ITN at which changes in the instantaneous values of n (t) no longer transfer the signal v (t) to the positive region. For this, U _{ITN is} selected based on the condition:

where max | n (t) | - the maximum possible instantaneous value of the interference modulus n (t).

The choice in this way of the voltage module U _ITN , which must be negative, will cause the asynchronous zeroing pulse R to hold the D-trigger 4 in the zeroed state until the instantaneous values of the signal v (t) are guaranteed to be in the negative region .

с периодом Т, если принять за результат величину τ, равную разности между истинной длительностью выходного импульса Т/2 и длительностью T_X, полученной при клиппировании сигнала в схеме с гистерезисом. Будем полагать, что гистерезисная характеристика смещает только передний фронт выходного импульса, то есть U_ITP>0, a U_ITN=0. В этом случае, если исходить из того, что длительность импульса х2 (см. фиг. 2), полученная на уровне U_ITP, равна

, то величина T_X определится из выражения:Thus, both in the presence of interference imposed on the useful signal and in the absence thereof, the leading edge of the output pulse is formed strictly at the moment of the first intersection of the zero level with the input signal when the sign changes from negative to positive, and the rear one - at the first intersection of the zero level at change sign from positive to negative. The reduction in the distortion of the output pulse duration in the presence of interference is obvious, since according to the principle of the device, the threshold level U _ITP does not affect the moment of formation of the leading edge of the output pulse and, therefore, there is no error τ due to an increase in the response level by the value specified by the hysteresis loop devices to increase noise immunity. From a quantitative point of view, the effect obtained is easily seen on the example of a sinusoidal signal

with a period T, if we take the result as a value of τ equal to the difference between the true duration of the output pulse T / 2 and the duration T _X obtained by clipping the signal in a hysteresis circuit. We assume that the hysteresis characteristic shifts only the leading edge of the output pulse, i.e., U _ITP > 0, and U _ITN = 0. In this case, based on the fact that the pulse duration x2 (see Fig. 2) obtained at the U _ITP level is

, then the value of T _{X is} determined from the expression:

We assume that the changes in the pulse durations caused by the superposition of noise on the wanted signal in the form of normal random processes with zero mean have the same sign and are equal in magnitude. For illustrative purposes, this assumption is quite valid, since in practice it is often possible to neglect a small change in the slope of the input signal in the region from 0 to U _ITP .

Hence

.or

.

The resulting record establishes a relation between the error τ and the level U _ITP , the amplitude U and the period of the signal T. For clarity, the relation τ with U _{ITP is} shown graphically (Fig. 3) for different values of T. Here it is seen that with decreasing frequency of the clipped signal, the error τ increases, and the dependence of τ on U _ITP in the region from 0 to 0.5 U is almost linear.

Regarding the choice of the value of the switching voltage U _ITP, we note the following. The level U _ITP should not exceed the minimum level klippiruemogo signal v (t), but at the same time must be above the noise n (t), it is necessary, on the one hand, to determine the existence of the positive half of the useful signal, on the other hand - to prevent switching of the RS-flip-flop 5 in the absence of a clippable signal and / or its repeated switching during the device’s processing of the peak of the output pulse. In the absence of a useful signal, if there is only interference at the input, provided that the inverting input of the comparator 1 is connected to the zero potential bus, a constant high logic level will be present at the output of the device. When a useful signal appears that exceeds the level of interference, the clipping process will begin with the appearance of the first negative half-wave of the useful signal. If necessary, to eliminate the appearance of a high logic level at the output, a small threshold voltage lower than U _ITP can be applied to the inverting input of comparator 1, which will protect comparator 1 from false alarms at low input noise levels. However, this will slightly change the duration of the pulses at the output of the device.

Claims (3)

1. A device for clipping alternating signals, containing two comparators and a D-trigger, the output of which is the output of the device, and the input is the combined direct input of the first comparator and the inverting input of the second comparator, characterized in that a third comparator, two RS-flip-flops are inserted into it and the element And, the output of the first comparator is connected to the clock input of the D-trigger, the D-input of which is an input of a fixed level of a logical unit, the output of the second comparator is connected to zeroing inputs of the first and second RS-triggers Gerov, the installation input of the first RS-trigger is connected to the output of the third comparator, the direct input of which is connected to the input of the device, the installation input of the second RS-trigger is connected to the output of the And element, the first input of which is connected to the output of the first RS-trigger, and the second input to the inverse output of the first comparator, the output of the second RS-trigger is connected to the zeroing input of the D-trigger, the inverting input of the first comparator is the input of the first threshold voltage, the inverting input of the third comparator is the input of the second burned voltage, the direct input of the second comparator is the input of the third threshold voltage. 2. The device according to claim 1, characterized in that the first threshold voltage is chosen equal to zero, the second threshold voltage is selected positive, the third threshold voltage is negative, while their absolute values are less than the amplitude of the clipped signals. 3. The device according to claim 1, characterized in that the first and second threshold voltage are selected positive, the third threshold voltage is negative, while the second threshold voltage is greater than the first, and their absolute values are less than the amplitude of the clipped signals.

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