RU2595629C1 - Frequency synthesizer - Google Patents

Abstract

FIELD: radio engineering and communications.

SUBSTANCE: invention relates to radio engineering and can be used in synchronous systems of radio systems to form signals with low time discrete frequency tuning in wide range and minimized level side (parasitic) components in the spectrum of output oscillation. Frequency synthesizer contains calibration generator 1, frequency divider with fixed division factor 2, phase 3 and 4 synchronous detectors, 5 switch signal polarity, the first 6 and second 7 voltage comparators, pulse generator 8, line 9 timing delay, logical circuit "exclusive or" 10, dreversible counter 11, digital-to-analogue converter (DAC) 12, first adder 13, signal multiplier 14, integrator 15, tuned generator 16, frequency divider with variable division factor 17, phase changer 18 at π/2, unit 19 of installation and stabilization of loop amplification, scaling voltage divider 25, buffer register 26, unit to control synthesizer 27, and required connections between them.

EFFECT: invention is a complex (simultaneous) improvement of main parameters of frequency synthesizer, in particular, reducing of time of initial synchronization and discrete frequency adjustment during operation and minimizing the level of secondary (parasitic) components in the spectrum of output oscillation of frequency synthesizer.

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Description

The invention relates to radio engineering and can be used in synchronous systems of radio complexes for generating signals with a short time of discrete frequency tuning over a wide range and a minimized level of side (spurious) components in the spectrum of the output oscillation.

The traditional structure of the frequency synthesizer based on the phase locked loop (PLL), which implements the method of indirect frequency synthesis, is known. Such a circuit includes a reference generator, a frequency divider with a fixed division coefficient, a phase detector, a loop filter, a DC amplifier, a tunable generator and a frequency divider with a variable division coefficient, forming a phase locked loop of the frequency of the adjustable oscillator [1, p. 37]. This circuit, which is a prototype of the claimed device, has insufficient speed during initial synchronization and discrete frequency tuning over a wide range.

Improved performance during initial synchronization and discrete frequency tuning is inherent in the frequency synthesizer circuit, which uses a pulsed frequency-phase detector (ChFD) with three stable states and a block of charge / discharge current generators. The structure and description of the operation of such a synthesizer based on the Charge Pump Phase Locked Loop (CPPLL) phase-locked loop frequency-locked loop system is given in [2,3]. However, a significant drawback of the synthesizer structures based on the CPPLL basic scheme is the presence in the spectrum of the output oscillator synthesizer of a variety of secondary (spurious) discrete components. This is due to the fact that at the output of the pulse frequency-phase detector of the CPPLL system in a transient and synchronous operation modes a chaotic stream of short pulses continuously arises [4,5], which, coming to the frequency control input

tunable generator, create side (parasitic) components in the spectrum of the output oscillator synthesizer.

Thus, the previously known structures of frequency synthesizers do not allow achieving high speed discrete tuning in a wide frequency range, provided that there are no many side (spurious) components in the output oscillation spectrum.

The aim of the invention is a comprehensive (simultaneous) improvement of the main parameters of the frequency synthesizer, namely: reducing the initial synchronization time and discrete frequency tuning during operation and minimizing the level of side (spurious) components in the spectrum of the output oscillation of the frequency synthesizer.

The frequency synthesizer contains a reference generator 1, a frequency divider with a fixed division coefficient 2, a phase detector 3, a synchronous detector 4, a switch 5 of the signal polarity, first 6 and second 7 voltage comparators, pulse shaper 8, line 9 time delay, the logic circuit EXCLUSIVE OR "10, a reversible counter 11, a digital-to-analog converter (DAC) 12, a first adder 13, a signal multiplier 14, an integrator 15, an adjustable oscillator 16, a frequency divider with a variable division coefficient (DPC) 17, a phase shifter 1 8 on π / 2, the loop gain setting and stabilization unit (BUSPU) 19, the scaling voltage divider 25, the buffer register 26 and the control and control unit 27. The BUSPU (19) block contains the first and second blocks for raising the current voltage value to the second power of 20 and 21, a second adder 22, a block for raising the current voltage value to ½ degree 23, and a second voltage divider 24,

In the device under discussion, unlike CPPLL systems, there are no pulsed PFDs that create pulsed interference in the control frequency of the GHG voltage. This leads to minimization of the level of side (spurious) components in the spectrum of the output oscillator of the synthesizer.

The device operates in two modes: initial synchronization mode and discrete frequency tuning mode.

1. In the initial synchronization mode (when the device is turned on), at the outputs of the phase 3 and synchronous 4 detectors, quadrature beating components occur with a frequency corresponding to the initial frequency detuning Δω = ω _e / m-ω ₀ / n, where ω _e is the frequency of the output signal reference generator, m is the fixed division coefficient in the frequency divider 2, ω ₀ is the oscillation frequency of the output signal of the tunable generator 16, n is the variable division coefficient in the DPKD 17. Figure 2 shows voltage plots at the points of the device circuit for the case Δω> 0.

In FIG. 2a and 2b show the output signals of synchronous 4 and phase 3 detectors, respectively. The first 6 and second 7 voltage comparators from the output signals of the detectors form the logical signals shown in fig.2d and figv. The pulse shaper 8 generates short pulses at time points corresponding to the edges of the output pulse signal of the second comparator 7. Figure 2g shows these pulses transmitted through the time delay line 9. The output of the EXCLUSIVE OR logic 10 is shown in FIG. 2e. From the diagrams of FIG. 2d, e it follows that the code recorded in the reversible counter 11 and then relayed through the control and control unit 27 to the buffer register code 26 and, therefore, the output voltage of the DAC 12 increase. Diagrams of the output voltage of the DAC 12 are shown in Fig.2g.

Thus, when a signal appears at the input of the system, the output voltage of the DAC 12 increases stepwise, as a result of which the frequency of the tunable generator 16 changes in the direction of decreasing the current frequency mismatch Δω.

When the current frequency mismatch Δω is reduced to a value corresponding to the capture band of the analogue GHG frequency control branch (including blocks 3, 5, 14, 15 and 13), the synchronous mode of the frequency synthesizer is established.

In FIG. 2L and FIG. 2i show, respectively, the output signal of the signal multiplier 14 and the output signal of the switch 5 of the signal polarity, and FIG. 2h shows the output signal (U _p ) of the first adder 13, which controls the frequency of the SG 16.

Thus, the formation of counting pulses for a reversible counter based on oscillations of the differential frequency from the output of the detectors inside the digital branch of the frequency control of the GHG (including blocks 3, 4, 6, 7, 8, 9, 10, 11, 26, 12, and 13) leads to a significant reduction in the synchronization time of the frequency synthesizer. Moreover, the multiple expansion of the bands of capture and retention of the synchronous mode of operation of the device with respect to the prototype is limited only by the bit depth and speed of the element base of the digital circuit blocks.

When changing the polarity of the initial frequency mismatch, i.e. provided Δω <0, the counting direction of the reversible counter 11 and, accordingly, the polarity of the voltage changes at the output of the DAC 12 and the first adder 13 change. Otherwise, the process of initial synchronization of the synthesizer and the voltage diagram at the points of the circuit remains the same.

For the correct functioning and increase the accuracy and stability of the synchronization process in the device, local discriminatory characteristics of the digital and analog branches of the GHG frequency control are coordinated. A single discrete ΔU of the _DAC formed at the output of the step-by-step DAC must correspond to the full amplitude of the signal voltage at the output of the polarity switch, equal to 2A ₀ . For this purpose, the reference voltage U _{op of the} digital-to-analog converter is used to form single analog voltage steps from the output of the DAC (ΔU _DAC = U _op / 2 ^q , where q is the resolution of the DAC) and to calculate 25 normalized (required) values in the scaling voltage divider the amplitude of the phase mismatch signal from the output of the phase detector (A ₀ = U _op / 2 ^{q + l} ). Further, with the help of the installation and stabilization unit of loop gain 19, the really arising amplitude value

the phase mismatch signal from the output of the phase detector 3 is reduced to the normalized (required) value (A ₀ = U _op / 2 ^{q + l} ).

The installation and stabilization of the required loop gain coefficient of the analog control branch is carried out in the current time scale and proceeds as follows. The quadrature components of the beats with a frequency Δω from the outputs of the phase 3 and synchronous 4 detectors are fed to the inputs of the first and second blocks of raising the current voltage value to the second power of 20 and 21, respectively. On figa and fig.2b, the signals from the outputs of the synchronous and phase detectors are shown with changing amplitudes of the signals at the input of the device and from the output of the GHG or changing transfer coefficients of the detectors. The output signals of blocks 20 and 21 are fed to the inputs of the second adder 22, the voltage from the output of which is supplied to the input of the block for raising the current voltage value to ½ degree 23. The output voltage of block 23 is A _real (real - real), which corresponds to the amplitude of the beat voltage from the outputs of the detectors , is fed to the first input (input of the denominator of the fractional division) of the second voltage divider 24. The second input (input of the numerator of the fractional division) of the second voltage divider 24 receives a constant voltage A ₀ , the level of which corresponds to the nominal ( the required) value of the amplitude of the output signals of the detectors. The signal at the output of the second voltage divider 24, shown in FIG. 2k, corresponds to the instantaneous current deviation of the amplitude value of the output signals of the detectors from the nominal value A ₀ and represents a correction coefficient applied to the second input of the signal multiplier 14. The output signal of the signal multiplier 14, taking into account correction of the amplitude of the signal from the output of the phase detector 3 is shown in Fig.2L.

If we introduce the notation: U _K0C, U _SIN - the voltage at the output of the synchronous detector and phase respectively (CBS - cosine, sin - sine). And _real is the instantaneous current value of the amplitude of the output signal of the detectors, U _op is the reference voltage of the DAC, A ₀ is the nominal (required) value

the amplitudes of the signals from the outputs of the detectors, k _st is the correction coefficient of the loop gain coefficient (st is stabilization), e (t) is the amplitude of the voltage at the output of the polarity switch 5, e * (t) is the signal at the output of block 14, then the in BUSPU, the procedure for correcting the loop gain of a system can be described by the following relationships:

one. $$A_{Re\mathrm{but}l}={\left(U_{\mathrm{TO}\mathrm{ABOUT}\mathrm{FROM}}^2+U_{\mathrm{FROM}\mathrm{AND}N}^2\right)}^{\mathrm{one}/2}$$

2. $$A_0=U_{\mathrm{about}P}/2^{q+\mathrm{one}}$$

3. $$k_{\mathrm{from}t}=A_0/A_{Re\mathrm{but}l}$$

four. $$e^{*}(t)=e(t)\times k_{\mathrm{from}t}$$

Due to the above, a pairing of transmission coefficients of the analogue GHG frequency control branch (its local discriminatory characteristic is shown in Fig. 2l) and the digital control branch (its local discriminatory characteristic is shown in Fig. 2g) is implemented. This provides "stitching" and "linearization" (see diagram 2z) of the global discriminatory characteristics of the claimed device.

After the initial synchronization process is completed, the device enters synchronous operation mode.

, являющегося выходным колебанием синтезатора частот, дискретно изменяется кратно минимальному шагу перестройки равному ω_э/m. Дискретная перестройка частоты синтезатора осуществляется путем изменения кода частоты (значения константы n) подаваемого с первого выхода блока контроля и управления 27 на второй (управляющий) вход ДПКД 17. По выходному сигналу реверсивного счетчика в блоке контроля и управления 27 осуществляется контроль наличия синхронного режима работы устройства. Управление динамическими характеристиками переходных процессов в устройстве может осуществляться путем обработки и корректировки в блоке 27 кода, поступающего с выхода реверсивного счетчика 11 и далее подавае-мого на буферный регистр 26. В остальном процессы дискретной перестройки 2. In the discrete tuning mode, the frequency of the output oscillation of the GHG $${\omega }_0={\omega }_{\mathrm{uh}}\times \left(n/m\right)$$

, which is the output oscillation of the frequency synthesizer, discretely changes in multiples of the minimum tuning step equal to ω _e / m. Discrete tuning of the synthesizer frequency is carried out by changing the frequency code (constant value n) supplied from the first output of the control and control unit 27 to the second (control) input of the DPKD 17. The output of the reversible counter in the control and control unit 27 monitors the presence of a synchronous operation mode of the device . The dynamic characteristics of transients in the device can be controlled by processing and adjusting in block 27 the code coming from the output of the reverse counter 11 and then fed to the buffer register 26. Otherwise, the processes of discrete tuning

 synthesizer frequencies are similar to the initial synchronization processes described above.

1. Martirosov V.E. Optimal reception of discrete signals TsSPI. M .: Radio engineering, 2010 .-- 208 s, p. 37.

2. Gardner F.M. Charge-Pump Phase-Lock Loops. // IEEE Transactions on Communications. Vol. com-28, No. 11, November, 1980, p. 1849-1858.

3. Egan F.W. Frequency Synthesis by Phase Lock, 2nd Edition. John Wiley & Sons inc., 1999, 624 pp.

4. Donald R. Stephens. PHASE-LOCKED LOOPS FOR WIRELESS COMMUNICATIONS. Digital, Analog and Optical Implementations. Kluwer Academic Publishers, 2002, 422 pp.

5. Dmitriev S., Nikitin Yu. Single-frequency synthesizers with pulse-phase self-tuning of frequency ADF4000 series // Components and Technologies. No. 9, 2002.

Claims (2)

1. A frequency synthesizer comprising a reference oscillator connected in series, a frequency divider with a fixed division coefficient and a phase detector, as well as a tunable oscillator, the output of which is the output of the device, and a frequency divider connected to the first input with a variable division ratio, the output of which is connected to the second input of the phase detector, characterized in that a phase shifter of π / 2, the input of which is connected to the output, is introduced into the device in series For a frequency with a variable division coefficient, a synchronous detector, the second input of which is connected to the output of the frequency divider with a fixed division coefficient, a second voltage comparator, the second input of which is connected to a common bus, a pulse shaper, a time delay line and a reversible counter connected to the counting input, and a buffer register, a digital-to-analog converter, and a first adder are also introduced in series, the first input of which is connected to the output of the digital-to-analog converter, and the output connected to the control input of the tunable generator, and the first voltage comparator is connected in series, the first input of which is connected to the output of the phase detector, and the second input is connected to the common bus, the logic is EXCLUSIVE OR, the second input of which is connected to the output of the second voltage comparator, and the output is connected to the control of the counting polarity by the input of the reversible counter, and also the polarity switch of the signal polarity is introduced, the control input of which is connected to the w output voltage comparator, and the signal input is connected to the output of the phase detector, and a signal multiplier connected at the first input, the output of which is connected to the second input of the first adder, and an integrator is introduced, the input of which is connected to the output of the signal multiplier, and the output is connected to the third input of the first adder, and also introduced a scaling divider
voltage, the input of which is the reference voltage of the digital-to-analog converter, and the loop gain setting and stabilization unit (BUSPU), the output of which is connected to the second input of the signal multiplier, and the corresponding inputs are respectively connected to the output of the scaling voltage divider and to the outputs of the phase and synchronous detectors as well as a control and control unit, the input of which is connected to the output of the reversible counter and the first output of which is connected to the second input of the frequency divider with variable division factor, and the second output is connected to the input of the buffer register. 2. The frequency synthesizer according to claim 1, characterized in that the loop gain setting and stabilization unit (BUSPU) comprises series-connected the first block for raising the current voltage value to the second degree, the input of which is connected to the output of the phase detector, the second adder, the block for raising the current value voltage in ½ the degree and the second voltage divider connected at the first input, the output of which is the output of the BUSPU and the second input of which is connected to the output of the scaling voltage divider, and, in addition, contains a second block for raising the current voltage value to the second degree, the input of which is connected to the output of the synchronous detector, and the output is connected to the second input of the second adder.

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