RU2580799C1 - Logic transducer - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: logical transducer comprises six majority elements (1₁,…,1₆), which outputs the i-th

and sixth majority of elements are respectively connected to a second input (i+1)-th third input and a third majority element, and a first input and a third output of the majority element connected respectively to the second tuning input and output a logic inverter, the first, second, third and first adjustment information inputs connected respectively to the first, second, and third inputs of the first combining the first inputs of the second, fourth majority elements.

EFFECT: simplification of the logical transducer settings.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

.Logic converters are known (see, for example, RF patent 2393527, class G06F 7/57, 2010), which can be configured to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals

.

.The reason that impedes the achievement of the technical result indicated below when using known logic converters is a complicated setup, due to the fact that it requires a five-element training set

.

.The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2443009, class G06F 7/57, 2012), which contains major elements and can be configured to implement any of five simple symmetric Boolean functions depending on five arguments - input binary signals

.

.The reason that impedes the achievement of the technical result indicated below when using the prototype is a complicated setting due to the fact that it requires a five-element training set

.

The technical result of the invention is to simplify the configuration to implement any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, by reducing the power of the training set.

и шестого мажоритарных элементов соединены соответственно с вторым входом (i+1)-го и третьим входом третьего мажоритарных элементов, а первый вход и выход третьего мажоритарного элемента подключены соответственно к второму настроечному входу и выходу логического преобразователя, первый, второй, третий информационные и первый настроечный входы которого соединены соответственно с первым, вторым, третьим входами первого и объединенными первыми входами второго, четвертого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logic converter containing six majority elements, the second, third inputs of the sixth and third inputs of the second, fifth majority elements are connected respectively to the outputs of the fourth, fifth majority elements and the fourth information, third tuning inputs of the logical converter , the first, second, third information and first tuning inputs of which are connected respectively to the second, third inputs of the fourth the first, the second input of the fifth and the combined first inputs of the fifth, sixth majority elements feature is that the yields of i-th

and the sixth majority elements are connected respectively to the second input of the (i + 1) -th and third input of the third majority elements, and the first input and output of the third majority element are connected respectively to the second tuning input and output of the logic converter, the first, second, third information and first the tuning inputs of which are connected respectively to the first, second, third inputs of the first and the combined first inputs of the second, fourth majority elements.

The drawing shows a diagram of the proposed logical Converter.

, 1_j 

и 1₆ соединены соответственно с вторым входом элемента 1_i+1 (j-2)-ым входом элемента 1₆ и третьим входом элемента 1₃, а третьи входы элементов 1₂, 1₅, первый вход и выход элемента 1₃ подключены соответственно к четвертому информационному, третьему, второму настроечным входам и выходу логического преобразователя, первый, второй, третий информационные и первый настроечный входы которого соединены соответственно с объединенными первым входом элемента 1₁, вторым входом элемента 1₄, объединенными вторым входом элемента 1₁, третьим входом элемента 1₄, объединенными третьим входом элемента 1₁, вторым входом элемента 1₅ и объединенными первыми входами элементов 1₂, 1₄, 1₅, 1₆.Logic converter contains majority elements 1_one,…,one₆, and the outputs of the elements 1_i

, one_j

 and 1₆ connected respectively to the second input of element 1_{i + 1} by the j-2th input of element 1₆ and the third input of element 1₃, and the third inputs of the elements 1₂, one₅first entry and exit of element 1₃ connected respectively to the fourth information, third, second tuning inputs and output of the logical converter, the first, second, third information and first tuning inputs of which are connected respectively to the combined first input of element 1_one, the second input of element 1_fourcombined by the second input of element 1_one, the third input of element 1_fourcombined by the third input of element 1_one, the second input of element 1₅ and the combined first inputs of the elements 1₂, one_four, one₅, one₆.

и

. На выходе мажоритарного элемента 1_k

имеем

, где

,

,

и

есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И. Следовательно, сигнал на выходе предлагаемого логического преобразователя определяется выражениемThe work of the proposed logical Converter is as follows. On its first, ..., fourth informational and first, ..., third tuning inputs binary signals are given respectively

and

. At the output of the majority element 1 _k

we have

where

,

,

and

there are, respectively, signals at its first, second, third inputs and symbols of operations OR, I. Therefore, the signal at the output of the proposed logical converter is determined by the expression

Thus, at the output of the proposed logical Converter we get

есть элементы настроечного множества;

есть простые симметричные булевы функции пяти аргументов

(см. стр. 126 в книге Поспелов Д.А. Логические методы анализа и синтеза схем. М.: Энергия, 1974).where 0, 1, x ₅ ,

there are elements of the training set;

there are simple symmetric boolean functions of five arguments

(see page 126 in the book Pospelov D. A. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974).

The above information allows us to conclude that the proposed logic converter has a simpler configuration compared to the prototype to implement any of the five simple symmetric Boolean functions, depending on five arguments - input binary signals, since the tuning set uses a smaller set of power compared to the prototype .

Claims (1)

A logic converter designed to implement any of five simple symmetric Boolean functions, depending on five arguments - input binary signals, containing six majority elements, the second, third inputs of the sixth and third inputs of the second, fifth majority elements being connected respectively to the outputs of the fourth, fifth majority elements and the fourth informational, third tuning inputs of the logical converter, the first, second, third informational and first tuning inputs of which connected respectively to the second, third inputs of the fourth, second input of the fifth and the combined first inputs of the fifth, sixth majority elements, characterized in that the outputs of the i-th

and the sixth majority elements are connected respectively to the second input of the (i + 1) -th and third input of the third majority elements, and the first input and output of the third majority element are connected respectively to the second tuning input and output of the logic converter, the first, second, third information and first the tuning inputs of which are connected respectively to the first, second, third inputs of the first and the combined first inputs of the second, fourth majority elements.