RU2531530C1 - Adaptive integrating synchronisation device - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to the field of electric engineering and may be used in control systems for alternating- and direct-current thyristor converters as well as active front ends. The synchronisation device represents a closed integrating self-oscillating system with the scheme of frequency-amplitude correction. The adaptive integrating synchronisation device comprises the first summator (1), an integrator (2), the second summator (3), a relay element (4), three identical synchronising circuits (5)-(7), a logic element (8) of 3 OR function, period-to-voltage converter (9), the third summator (10), an amplitude modulator (11) and reference voltage source (12).

EFFECT: improving dynamic accuracy in the area of low synchronizing depth values less than the level of 2,0 due to change in the line voltage period T_C during time T_C/6 or 60 electrical degrees.

6 dwg

Description

The device relates to the field of converter technology and can be used in control systems for thyristor converters of direct and alternating voltage, as well as active rectifiers.

Known synchronization device (DC) of direct action (Information circuits of thyristor electric drives converters / S. S. Krylov, E. V. Melnikov, L. I. Konyshev. - M .: Energoatomizdat, 1984. - 160 p.), Containing a comparator on an operational amplifier with positive feedback circuit resistors connected to the mains voltage through an isolation step-down transformer and extracting, using the output signal, a logical “1” moment of time when the mains voltage passes through the zero level. The two-anode zener diode serves to protect the input of the microcircuit from overvoltages from the mains voltage.

A disadvantage of the known technical solution is its low noise immunity to impulse noise and switching distortion from the side of the synchronization voltage, as well as the error when changing the amplitude and frequency of the synchronization signal.

A synchronization device is known that contains an amplifier with positive feedback resistors, a synchronizing transformer with rectifier diodes and a matching transistor (a.s. , Tsytovich L.I. et al. (USSR). - No. 4778744/07, declared 05.01.90; publ. 02.28.93, Bull. No. 8).

The comparator is powered by two three-phase zero rectification circuits, forming an unstabilized voltage for the amplifier. In this case, the switching thresholds of the comparator change according to the law of the rectified mains voltage. Switching the DC is carried out by the voltage of the corresponding phase on the secondary side of the transformer. As a result, the duration of the output pulse of the comparator corresponds to a given range of variation of the angle of control of the thyristors even for the case of significant instability of the voltage of the network of phases A, B, C.

A disadvantage of the known CSS is its low noise immunity to impulse noise from the side of the synchronization voltage, as well as the fact that the high accuracy of maintaining a given regulation range by thyristors occurs only when the amplitudes of all phases of the network voltage are synchronous and identical in level to the amplitude.

A synchronization device of an integrating type is known, comprising a synchronization signal source connected sequentially from the side of the transformer of the pulse-phase control system, an adder, an integrator, a relay element, the output of which is connected to the second input of the adder and at the same time is the "output" of the device. The mains voltage is directly used as the source of the synchronization signal (MM Dudkin, LI Tsytovich. Elements of information electronics for valve converters control systems: monograph. - Chelyabinsk: SUSU Publishing Center, 2011. - P.37).

The device has high noise immunity to impulse noise from the side of the synchronization voltage, as well as the ability to adapt to changes in the voltage amplitude of the network (synchronizing effect), which is explained by the closed nature of the structure of the DC and the presence of an integrator in the direct control channel.

The disadvantage of this device is its partial, but not complete, adaptation to a change in the frequency of the mains voltage, depending on the depth of the synchronizing effect.

Closest to the proposed technical solution is an adaptive synchronizing device of an integrating type (Dudkin M.M. Energy-saving technologies in test benches using single-phase reversible converters // Vestnik SUSU. Series "Energy". - 2013. - Issue 13. - No. 1. - C.9).

The structure of the DC includes a serially connected source of a synchronization signal — the “input” of a synchronization device, a first adder, an integrator, a second adder, a relay element, a short pulse generator, a period to voltage converter, a third adder, and an amplitude modulator. The output of the relay element is the "output" of the synchronization device and is simultaneously connected to the second input of the first adder and the second input of the amplitude modulator, the output of which is connected to the second input of the second adder. The second input of the third adder is connected to a voltage reference source.

- период собственных автоколебаний УС при отсутствии сигнала синхронизации; $$\overline{b}=|b/A|$$

- нормированное значение порогов переключения РЭ; T_И - постоянная времени интегрирования интегратора.Under the influence of a harmonic synchronizing signal (mains voltage), forced oscillations are established at the output of the DC, at which the pulses at the output of the relay element are shifted relative to the mains voltage by the synchronization angle α _C = -90 el. hail subject to the equality T _C = T ₀ , where T _C is the period of the mains voltage; $${\mathrm{<figure-callout\; id="0"\; label="T"\; filenames="00000027.png,00000028.png"\; state="\{\{state\}\}">T</figure-callout>}}_0=\mathrm{four}\overline{b}{T}_{\mathrm{AND}}$$

- period of self-oscillations of the CSS in the absence of a synchronization signal; $$\overline{b}=|\; |\; |b/A|\; |\; |$$

- the normalized value of the thresholds of switching RE; T _And is the integrator integration time constant.

The prototype device has high noise immunity to impulse noise from the side of the synchronization voltage, as well as the ability to adapt to changes in the amplitude and frequency of the mains voltage (synchronizing effect), which is explained by the closed nature of the structure of the DC, the presence of an integrator in the direct control channel and a frequency correction unit, consisting of a short pulse generator, a period to voltage converter, an adder, an amplitude modulator and a reference voltage source.

, где A_С, A - амплитуды синхронизирующего воздействия и импульсов на выходе релейного элемента соответственно. Так, например, при глубине синхронизации, лежащей в диапазоне $$\mathrm{2,0}\le {\overline{A}}_C\le \mathrm{8,0}$$

, допустимая скорость изменения частоты напряжения сети за 1 сек составляет ±12 Гц/с, при $${\overline{A}}_C=\mathrm{1,0}-\pm 7\text{ Гц/с}$$

, а при $${\overline{A}}_C=\mathrm{0,5}$$

- всего лишь ±4 Гц/с при условии, что абсолютная ошибка угла синхронизации Δα_С=(α_С - 90 эл. град) не превышает ±2 эл. град. Кроме этого, работа УС в области $${\overline{A}}_C>\mathrm{2,0}$$

неизбежно приводит к снижению динамической точности при резких отклонениях амплитуды напряжения сети, т.к. интегрирующее УС по отношению к информационному гармоническому сигналу представляет собой апериодическое звено первого порядка с передаточной функциейThe disadvantage of the prototype device is its low dynamic characteristics in the field of small values of the depth of the synchronization signal $${\overline{A}}_C=|\; |\; |A_C/A|\; |\; |$$

where A _C , A are the amplitudes of the synchronizing effect and pulses at the output of the relay element, respectively. So, for example, with a depth of synchronization lying in the range $$2.0\le {\overline{A}}_C\le 8.0$$

, the permissible rate of change of the mains voltage frequency for 1 sec is ± 12 Hz / s, at $${\overline{A}}_C=\mathrm{1,0}-\pm 7\text{Hz / s}$$

, and when $${\overline{A}}_C=0.5$$

- only ± 4 Hz / s, provided that the absolute error of the synchronization angle Δα _С = (α _С - 90 el. grad) does not exceed ± 2 el. hail. In addition, the work of the CSS in the field $${\overline{A}}_C>2.0$$

inevitably leads to a decrease in dynamic accuracy with sharp deviations of the network voltage amplitude, because the integrating DC with respect to the harmonic information signal is a first-order aperiodic link with a transfer function

, $$W\left(p\right)=\frac{\mathrm{one}}{\mathrm{one}+T_{E}p}$$

,

- эквивалентная постоянная времени УС, зависящая от периода T_C и глубины сигнала синхронизации $${\overline{A}}_C$$

.Where $$T_E\approx \pi \cdot {\overline{A}}_C\cdot T_C/16$$

is the equivalent time constant of the DC, depending on the period T _C and the depth of the synchronization signal $${\overline{A}}_C$$

.

Thus, the prototype device is characterized by low dynamic accuracy in the field of small values of the depth of synchronization with instability of the frequency of the mains voltage, which is especially important for thyristor converters powered by limited power systems, such as diesel generator sets.

The basis of the invention is a technical problem, which consists in increasing the dynamic accuracy of the synchronization device in the field of small values of the depth of synchronization, less than 2.0, with deviations of the frequency of the mains voltage.

The specified technical problem is solved due to the fact that in an adaptive integrating synchronization device containing a reference voltage source, a first adder, an integrator, a second adder and a relay element are connected in series, as well as a period to voltage converter, a third adder and an amplitude modulator connected in series, the output being the relay element is the "output" of the device and is simultaneously connected to the first input of the first adder and the second input of the amplitude modulator, the output of which is connected to the second input of the second adder, the reference voltage source is connected to the second input of the third adder, and the second input of the first adder is connected to the network voltage phase A bus according to the invention, three identical synchronization circuits and one “3 OR” logic element are introduced, and the inputs of the first, the second and third synchronization circuits are connected to the phase voltage buses A, B, C, respectively, and the outputs of the synchronization circuits are connected to the first, second and third inputs of the 3 OR logic element, the output of which is connected to the input period-to-voltage converter.

The stated technical problem is achieved due to the fact that three identical synchronization circuits and one logical element “3 OR” are introduced into the device.

The main task of synchronization circuits is the formation of short pulses that coincide with the time when the voltage of the network of phases A, B, C passes through zero values, followed by their summation using the "3 OR" logic element. As a result of this, pulses are formed at the output of the “3 OR” element, following each other through 60 e. hail or T _C / 6, which allows three times to accelerate the process of converting the network period T _C to voltage, compared with the prototype device, in which this time interval is 180 el. hail or T _C / 2.

, который, как видно, зависит от нормированного порога переключения релейного элемента $$\overline{b}=|b/A|$$

и постоянной времени интегрирования интегратора, являющейся постоянной величиной. Здесь A - амплитуда импульсов на выходе релейного элемента. В результате этого угол синхронизации α_C между выходными импульсами релейного элемента и сигналом синхронизации (напряжения сети) в установившемся режиме работы при изменении частоты напряжения сети сохраняется постоянным и равен -90 эл. град, что однозначно свидетельствует об адаптации устройства синхронизации к частоте напряжения сети.The amplitude modulator corrects the switching thresholds of the relay element in such a way that when the frequency of the mains voltage changes, the equality between the mains voltage period T _C and the period of the device’s self-oscillations is always true $$T_{}$$$${}_0=\mathrm{four}\overline{b}{T}_{\mathrm{AND}}$$

, which, as can be seen, depends on the normalized switching threshold of the relay element $$\overline{b}=|\; |\; |b/A|\; |\; |$$

and the integrator integration time constant, which is a constant. Here A is the amplitude of the pulses at the output of the relay element. As a result of this, the synchronization angle α _C between the output pulses of the relay element and the synchronization signal (mains voltage) in the steady-state mode when the frequency of the mains voltage changes, remains constant and equal to -90 el. hail, which clearly indicates the adaptation of the synchronization device to the frequency of the mains voltage.

, меньших 2,0, т.к. с ростом $${\overline{A}}_C$$

наблюдается увеличение эквивалентной постоянной времени фильтра $$T_{Э}\approx \pi \cdot {\overline{A}}_C\cdot T_C/16$$

и, как следствие, повышение инерционности устройства синхронизации.Improving the dynamic accuracy of the device can only be achieved in the field of small values of the depth of synchronization $${\overline{A}}_C$$

less than 2.0, because with growth $${\overline{A}}_C$$

an increase in the equivalent filter time constant is observed $$T_E\approx \pi \cdot {\overline{A}}_C\cdot T_C/16$$

and, as a result, increasing the inertia of the synchronization device.

Thus, the proposed adaptive integrating synchronization device has increased dynamic accuracy in the field of small values of the depth of synchronization, less than the level of 2.0, due to the measurement of the network voltage period T _C during the time T _C / 6 or 60 el. hail, which is ensured by the introduction of three identical synchronization circuits and one logical element "3 OR".

The invention is illustrated by drawings:

Figure 1 - functional diagram of the proposed device;

Figa, b, c, d - characteristics of the elements of the proposed device;

Figa, b, c, d, d, e are signal diagrams of an adaptive integrating synchronization device;

Figure 4 is an example of a technical implementation of the period to voltage converter;

Figa, b, c, d, d are timing diagrams of the signals of the period to voltage converter.

Figa, b - graphs of the dependencies of the absolute error of the angle of synchronization when changing the frequency of the mains voltage and various values of the depth of synchronization for the proposed device and the prototype device, respectively.

The structure of the control unit includes (Fig. 1) a series-connected first adder 1, an integrator 2, a second adder 3 and a relay element 4. Blocks 1-4 form a deployment converter (RP). The DC also includes a frequency correction unit (BCCH), consisting of three identical synchronization circuits 5-7, series-connected logic element 8 of the “3 OR” function, a period-to-voltage converter 9, a third adder 10 and an amplitude modulator 11, as well as a source reference voltage 12. The output of the relay element 4 is the "output" of the synchronization device and is simultaneously connected to the first input of the first adder 1 and the second input of the amplitude modulator 11, the output of which is connected to the second input of the second adder 3. W "3 OR" function s phases A, B, C voltage are respectively connected to the input of the first 5, second 6 and third 7 clock circuit, the outputs of which are respectively connected to the first, second and third inputs of NAND gate 8. The phase A bus of the mains voltage is connected to the second input of the first adder 1, and the second input of the third adder 10 is connected to a reference voltage source 12.

Each of the synchronization circuits 5-7 (Fig. 1) contains serially connected aperiodic filters 13, 16, 19, comparators 14, 17, 20 and short pulse generators 15, 18, 21.

The period-to-voltage converter (ППН) 9 (Fig. 1) consists of series-connected elements - a high-frequency pulse generator 22, a binary totalizing counter 23, a memory register 24 and a digital-to-analog converter 25 (Fig. 4), which is the output of the ППН. The PPN also includes a delay element 26, the output of which is connected to the R-input of the binary counter 23. The input of the PPN is simultaneously connected to the C-input of the memory register 24 and the input of the delay element 26.

Figure 1-6 introduced the following notation:

X _C - synchronization signal US (bus phase A of the mains voltage);

A, B, C - bus phase voltage network;

A _C , T _C - amplitude and period of the synchronization signal, respectively;

α _C is the angle of synchronization at the output of the device;

Y _And - the output signal of the integrator 2;

Y is the output signal of the relay element 4;

± A, T ₀ - the amplitude and period of the output pulses of the relay element 4, respectively;

± b - switching thresholds of the relay element 4;

Y _G1 , Y _G2 , Y _G3 - output signals of synchronization circuits 5-7, respectively;

Y _Ф1 , Y _Ф2 , Y _Ф3 - signals at the output of aperiodic filters 13, 16, 19, respectively;

Y _K1 , Y _K2 , Y _K3 - signals at the output of the comparators 14, 17, 20, respectively;

Y _Г∑ - output signal of the logic element 8 of the function "3 OR";

Y _T is the output signal of the period to voltage converter 9;

Δb is the deviation of the switching threshold of the relay element 4 when the frequency of the synchronizing effect;

Y _A is the output signal of the amplitude modulator 11;

X ₀ - source of reference voltage 12;

Y _G is the output signal of the high-frequency pulse generator 22;

N is a binary digital code at the output of the counter 23;

Y _DL is the output signal of the delay element 26;

τ is the delay time of the element 26.

Links CSS have the following characteristics (figure 2).

The adder 1 sums the synchronizing effect X _C (t) and the signal Y (t) from the output of the relay element 4 and has a single transmission coefficient for each of the inputs.

Integrator 2 has a transfer function W (p) = 1 / T _AND p, where T _AND is the integration time constant. With a discrete change in the input action, the output signal of the integrator 2 changes linearly with the sign opposite to the sign of the signal at its input (Fig. 2a).

The adders 3 and 10 subtract the signal Y _A (t) of the amplitude modulator 11 from the output signal Y _And (t) of the integrator 2 and the output voltage Y _T (t) of the ППН 9 from the source 12 of the reference voltage X _0, respectively, and have unit transmission coefficients for each from the entrances.

(фиг.2б).Relay element 4 has a zero-symmetrical and non-inverting hysteresis loop with switching thresholds $$|\; |\; |b|\; |\; |<<|\; |\; |A|\; |\; |$$

(figb).

Synchronization circuits 5-7 form pulses of short duration at the output synchronously with a change in the sign of the network voltage of the corresponding phase.

Logic element 8 of the “3 OR” function switches to the logical “1” state, when at least one of its inputs contains a logical “1” signal.

PPN 9 converts the period of the pulses at the output of the logic element 8 into an analog signal Y _T (t), the level of which increases linearly with the growth of the period of input exposure (pigv).

The amplitude modulator 11 generates an alternating pulse signal Y _A (t) at the output, the amplitude of which corresponds to the voltage level at the output of the adder 10, and the frequency is determined by the frequency of the output pulses of the relay element 4 (Fig.2g).

Filters 13, 16, 19 have a transfer function W (p) = 1 / (T _F p + 1),

where T _f - time constant of the first-order aperiodic filter.

Comparators 14, 17, 20 have a non-inverting input-output characteristic and switch when the sign of the voltage at the output of the filters 13, 16, 19 changes.

Generators of short pulses 15, 18, 21 form short pulses with constant amplitude along the leading and trailing edges of the pulses from the output of the comparators 14, 17, 20.

The pulse generator 22 generates high-frequency pulses with a stable frequency for counting them by the totalizing counter 23.

The binary counter 23 is a summing counter and increases its contents by a unit of the least significant digit synchronously with the leading edge of the pulse at the C input. When the leading edge of the pulse acts on the R-input, the counter 23 goes into the “zero” state in all digits.

The memory register 24 records data from its D-inputs synchronously with the leading edge of the pulse at the C-input.

The digital-to-analog converter 25 converts the digital code N (t) from the output of the memory register 24 into an analog signal Y _T (t).

The delay element 26 shifts in time the clock pulse from the output of the logic element 8 by the value of "τ", leaving its amplitude and duration unchanged.

The principle of operation of the device is as follows.

релейного элемента 4In the absence of a signal at the synchronization input X _C (t), the adders 1, 3, the integrator 2 and the relay element (RE) 4 (Fig. 1) together form a self-oscillating system with frequency-pulse-width modulation. The amplitude of the output signal of the integrator 2 is limited by the switching thresholds ± b of the relay element 4 and has the form of a “saw” symmetrical with respect to the zero level. The frequency of self-oscillations of a system composed of blocks 1-4 is determined by the time constant T _{AND of the} integrator 2, as well as the normalized value of the switching thresholds $$\overline{b}=|\; |\; |b/A|\; |\; |$$

relay element 4

. $${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000027.png,00000028.png"\; state="\{\{state\}\}">f</figure-callout>}}_0={(T_0)}^{-\mathrm{one}}=\mathrm{one}/(\mathrm{four}\overline{b}{T}_{\mathrm{AND}})$$

.

We consider that the natural frequency of self-oscillations f _{0 of the} system is equal to the frequency f _{C of} the synchronization signal (frequency of phase A, B, C of the mains voltage) and corresponds to 50 Hz.

Consider the operation of the device in external synchronization mode with the frequency of the phase A network voltage.

When exposed to a harmonic synchronizing signal X _C (t) of phase A of the network voltage with a frequency f ₀ = 50 Hz (Fig. 3a), forced oscillations with a frequency (T ₀ ) ^-1 equal to the frequency f _C = (T _C ) ^-1 synchronizing effect (fig.3b), and the pulses Y (t) are shifted relative to phase A of the mains voltage by an angle α _C = -90 el. hail (figa, b). The output signal Y _AND (t) of the integrator 2 is close in shape to the harmonic signal (figb). Switching of the relay element 4 is carried out when the scan of the integrator Y _AND (t) reaches the switching thresholds ± b RE.

Synchronization Schemes 5-7 (Figure 1) are formed short in Y pulses _{T1, T2} Y, Y _T3 (Figure 3D, Y pulses _{T2, T3} Y not shown) coinciding with the timing of transition voltages of phases A, B, C through zero values (figa), provided there are no filters 13, 16, 19 at the input of the synchronization circuits 5-7, followed by the summation of pulses Y _G1 , Y _G2 , Y _G3 using logic element 8 of the function "3 OR" (fig.3d). The introduction of filters 13, 16, 19 (Fig. 1) increases the noise immunity of synchronization circuits 5-7 to external noise and inevitably leads to a phase shift of the voltages of phases A, B, C (Fig. 3a, signal Y _F1 ), as well as pulses Y _K1 , Y _K2 , Y _K3 and Y _G1 , Y _G2 , Y _G3 at the output of the comparators 14, 17, 20 and the generator of short pulses 15, 18, 21 at an angle φ _Ф (figv-d, pulses Y _K2 , Y _K3 and Y _G2 , Y _G3 not shown). The phase shift φ _Ф introduced by the filters 13, 16, 19, at a frequency of the network voltage of phases A, B, C f _С = 50 Hz, it is recommended to choose in the range of 20-40 el. hail.

Thus, at the output of logic element 8 of the “3 OR” function, pulses Y _{Г∑ are formed} , following each other after 60 e. hail or T _C / 6 (fig.3d), which allows three times to speed up the process of converting the period T _C to voltage Y _T (t) in PPN 9, compared with the prototype device in which this time interval is 180 el. hail or T _C / 2.

When the voltage frequency of the network of phases A, B, C f _C = 50 Hz, the signal Y _T (t) at the output of the PLC 9 is equal in modulus to the switching threshold b of the relay element of the RE (Fig.3d). Given the choice of the source 12 of the reference voltage X ₀ equal to the value of the switching threshold + b of the relay element 4, the signal Y _A (t) at the output of AM 11 is zero (Fig. 3e).

релейного элемента 4 на величину $$\left|\Delta b\right|$$

(фиг.3б) при сохранении равенства $$T_C=T_0=4\overline{b}{T}_{И}$$

. В результате, в установившемся режиме работы угол синхронизации α_C между напряжением сети фазы A и выходными импульсами Y(t) релейного элемента 4 сохраняется равным -90 эл. град (фиг.3а, б).With a decrease in the voltage frequency of the network of phases A, B, C (Fig. 3a), the signal Y _T (t) at the output of the arrester increases to the level b + Δb (Fig. 3d), and a negative deviation Δb is formed at the output of the adder 10. The amplitude modulator 11 generates an alternating pulse signal Y _A (t) with an amplitude Δb and a period equal to the period T _{0 of the} output pulses of the relay element 4 (Fig. 3b, e). The sign of the output pulses AM 11 is determined as the result of multiplying the signals from the output of RE 4 and the adder 10. As a result of this, the switching threshold changes $$|\; |\; |b|\; |\; |$$

relay element 4 by $$|\; |\; |\Delta b|\; |\; |$$

(figb) while maintaining equality $$T_C={\mathrm{<figure-callout\; id="0"\; label="T"\; filenames="00000027.png,00000028.png"\; state="\{\{state\}\}">T</figure-callout>}}_0=\mathrm{four}\overline{b}{T}_{\mathrm{AND}}$$

. As a result, in the steady state mode of operation, the synchronization angle α _C between the phase A network voltage and the output pulses Y (t) of the relay element 4 is kept equal to -90 e. hail (figa, b).

PPN 9 (figure 4) converts the period of the pulses Y _Г∑ (t) coming from the output of the logic element 8 ( _figure 1), into an analog signal Y _T (t) (figa, d). With the time delay "τ" generated by block 26 (Fig. 4), the binary totalizing counter 23 is "reset" (Fig. 5c) by a short pulse Y _DL (t) (Fig. 5g), and the counting process begins in the counter 23 of pulses Y _G (t) (Fig.5b) from the output of the high-frequency generator 22 (Fig.4). As a result, by the time of the formation of the next short pulse Y _Г∑ (t) (Fig.5a), the number N (t) accumulates at the output of the counter 23 (Fig.5c), which is directly proportional to the time interval T _C / 6 (Fig.5a), which it is copied from the output of the counter 23 to the memory register 24. The digital-to-analog converter 25 converts the binary number from the output of the memory register 24 to the analog signal Y _T (t) (Fig. 5d). With a time delay of "τ" (Fig.5g), the binary counter 23 is "zeroed" (Fig.5c), the processes in the circuit are repeated.

для предлагаемого устройства и устройства-прототипа соответственно. Здесь Δα_C=(α_C-90 эл. град) - абсолютная ошибка угла синхронизации при изменении частоты напряжения сети f_C; S_f - абсолютная скорость изменения частоты напряжения сети за заранее заданный интервал времени, равный 1 сек.On figa, b shows the dependency graphs Δα _C = f (S _f ), obtained on the basis of mathematical modeling in the program MatLab + Simulink, for different values of the depth of synchronization $${\overline{A}}_C$$

for the proposed device and the prototype device, respectively. Here Δα _C = (α _C -90 el. Hail) is the absolute error of the synchronization angle when changing the frequency of the mains voltage f _C ; S _f - the absolute rate of change of the frequency of the mains voltage for a predetermined time interval equal to 1 second.

, допустимая скорость изменения частоты напряжения сети за 1 сек S_f составляет ±12 Гц/с при условии, что абсолютная ошибка угла синхронизации Δα_C не превышает ±2 эл. град. При $${\overline{A}}_C<\mathrm{2,0}$$

быстродействие предлагаемого устройства увеличивается (фиг.6а), а устройства-прототипа наоборот снижается (фиг.6б). Так, например, при $${\overline{A}}_C=\mathrm{0,5}$$

для предлагаемого устройства S_f=±21 Гц/с, а для устройства прототипа составляет всего лишь ±4 Гц/с.From the graphs (Fig.6) it is seen that for the proposed device and the prototype device with a synchronization depth lying in the range $$2.0\le {\overline{A}}_C\le 8.0$$

, the permissible rate of change of the mains voltage frequency for 1 s S _f is ± 12 Hz / s, provided that the absolute error of the synchronization angle Δα _C does not exceed ± 2 e. hail. At $${\overline{A}}_C<2.0$$

the performance of the proposed device is increased (figa), and the prototype device, on the contrary, is reduced (fig.6b). So, for example, when $${\overline{A}}_C=0.5$$

for the proposed device S _f = ± 21 Hz / s, and for the device of the prototype is only ± 4 Hz / s

Thus, due to the introduction of three identical synchronization circuits and one “3 OR” logic element, the proposed synchronization device with deviations of the mains voltage frequency has increased dynamic accuracy in the region of small synchronization depths less than 2.0.

Industrial applicability

The proposed device is intended to be used in the control system of a DC valve converter of an automated electric edge-cutting machine drive at Chelyabinsk Tube-Rolling Plant OJSC.

Claims (1)

An adaptive integrating synchronization device containing a reference voltage source, a first adder, an integrator, a second adder and a relay element connected in series, as well as a period to voltage converter, a third adder and an amplitude modulator connected in series, the output of the relay element being the “output” of the device and simultaneously connected with the first input of the first adder and the second input of the amplitude modulator, the output of which is connected to the second input of the second adder, the source of the supports voltage is connected to the second input of the third adder, and the second input of the first adder is connected to the phase A bus of the mains voltage, characterized in that three identical synchronization circuits and one “3 OR” logic element are introduced into it, the inputs of the first, second and third circuits synchronization are connected to the buses of phases A, B, C of the network voltage, respectively, and the outputs of the synchronization circuits are connected to the first, second and third inputs of the logic element "3 OR", the output of which is connected to the input of the period to voltage converter.

Images