RU2503996C1 - Apparatus for dynamic prediction of microprocessor conditional jump commands - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus consists of a global jump history shift register, a program counter register, a processor operating mode register, an XOR logic element, global prediction memory, two-bit prediction memory, a final prediction selection multiplexer, a process address space identifier register, process jump history memory, an XOR logic element, process local prediction memory, a process prediction control memory address register, process prediction control memory and an intermediate process prediction selection multiplexer.

EFFECT: high efficiency of the microprocessor due to high accuracy of predicting the direction of conditional jumps.

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Description

The invention relates to the field of computer technology and can be used in high-performance microprocessor systems.

A device for predicting conditional branch instructions is included in the instruction buffer of a hybrid microprocessor, including a central processor, system controller, external memory, two-level cache memory (Patent RU No. 2359315, class G06F 9/30, published on June 20, 2009) .

The disadvantage of this block is the lack of system performance due to the low accuracy of the static prediction of conditional branch instructions.

A block of dynamic prediction of instructions for conditional transition of a microprocessor is also known, including a shift register of global transition history, a program counter register, an exclusive OR logic element, a prediction memory, and a prediction selection device (Application for invention US No.20100169626, class G06F 9/38, publ. 07/01/2010).

A disadvantage of the device described above is the lack of prediction accuracy that forms the prediction selection device.

The closest in technical essence and the achieved technical result is a device for dynamic prediction of conditional transition instructions of a microprocessor, consisting of a shift register of the global transition history, a register of the program counter, a register of the processor operating mode, an exclusive OR logic element, a global prediction memory, a two-bit prediction memory, and multiplexer selection of the final prediction. (Application for invention US 20080215866, CL G06F 9/38, publ. 04.09.2008).

The disadvantage of the block described above is the lack of accuracy in predicting conditional branch instructions during parallel execution of application programs (when they switch without changing the processor operating mode).

The technical result from the use of this invention is to increase the performance of the microprocessor by increasing the accuracy of predicting the direction of conditional transitions.

The specified technical result is achieved by the fact that in the device for the dynamic prediction of conditional branch instructions, consisting of a shift register of global transition history, a program counter register, a processor operating mode register, an exclusive OR logic element, global prediction memory, two-bit prediction memory, and a final multiplexer predictions, according to the invention further comprises a register of the identifier of the address space of the process, a memory of the history of transitions pr a process, an exclusive OR logic element, a local process prediction memory, an address register of a process prediction control memory, a process prediction control memory and an intermediate process prediction selection multiplexer, wherein the intermediate process prediction selection multiplexer is associated with a two-bit prediction memory controlling the process prediction memory, a process prediction associated with the address register of the control memory that combines the values of the address identifier register process space and the program counter register, and the memory local prediction process which is associated with memory stories process transitions associated with register process address space identifier, and the program counter register gate "XOR".

Using the mechanism of choosing intermediate prediction allows one to accumulate a history of prediction efficiency of different prediction schemes and to use for each specific conditional transition command the prediction scheme that gives the greatest prediction accuracy for a given processed command.

The invention is illustrated in figure 1, which shows a block diagram of a dynamic prediction of conditional branch instructions.

The block of dynamic prediction consists of a register of the identifier of the address space of the process (IAPP) 1, software counter (PS) 2, the shift register of the global history of transitions (RGIP) 3, logical elements "exclusive OR" (XOR) 4 and 5, the memory of the history of transitions of the process ( PIPP) 6, global prediction memory (PP1) 7, two-bit prediction memory (PP2) 8 and local process prediction memory (PP3) 9. There are also two prediction selection devices - the first (to select the intermediate prediction) 10 and the second (to select the final prediction Azania) 11. The first intermediate prediction selection device 10 includes the address register of the process prediction control memory 12, the process prediction control memory (PP4) 13 and the process intermediate prediction selection multiplexer 14. The second final prediction selection device 11 contains a status register of the mode processor operation (PP) 15 and the multiplexer of the selection of the final prediction 16.

The prediction mechanism using the data of the process address space identification register (IAPP) 1 operates as follows.

When decoding a conditional branch instruction to the address contained in the program counter (PS) register 2, the data of the process address space identification register (IAPP) 1 is used as an address for the memory of the process transition history (PIPP) 6, and at the same time, part of its bits are combined with part of the bits of the register of the program counter (PS) 2, writing the received set of bits in the address register of the control memory of the prediction of the process 12. The data of the register address of the control memory of the prediction of the process 12 addresses the control memory before Legends of the process (PP4) 13.

The data obtained from the memory of the history of process transitions (PIPP) 6 are combined with the data of the register of the program counter (PS) 2 by the exclusive OR logic element 5, forming an address for the memory of the local process prediction (PP3) 9.

Software counter (PS) 2 is used as:

1. the address for the memory of two-bit prediction (PP2) 8,

2. the input of the element "exclusive OR" 4, which combines it with the value of the shift register of the global transition history (RGIP) 3, to obtain the memory address of the global prediction (PP1) 7,

3. the input of the element “exclusive OR” 5, which combines it with data read from the memory of the history of transitions of the process (PIPP) 6, to obtain the memory address of the local prediction of the process (PP3) 9.

The prediction of the branch instructions for the current process is formed from the data outputs of the two-bit prediction memory (ПП2) 8 and the local process prediction memory (ПП3) 9, which are selected by the intermediate prediction selector by process 14 using the data output value of the process prediction control memory (ПП4) 13 to control The output of the intermediate prediction selection multiplexer 14 is supplied to the final prediction selection device 11, where the final prediction selection multiplexer 16 selects or the output of the global prediction memory (PP1) 7 or the output of the intermediate prediction device 10, using the data of the processor mode (PP) status register 15. The two-bit code received at the output of the final prediction selection device 11 is used in the processor in the standard way to determine the direction of instructions branching. The described block of dynamic prediction allows to increase the accuracy of prediction of the direction of transition of the conditional transition commands in comparison with the known blocks of dynamic prediction and, as a result, to increase the performance of the microprocessor system as a whole.

Claims (1)

A device for dynamically predicting microprocessor conditional transition instructions, consisting of a shift register of global transition history, a program counter register, a processor operating mode register, an exclusive OR logic element, global prediction memory, two-bit prediction memory, and a final prediction selection multiplexer, characterized in that the device additionally contains a register of the identifier of the address space of the process, a memory of the history of transitions of the process, a logical element exclusive OR ”, a local process prediction memory, a process prediction control memory address register, a process prediction control memory and an intermediate process prediction selection multiplexer, wherein the intermediate process prediction selection multiplexer is associated with a two-bit prediction memory controlling the process prediction memory associated with the control address register process prediction memory, which combines the values of the register identifier of the process address space identifier and p Giustra program counter, memory and local prediction process which is associated with memory stories process transitions associated with register process address space identifier, and the program counter register gate "XOR".