RU2491728C1 - Method and apparatus for channel encoding and decoding in communication system using low-density parity-check codes - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: method for channel decoding in a communication system using a low-density parity check code (LDPC) includes steps of demodulating a received signal determining the position of cut information bits and decoding the demodulated signal based on the determined position of cut information bits, wherein determination of the position of cut information bits includes steps of dividing the information bits into a plurality of bit groups, determining the number of cut information bits, determining the number of cut bit groups based on the determined number of information bits that should be cut, and determining the cut bit groups based on a given order.

EFFECT: efficient support of different lengths of code words from an existing parity check matrix without the need to construct a new parity check matrix.

12 cl, 11 dwg

Description

FIELD OF THE INVENTION

The present invention generally relates to a communication system that uses low density parity check codes (LDPC), and in particular, to a channel coding / decoding method and apparatus that are designed to generate LDPC codes having different codeword length and various code rate values from a given LDPC code.

State of the art

In wireless communication systems, the channel’s performance is significantly reduced due to the presence of various noise in the channels, attenuation phenomena and mutual interference between symbols (ICI, PMS). Therefore, to implement high-speed digital communication systems that require high bandwidth and reliable data transfer, for example, in next-generation mobile communications, digital broadcasting and portable Internet, it is necessary to develop a technology that eliminates noise, attenuation and ICI . Recently, intensive studies of the error correction code have been performed as a way to increase the reliability of data transmission by efficiently recovering distorted information.

The LDPC code, first introduced by Gallagher in the 1960s, lost its appeal over time, due to the complexity of its implementation, which could not be improved using the technology of that time. However, as a turbo code, which was discovered by Burrow, Glavier, and Sitimashima in 1993, it exhibits performance characteristics approaching the Shannon channel limit, while iterative decoding and coding of the channel based on the graph were studied, along with an analysis of performance and characteristics turbo code. Thanks to such studies, the LDPC code was re-examined in the late 1990s. and proved that the LDPC code has characteristics approaching the Shannon channel limit if it is decoded using iterative decoding based on the product-summation algorithm according to the Tanner graph (a special case of the factor graph) corresponding to the LDPC code.

LDPC code is usually represented using graph representation technology, and many characteristics can be analyzed using methods based on graph theory, algebra, and probability theory. Typically, a channel code graph model is useful for describing codes, and by mapping the information of the encoded bits to the vertices of the graph and displaying the relationships between the bits on the edges of the graph, it becomes possible to consider a data network in which the vertices exchange specified messages through the edges, thus allowing derive a natural decoding algorithm. For example, a decoding algorithm derived from a lattice, which can be considered as a kind of graph, may include the well-known Viterbi algorithm and the Bal, Koke, Yelinek and Raviv algorithm (BCJR, BKER).

The LDPC code is usually defined as a parity check matrix, and it can be represented using a bipartite graph called the Tanner graph. A bipartite graph means that the vertices that make up the graph are divided into two different types, and the LDPC code is represented by a bipartite graph consisting of vertices, some of which are called variable nodes, and others of which are called verification nodes. Different nodes map to coded bits in a one-to-one correspondence.

With reference to FIG. 1 and 2, a description will be given of a graph presentation method for an LDPC code.

In FIG. 1 shows an example of a parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns. As shown in FIG. 1, since the number of columns is 8, the parity check matrix H ₁ means an LDPC code that generates a codeword of length 8, and the columns are mapped to 8 encoded bits.

In FIG. 2 is a diagram illustrating the Tanner graph corresponding to H1 of FIG. one.

Consider FIG. 2, on which the Tanner graph of the LDPC code consists of 8 variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214) and x ₈ (216), and 4 test nodes 218, 220, 222 and 224. The i-th column and the j-th row in the matrix H ₁ of the parity check of the LDPC code are mapped to the variable node x _i , and j th test node, respectively. In addition, the value 1, that is, the non-zero value at the point where the i-th column and the j-th row in the matrix H ₁ of the parity check of the LDPC code intersect each other, means that there is an edge between the variable node x _i and j the test node in the Tanner graph of FIG. 2.

In the Tanner column of the LDPC code, the degree of the variable node and the test node means the number of edges connected to each representative node, and the degree is equal to the number of nonzero entry points in the column or row corresponding to the associated node in the parity check matrix of the LDPC code. For example, in FIG. 2, degrees of variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214) and x ₈ ( 216) are 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and the degrees of the test nodes 218, 220, 222, and 224 are 6, 5, 5, and 5, respectively. In addition, the number of non-zero entry points in the columns of the parity check matrix H _{1 of} FIG. 1, which correspond to the variable nodes in FIG. 2 coincide with their degrees 4, 3, 3, 3, 2, 2, 2, and 2, and the number of nonzero entry points in the rows of the parity check matrix H _{1 of} FIG. 1, which correspond to the test nodes of FIG. 2, coincide with their degrees 6, 5, 5 and 5.

To represent the degree distribution for nodes of the LDPC code, the ratio of the number of variable nodes with degree i with the total number of variable nodes is defined as f _i , and the ratio of the number of test nodes with degree j to the total number of test nodes is defined as g _j . For example, for the LDPC code corresponding to FIG. 1 and 2, f ₂ = 4/8, f ₃ = 3/8, f ₄ = 1/8, and f _i = 0 for i ≠ 2, 3, 4; and g ₅ = 3/4, g ₆ = 1/4, and g _j = 0 for j ≠ 5, 6. When the length of the LDPC code is defined as N, that is, the number of columns is defined as N, and when the number of rows is defined as N / 2, the density of non-zero entry points in the entire parity check matrix having the degree distribution described above is calculated as equation (1).

(1)

(one)

In equation (1), as N increases, the density of units in the parity check matrix decreases. Typically, with regard to the LDPC code, since the length of the N code is inversely proportional to the density of non-zero entry points, the LDPC code with a large N value has a very low density. The expression "low density" in the name of the LDPC code comes from the above interdependence.

Next, with reference to FIG. 3, characteristics of a parity check matrix of a structured LDPC code used in the present invention will be described. In FIG. 3 schematically illustrates an LDPC code adopted as a standard technology in DVB-S2 (Satellite Broadcasting Standard), which is one of the European standards for digital broadcasting.

In FIG. 3, N ₁ denotes the length of the LDPC codeword, K ₁ provides the length of the information word, and (N ₁ -K ₁ ) provides the length of the parity check. In addition, M ₁ and Q are defined so that q = (N ₁ -K ₁ ) / M _{1 is} satisfied. Preferably, the ratio K ₁ / M ₁ should be an integer. For convenience, the parity check matrix of FIG. 3 is called the first parity check matrix H ₁ .

Consider again FIG. 3, in which the structure of the parity check part, that is, the K _1st column is the (N ₁ -1) column, in the parity check matrix, has a double diagonal shape. Therefore, with regard to the distribution of the degree among the columns corresponding to the parity part, all columns have a degree of “2”, with the exception of the last column having a degree of “1”.

In the parity check matrix, the structure of the information part, that is, the 0th column - (K ₁ -1) -th column is obtained using the following rules.

Rule 1: It generates a total of K ₁ / M ₁ column groups by grouping K ₁ columns corresponding to the information word in the parity check matrix into a plurality of groups of M ₁ columns. The method for generating columns belonging to each group of columns is in accordance with Rule 2 below.

Rule 2: First, determine the positions of units in each 0th column of the i-th group of columns (where i = 1, ..., K ₁ / M ₁ ). When the degree of the 0th column in each i-th group of columns is denoted by D _i , if we assume that the positions of rows with 1 are R ⁽¹⁾ _{i, 0,} R ⁽²⁾ _{i, 0} , ... R ^{(Di )} _{i, 0} , positions R ^(k) _{i, j} (k = 1,2, ..., D _i ) of rows with 1 are defined as equation (2), in the jth column (where j = 1, 2, ..., M _j -1) in the group of the ith column.

(2) $$\begin{array}{l}{R}_{i,j}^{(k)}=\{R_{i,(j-\mathrm{one})}^{(k)}+q\}\mathrm{mod}(N_{\mathrm{one}}-K_{\mathrm{one}}),\\ k=\mathrm{1,2,\; ...,}{D}_i,i=\mathrm{one,...,}{K}_{\mathrm{one}}/M_{\mathrm{one}},j=\mathrm{one,...,}{M}_{\mathrm{one}}-\mathrm{one}\end{array}$$

(2)

In accordance with the above rules, it can be expected that not all degrees of columns belonging to the i-th group of columns are equal to D _i . For a better understanding of the DVB-S2 LDPC code structure, which contains information about the parity check matrix in accordance with the rules described above, the following detailed example will be described.

As a detailed example, for N ₁ = 30, K ₁ = 15, M ₁ = 5, and q = 3, three sequences for position information of lines with 1 (below these sequences are referred to as “position sequence with weight 1” for convenience) for 0th columns in 3 groups of columns can be expressed as follows;

As for the position sequence with a weight of 1 for the 0-column in each column group, only the corresponding position sequences can be expressed for convenience as follows for each group of columns. For example:

0 1 2

0 11 13

0 10 14.

In other words, the i-th position sequence with a weight of 1 in the i-th row sequentially represents information about the position of rows from 1 in the i-th column group.

It is possible to generate an LDPC code having the same concept as in the DVB-S2 LDPC code of FIG. 4, forming a parity check matrix, using the information corresponding to the detailed example and Rule 1 and Rule 2.

It is known that the DVB-S2 LDPC code developed in accordance with Rule 1 and Rule 2 can be effectively encoded using the structural form. The process of performing LDPC encoding using a parity check matrix and based on DVB-S2 will be described below as an example.

In the following exemplary description, as a detailed example, the DVB-S2 LDPC code with N ₁ = 16200, K ₁ = 10800, M ₁ = 360, and q = 15 is subjected to an encoding process. For convenience, information bits having a length K ₁ are represented as (i ₀ , i ₁ , ..., i _K-1 ), and parity bits having a length (N ₁ -K1) are expressed as (p ₀ , p ₁ , ..., p _N1-K1-1 ).

Step 1: the encoder initializes the parity bits as follows:

p ₀ = p ₁ = ... = p _N1-K1-1 = 0

Stage 2: The encoder reads information about the line where 1 is located, within the first group of columns of the information word, from a sequence of 0 positions with a weight of 1 stored sequences representing the parity check matrix.

0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622

The encoder updates the specific parity check bits p _x in accordance with equation (3) using the read information and the first information bit i ₀ . Here x means the value of R ^(k) _1,0 for k = 1,2, ..., 13.

(3)

(3)

i₀ также может быть выражено как p_x ← p_x $$\oplus$$

i₀, и $$\oplus$$

означает двоичное суммирование.In equation (3), p _x = p _x $$\oplus$$

i ₀ can also be expressed as p _x ← p _x $$\oplus$$

i ₀ and $$\oplus$$

means binary summation.

Step 3: the encoder first finds the value of equation (4) for the next 359 information bits i _m (where m = 1, 2, ..., 359) after i ₀ .

(4)

(four)

In equation (4), x means the value of R ^(k) _{i, 0} for k = 1,2, ..., 13. It should be noted that equation (4) has the same concept as equation (2).

Next, the encoder performs an operation similar to equation (3) using the value found in equation (4). Thus, the encoder updates P _{{x + (m modM1) xq} mod (N1-K1)} for i _m . For example, for m = 1, that is, for i ₁ , the encoder updates the parity check bits P _{(x + q) mod (N1-K1)} as defined in equation (5).

(5)

(5)

It should be noted that q = 15 in equation (5). The encoder performs the above processing for m = 1, 2, ..., 359, in the same way as shown above.

Stage 4: As in stage 2, the encoder reads the information R ^(K) _2,0 (k = 1,2, ..., 13), the 1st sequence of positions with a weight of 1 for the 361st information bit i ₃₆₀ and updates the specific value of p _x , where x means R ^(K) _2.0 . The encoder updates P _{{x-1 (m modM1) xq} mod (N1-K1),} m = 361,362, ..., 719, similarly applying equation (4) to the next 359 information bits i ₃₆₁ , i ₃₆₂ , ... , i ₇₁₉ after i _360.

Step 5: the encoder repeats steps 2, 3 and 4 for all groups, each of which has 360 information bits.

Step 6: the encoder ultimately determines the parity bits using equation (6).

(6)

(6)

The parity check bits p _{i of} equation (6) are the parity check bits that have been subjected to LDPC coding.

As described above, the DVB-S2 performs encoding using the processing in step 1 through step 6.

In order to apply the LDPC code in an actual communication system, the LDPC code must be designed to match the data rate required in the data system. In particular, not only in adaptive communication systems using a hybrid automatic retransmission request scheme (HARQ, HARQ) and adaptive modulation and coding scheme (AMC, AMC), but also in a communication system supporting various broadcast services, LDPC codes are required having different keyword lengths to support different data rates in accordance with the requirements of the system.

However, as described above, the LDPC code used in the DVB-S2 system has only two types of codeword lengths due to its limited use, and each type of LDPC code requires an independent parity check matrix. For these reasons, there is an urgent need in the art to develop a method for supporting different keyword lengths, to increase the possibility of expansion and increase the flexibility of the system. In particular, in the DVB-S2 system, the transmission of data containing from several hundred to thousands of bits is necessary for transmitting signal information. However, since only 16,200 and 64,800 are available as DVB-S2 LDPC code lengths, it is necessary to provide support for different codeword lengths.

In addition, since keeping an independent parity check matrix separately for each codeword length for an LDPC code reduces the overall memory usage, there is a need for a scheme that can effectively support different codeword lengths from a given existing parity check matrix, without the need compiling a new parity check matrix.

SUMMARY OF THE INVENTION

An exemplary aspect of the present invention is to provide a channel coding / decoding method and apparatus for generating LDPC codes having different codeword lengths from a given LDPC code using shortening or puncturing in a communication system using LDPC codes.

Another exemplary aspect of the present invention is to provide a method and apparatus for channel coding / decoding that ensures optimal performance with respect to the DVB-S2 architecture in a communication system that uses LDPC codes.

According to an exemplary aspect of the present invention, there is provided a channel coding method in a communication system using a low density parity check code (LDPC). The method may include, for example, the steps of generating a plurality of column groups by grouping the columns corresponding to the information word in the parity check matrix of the LDPC code, and arranging the column groups; determining the range of the information word to be obtained by performing the reduction; based on a certain range of the information word, column group reduction is performed, column group after column group for column groups, in order, in accordance with a predetermined reduction structure; and perform LDPC encoding of the shortened information word.

In accordance with another exemplary aspect of the present invention, there is provided a channel coding method in a communication system using a low density parity check code (LDPC). The method may include the steps that generate a plurality of column groups by grouping the columns corresponding to the information word in the parity check matrix of the LDPC code, and arranging the column groups; determining the range of the information word to be obtained by performing the reduction; based on a certain range of the information word, a column group is reduced by a column group for a group of columns, in order, in accordance with a predetermined reduction structure; and perform LDPC encoding of the shortened information word; moreover, performing the reduction, the group of columns after the group of columns contains the stages, which include 168 bits of the Parity Bose-Chowdhury-Hockenham (BCH) in the information word that you want to obtain as a result of the reduction, and perform the reduction of the columns except for the columns in the positions corresponding 168 BCH parity bits.

In accordance with another exemplary aspect of the present invention, there is provided a device for channel coding in a communication system using a low density parity check code (LDPC). The apparatus includes a parity check matrix extractor for generating a plurality of column groups by grouping columns corresponding to an information word in an LDPC code parity check matrix and arranging column groups; an abbreviation structure application module for determining a range of an information word to be obtained by performing abbreviation, and, based on a certain range of an information word, performing abbreviation, column group after column group for column groups, in order, in accordance with a predetermined reduction structure; and an encoder for encoding the LDPC of the shortened information word.

In accordance with another exemplary aspect of the present invention, there is provided an apparatus for channel coding in a communication system using a low density parity check code (LDPC). The apparatus includes a parity check matrix extractor for generating a plurality of column groups by grouping columns corresponding to an information word in an LDPC code parity check matrix and arranging column groups; an abbreviation structure application module for determining the range of the information word to be obtained by performing abbreviation and, based on a certain range of the information word, performing abbreviation column group after column group for column groups, in order, in accordance with the specified structure of the reduction; and an encoder for encoding the LDPC of the shortened information word; moreover, when performing the reduction, the group of columns after the group of columns, the module for applying the reduction structure includes, for example, 168 Bowse-Chowdhury-Hockenham (BCH) parity bits in the information word to be obtained as a result of the reduction, and reduces the columns, except for the columns at positions corresponding to 168 BCH parity bits.

In accordance with another exemplary aspect of the present invention, a channel decoding method in a communication system using a low density parity check code (LDPC) is provided. The method includes, for example, the steps of demodulating a signal transmitted from a transmitter; determining the position of the abbreviated bit by evaluating information on the structure of the abbreviation of the LDPC code obtained from the demodulated signal; and decode the data using the specific position of the reduced bit.

In accordance with yet another exemplary aspect of the present invention, there is provided an apparatus for channel decoding in a communication system using a low density parity check code (LDPC). The device includes, for example, a demodulator designed to demodulate a signal transmitted from a transmitter; an abbreviation structure determiner for determining the position of the abbreviated bit by evaluating information on the abbreviation structure of the LDPC code from the demodulated signal; and a decoder for decoding data using the determined position of the reduced bit.

In accordance with another exemplary aspect of the present invention, there is provided a method for demodulating a received signal, determining the position of the reduced information bits, and decoding the demodulated signal based on the determined position of the reduced information bits, wherein determining the position of the reduced information bits includes dividing the information bits into a plurality of bit groups, determining the number of reduced information bits, determining the number of reduced bit groups based on the definition Nogo number of information bits that need to be cut, and the determination of reduced bit groups based on a predetermined order.

In accordance with yet another exemplary aspect of the present invention, there is provided an apparatus for implementing a demodulator for demodulating a received signal, an abbreviation structure determiner for determining the position of the abridged information bits, and a decoder for decoding the demodulated signal taking into account the determined position of the abridged information bits, wherein determining the position of the abridged information bits includes dividing information bits into many bit groups, determining the number of abbreviations are information bits, determining the number of abbreviated bit groups based on the determined number of information bits that need to be cut, and the determination of reduced bit groups based on a predetermined order.

Brief Description of the Drawings

The above and other aspects, properties and advantages of the present invention will be better understood from the following detailed description of the invention when considered in conjunction with the attached drawings, in which:

in FIG. 1 is a diagram illustrating an example parity check matrix of an LDPC code of length 8;

in FIG. 2 is a diagram illustrating a Tanner graph for an exemplary LDPC parity check matrix of length 8;

in FIG. 3 is a diagram illustrating a schematic structure of a DVB-S2 LDPC code;

in FIG. 4 is a diagram illustrating an example DVB-S2 LDPC code parity check matrix;

in FIG. 5 is a block diagram illustrating a structure of a transceiver in a communication system using LDPC codes;

in FIG. 6 is a flowchart illustrating a process for generating an LDPC code having a different codeword length from a parity check matrix of a stored LDPC code, in accordance with an exemplary embodiment of the present invention;

in FIG. 7 is a block diagram illustrating a structure of a transmission device using abbreviated LDPC codes in accordance with an embodiment of the present invention;

in FIG. 8 is a block diagram illustrating a structure of a transmission device using abbreviated / punctured LDPC codes in accordance with an exemplary embodiment of the present invention;

in FIG. 9 is a block diagram illustrating a structure of a reception apparatus using LDPC codes for which abbreviation is applied in accordance with an exemplary embodiment of the present invention;

in FIG. 10 is a block diagram illustrating a structure of a reception apparatus using LDPC codes that simultaneously use shortening and puncturing codes, in accordance with an exemplary embodiment of the present invention; and

in FIG. 11 is a flowchart illustrating a reception operation in a reception apparatus according to an exemplary embodiment of the present invention.

In the drawings, the same reference numerals should be understood as referring to the same elements, properties, and structures.

DETAILED DESCRIPTION OF THE INVENTION

Preferred exemplary embodiments of the present invention will be described in detail below with reference to the attached drawings. In the following description, a detailed description of known functions and exemplary configurations included herein may be omitted for clarity and brevity, when their inclusion may complicate the understanding of the invention to a person skilled in the art.

The present invention is directed to a method for supporting LDPC codes having different codeword lengths using a parity check matrix of a specific type of structured LDPC code. In addition, the present invention is directed to an apparatus for supporting various codeword lengths in a communication system using a specific type of LDPC, and a method for controlling it. In particular, the present invention is directed to a method and apparatus for generating an LDPC code using a parity check matrix of a given LDPC code, wherein the generated LDPC code is shorter than the specified LDPC code.

In FIG. 5 is a block diagram illustrating a structure of a transceiver in a communication system using LDPC codes.

As shown in FIG. 5, the message u is input to the LDPC encoder 511 at the transmitter 510 before being transmitted to the receiver 530. The LDPC encoder 511 then encodes the input message u and outputs the encoded signal to the modulator 513. Modulator 513 modulates the encoded signal and transmits this modulated signal to the receiver 530 wirelessly 520. Then, the demodulator 531 at the receiver 530 demodulates the signal transmitted by the transmitter 510 and outputs the demodulated signal to the LDPC decoder 533. Then, the LDPC decoder 533 estimates the value of the message u based on the data received through the wireless channel 520.

The LDPC encoder 511 generates a parity check matrix in accordance with the codeword length required in the communication system using a predetermined scheme. In particular, in accordance with the present invention, the LDPC encoder 511 can support different codeword lengths using the LDPC code without the separate need to store additional information. A detailed operation of the LDPC encoder to support various codeword lengths will be described below with reference to FIG. 6.

In FIG. 6 is a flowchart illustrating an encoding operation of an LDPC encoder according to an exemplary embodiment of the present invention. More specifically, in FIG. 6 shows a method for generating LDPC codes having different codeword lengths from a parity check matrix of a previously stored LDPC code.

Here, in a method for supporting different codeword lengths, reduction technology and puncturing technology are used.

The term “reduction technology” as used herein means a method in which a specific part of a given specific parity check matrix is not substantially used. For a better understanding of the reduction technology, the parity check matrix of the DVB-S2 LDPC code shown in FIG. 3.

Consider now the parity check matrix of the DVB-S2 LDPC code shown in FIG. 3, its total length is N ₁ , the leading part corresponds to information bits (i ₀ , i ₁ , ..., i _K1-1 ) of length K _1, and the back part corresponds to bits (p ₀ , p ₁ , ..., p _N1-K1-1) a parity check of length (N ₁ -K ₁ ). Typically, information bits freely have a value of 0 or 1, and reduction technologies limit the values of information bits of a particular part to be reduced. For example, the abbreviation N _{s of} information bits i ₀ - i _Ns-1 usually means that i ₀ = i ₁ = ... = i _N1-1 = 0. In other words, by limiting the value of N _s information bits i ₀ - i _Ns-1 to 0, the reduction technology allows you to get the same effect as, essentially, when not using Ns leading columns in the matrix parity check code DVB-S2 LDPC shown in FIG. 3. The term “reduction technology” is derived from the reduction operation mentioned above. Therefore, the use of abbreviations here means taking into account the values of the abbreviated information bits as equal to 0.

With regard to reduction technology during system installation, the transmitter and receiver can share or generate the same position information for the reduced information bits. Therefore, although the transmitter does not transmit the abbreviated bits, the receiver performs decoding, knowing that the information bits at the positions corresponding to the abbreviated bits have a value of 0.

In abbreviation technology, since the length of the codeword that the transmitter actually transmits is N ₁ -N _S and the length of the information word is also K ₁ -N _S , the code rate becomes (K ₁ -N _S ) / (N ₁ -N _S ), which is always less than the first given code speed K ₁ / N ₁ .

Next, puncturing technology will be described in detail. Typically, puncturing can be applied to both information bits and parity bits. Although the puncturing technology and the reduction technology perform the same function of reducing the codeword length of codes, the puncturing technology, unlike the reduction technology described above, does not have a concept that limits the values of certain bits. The puncturing technology is a method in which a transmission of certain information bits or a certain group of generated parity bits is simply not performed so that the receiver can perform the deletion processing of the corresponding bits. In other words, by simply not transmitting bits at N _p specific positions in the generated LDPC codeword of length N ₁ , the puncturing technique allows to obtain the same effect as when transmitting the LDPC codeword of length (N ₁ - N _p ). Since all columns corresponding to the bits punctured in the parity check matrix are used without disruption in the decoding process, the puncturing technology is different from the reduction technology.

Since, according to the invention, information about the position of the punctured bits can equally be shared or evaluated by the transmitter and the receiver when installing the system, the receiver performs deletion processing of the respective punctured bits before decoding.

In puncturing technology, since the length of the codeword that the transmitter actually transmits is N ₁ -N _p and the length of the information word is constantly K ₁ , the code speed becomes K ₁ / (N ₁ -N _p ), which is always greater than the first target speed K ₁ / N ₁ code.

Next, a description will be made of an example reduction technology and an example puncturing technology suitable for DVB-S2 LDPC code. The DVB-S2 LDPC code, as noted above, is a kind of LDPC code having a specific structure. Therefore, compared to the normal LDPC code, the DVB-S2 LDPC code can undergo a more efficient reduction and puncturing.

обычно отличается от скорости K₁/N₁ кода для кода DVB-S2 LDPC, его алгебраические характеристики изменяются. Для N_Δ=K_Δ код LDPC генерируют, не используя ни сокращение, ни выкалывание, или используя только сокращение.For the convenience of this example, suppose that the codeword length and the length of the LDPC code information are N ₂ and K ₂ , respectively, which, in accordance with the present invention, ultimately need to be obtained from the DVB-S2 LDPC code, the codeword length and the information length of which is N ₁ and K ₁ , respectively, using reduction technology and puncturing technology. If N ₁ -N ₂ = N _Δ and K ₁ -K ₂ = K _Δ, it becomes possible to generate an LDPC code whose codeword length and information length are N ₂ and K ₂ , respectively, by reducing K _Δ bits and puncturing ( N _Δ -K _Δ ) bits from the DVB-S2 LDPC code parity matrix. For the generated code, N _Δ > 0 or K _Δ > 0, since its code rate

usually different from code speed K ₁ / N ₁ for DVB-S2 LDPC code, its algebraic characteristics change. For N _Δ = K _Δ, the LDPC code is generated using neither shortening nor puncturing, or using only shortening.

соответствует М₁ столбцам, в сумме каждая из групп K₁/N₁ столбцов имеет структурную форму. Поэтому код DVB-S2 LDPC равен коду LDPC, в котором не используется М₁ столбцов, если в нем не используется одно значение R^(k) _i,j. Следующий процесс сокращения предложен, учитывая такие характеристики.However, with regard to the DVB-S2 LDPC code, as described in Rule 1 and Rule 2, since one value

corresponds to M ₁ columns; in sum, each of the groups K ₁ / N ₁ columns has a structural form. Therefore, the DVB-S2 LDPC code is equal to the LDPC code, which does not use M ₁ columns, if it does not use the same value of R ^(k) _{i, j} . The following reduction process has been proposed considering such characteristics.

In step 601, the LDPC encoder 511 reads the group information of the column of DVB-S2 LDPC code being truncated. Thus, the LDPC encoder 511 reads the stored information of the parity check matrix. Thereafter, in step 603, the LDPC encoder 511 determines the codeword length N ₂ and the information length K ₂ for the abbreviated LDPC codeword, for actual transmission after the abbreviation. Thereafter, the LDPC encoder 511 performs abbreviation processing in steps 605-611, in which the LDPC encoder 511 performs abbreviation corresponding to the required length of the LDPC code information based on the read information of the stored parity check matrix.

на этапе 605, где [x] означает максимальное целое число, которое меньше чем или равно x.Reduction Stage 1: LDPC encoder 511 defines

at step 605, where [x] means the maximum integer that is less than or equal to x.

на этапе 607, и выбранная последовательность определена как

. Кодер 511 LDPC учитывает, что отсутствует последовательность R^(k) _i,0 для остальных групп столбцов K₁/M₁-A-1.Stage 2 abbreviations: LDPC encoder 511 selects a sequence for (A + 1) groups of columns among

 at step 607, and the selected sequence is defined as

. LDPC encoder 511 takes into account that there is no sequence R^(k) _{i, 0}for other groups of columns K_one/ M_one-A-1.

Stage 3 abbreviations: LDPC encoder 511 generates an abbreviated DVB-S2 LDPC code from A + 1 S ^(k) _{i, 0} values selected in step 2 of the abbreviation using Rule 1 and Rule 2 in step 609. It should be noted that the abbreviated LDPC code has a length of information (A + 1) M ₁ , which is always greater than or equal to K ₂ .

Stage 4 reduction: the LDPC encoder 511 further reduces in step 611 (A + 1) M ₁ -K ₂ columns for the abbreviated LDPC code generated in step 3 of the reduction.

To describe the detailed examples, a detailed description will be given below of the processing for generating a new LDPC code, the codeword of which is N ₂ = 4050 and the information length of which is K ₂ -1170, by reducing 12150 bits of information bits using the DVB-S2 LDPC code, which has characteristic N ₁ = 16200, K ₁ = 13320, M ₁ = 360 and q = 9.

Abbreviation Step 1 Example: LDPC encoder 511 determines

Example of abbreviation step 2: the LDPC encoder 511 selects a sequence for 4 groups of columns among a total of 37 R ^(k) _{i, 0} values. In this particular example, the LDPC encoder 511 selects the following sequence.

Example of abbreviation step 3: LDPC encoder 511 generates an abbreviated DVB-S2 LDPC code from 4 S ^(k) _{i, 0} values selected in the abbreviation step 2 example using Rule 1 and Rule 2. For an abbreviated LDPC code, the length of its information word is 4x360 = 1440.

Example of abbreviation step 4: the LDPC encoder 511 further reduces 1440-1170 = 270 columns for the abbreviated LDPC code generated in the abbreviation step 3 example. The LDPC encoder 511 performs encoding based on the abbreviated LDPC code.

значений не используется, это эквивалентно сокращению в сумме 33x360=11880 битов в примере этапа 2 сокращения. Кроме того, поскольку в кодере 511 LDPC сокращено 270 информационных битов в ходе примера этапа 3 сокращения и примера этапа 4 сокращения, в конечном итоге, это становится эквивалентно сокращению 12150 информационных битов. Поэтому результат варианта выполнения представляет сокращенный код LDPC с длиной N₂=4050 кодового слова и длиной K₂=1170 информации.According to an exemplary embodiment, since sequence information for K ₁ / M ₁ -A-1 = 13320 / 360-4 = 33 groups of columns among

values are not used, this is equivalent to a reduction of 33x360 = 11880 bits in the example of stage 2 reduction. In addition, since 270 information bits are reduced in the LDPC encoder 511 during the example of the reduction stage 3 and the example of the reduction stage 4, this ultimately becomes equivalent to the reduction of 12150 information bits. Therefore, the result of an embodiment is an abbreviated LDPC code with a codeword length N ₂ = 4050 and information length K ₂ = 1170.

As described above, the present invention allows the use of an effective reduction technology in which, compared to the bit-by-bit reduction technology commonly used to reduce DVB-S2 LDPC code, a method is used that does not use information in DVB-S2 LDPC code column groups depending on the structural properties of the DVB-S2 LDPC code.

The selection of sequence criteria for groups of columns can be briefly reduced to step 2 in the process of reducing the DVB-S2 LDPC code.

Criterion 1: the LDPC encoder 511 selects an abbreviated LDPC code with a codeword length N ₂ and information length K ₂ obtained by performing a DVB-S2 LDPC code abbreviation with a codeword length N ₁ and information length K ₂ , wherein the degree distribution of the selected abbreviated code LDPC is almost analogous to the optimal degree distribution of a normal LDPC code with codeword length N ₂ and information length K ₂ .

Criterion 2: the LDPC encoder 511 selects a code having a good loop characteristic on the Tanner graph among the abbreviated codes selected according to criterion 1. In the present invention, with regard to the criterion for the loop characteristic, the LDPC encoder 511 selects a case in which the cycles of the minimum length in the Tanner graph are as large as possible, and the number of cycles of minimum length is as small as possible.

Although the optimal degree distribution of the normal LDPC code can be determined by criterion 1 using a density evolution analysis method, a detailed description thereof will be excluded because it does not correspond to the understanding of the present invention.

If the number of options for choosing a sequence of positions with a weight of 1 for a column group is not large, the LDPC encoder 511 can select a sequence of positions with a weight of 1 for the corresponding column group that has the best characteristics by fully searching all cases, regardless of criterion 1 and criterion 2. However, selection criteria for column groups used in step 2 of the DVB-S2 LDPC code reduction can increase their efficiency by selecting an LDPC code that simultaneously satisfies the conditions when the number of selections is sequential different positions with weight 1 for the column group is too large.

To describe an example of a good sequence obtained by applying the criteria for selecting a sequence of positions with a weight of 1 for a group of columns, we will consider the DVB-S2 code with N ₁ = 16200, K ₁ = 3240, M ₁ = 360, and q = 36. The DVB-S2 LDPC code has the following sequence of positions with a weight of 1 over column groups.

6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 12557

10691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 11090

10774 3613 5208 11177 7676 3549 8746 6583 7239 12,265 2,674 4,292

11869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 11120

7844 3079 10773

3385 10854 5747

1360 12010 12202

6189 4241 2343

9840 12726 4977

The i-th sequence of positions with a weight of 1 in the i-th row sequentially represents information about the positions of rows with 1 for the i-th group of columns. Therefore, it can be understood that the DVB-S2 LDPC code consists of 9 groups of columns, and the length of its information is 9x360 = 3240. If the length of the codeword and the length of the information that should be obtained when performing the reduction are N ₂ and K ₂ , respectively, it becomes possible to determine the optimized structure of the reduction using stage 1 reduction - stage 4 reduction.

However, when the N ₂ and K ₂ values required by the system are extremely variable, the optimized contraction structure may not correlate with the N ₂ value. For example, assuming that with the optimal choice for the case necessary to reduce 2 groups of columns from the DVB-S2 LDPC code, information about rows from 1 in the 4th and 8th column groups is not used, since the choice and reduction of the 1st The 5th and 6th groups of columns can also be optimal when choosing 3 groups of columns; they do not have correlation with each other. Therefore, when the N ₂ and K ₂ values required by the system are extremely variable, it is not advisable to preserve all optimized contraction structures in accordance with the K ₂ value for optimized performance.

Thus, if the values of N ₂ and K ₂ required by the system are extremely variable, can be found close in the optimal structure of the reduction, using the following method for the efficiency of the system.

First, suppose that the choice of 1 group of columns is necessary for reduction. In this case, since the number of selectable column groups is only 1 in the optimal sense, it becomes possible to select the column group with the highest performance. Then, when there is a need to select 2 column groups for reduction, the LDPC encoder 511 selects a column group representing the best performance among the remaining column groups including the selected 1 column group. In the same way, when there is a need to select i column groups for reduction, the LDPC encoder 511 selects one column group with the highest performance among the remaining column groups including (i-1) column groups selected in the previous step for reduction.

The reduction method, although it cannot guarantee optimal selection, can stabilize performance from one reduction structure, regardless of the change in K ₂ value.

As a detailed example, when the values of N ₂ and K ₂ required by the system are extremely variable, it becomes possible to find near-optimal reduction patterns in accordance with N ₂ and K ₂ for 9 cases shown in Table 1. Here N ₂ = N ₁ -K ₂ , because puncturing technology is not considered.

Table 1 K range ₂ Reduction method 1) 2880≤K ₂ <3240 Reduce 3240-K ₂ bits from the information word corresponding to the 8th sequence of 6189 4241 2343 for the 8th group of columns among sequences of positions with a weight of 1. 2) 2520≤K ₂ <2880 Reduce all the columns included in the group of columns that correspond to the 8th sequence among sequences of positions with a weight of 1 and further reduce 2880-K ₂ bits from the information word corresponding to the 4th sequence
11869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 11120
for the 4th group of columns. 3) 2160≤K ₂ <2520 Reduce all columns included in the column group that correspond to the 8th and 4th sequences among position sequences with a weight of 1, and further reduce 252-K₂bits from the information word corresponding to the 7th sequence
1360 12010 12202
for the 7th group of columns.

4) 1800≤K ₂ <2160 Reduce all the columns included in the group of columns that correspond to the 8th, 4th and 7th sequences among position sequences with a weight of 1 and further reduce 2160-K ₂ bits from the information word corresponding to the 6th sequence
3385 10854 5747
for the 6th group of columns. 5) 1440≤K ₂ <1800 Reduce all the columns included in the group of columns that correspond to the 8th, 4th, 7th and 6th sequences among sequences of positions with a weight of 1, and further reduce 1880-K ₂ bits from the information word corresponding to the 3rd sequences
10774 3613 5208 11177 7676 3549 8746 6583 7239 12,265 2,674 4,292
for the 3rd group of columns. 6) 1080≤K ₂ <1440 Reduce all the columns included in the group of columns that correspond to the 8th, 4th, 7th, 6th and 3rd sequences among position sequences with a weight of 1, and further reduce 1440-K ₂ bits from the information word, corresponding to the 5th sequence
7844 3079 10773
for the 5th group of columns.

7) 720≤K ₂ <1080 Reduce all the columns included in the group of columns that correspond to the 8th, 4th, 7th, 6th, 3rd and 5th sequences among position sequences with a weight of 1, and further reduce 1080-K ₂ bits from the information word corresponding to the 2nd sequence
10691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 11090
for the 2nd group of columns. 8) 528≤K ₂ <720 Reduce all the columns included in the column group that correspond to the 8th, 4th, 7th, 6th, 3rd, 5th and 2nd sequences among sequences of positions with a weight of 1, and further reduce 720 -K ₂ bits from the information word corresponding to the 9th sequence
9840 12726 4977
for the 9th group of columns. However, since the 168 BCH parity bits are mapped to part of a group of columns that correspond to the 9th sequence using the DVB-S2 coding scheme, the columns at the positions corresponding to the BCH parity check are not reduced.

9) 168≤K ₂ <528 Reduce all the columns included in the group of columns that correspond to the 8th, 4th, 7th, 6th, 3rd, 5th, 2nd and 9th sequences among sequences of positions with a weight of 1, and further reduce 528-K ₂ bits from the information word corresponding to the 1st sequence
6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 12557
for the 1st group of columns. Here, K ₂ = 168 means the case where only columns corresponding to BCH parity remain in the DVB-S2 LDPC code. In other words, there are no clear bits of the information word. This does not count.

The order of abbreviations in table 1 is determined by, for example, dividing an information word into 9 intervals, followed by applying criterion 1 and criterion 2 to it.

As for table 1, you can see that all the columns corresponding to the 8th, 4th, 7th, 6th, 3rd, 5th, 2nd, 9th and 1st sequences, the column included in the group is sequentially reduced in accordance with the required length of the LDPC code information. Thus, the value zero is mapped onto the information bits to be reduced, in the order of the columns corresponding to the 8th, 4th, 7th, 6th, 3rd, 5th, 2nd, 9th 1st and 1st lines in accordance with the required length of information. Alternatively, it can also be taken into account that relevant information bits, the values of which are not fixed to 0, are sequentially mapped onto columns corresponding to the 1st, 9th, 2nd, 5th, 3rd, 6th , 7th, 4th and 8th sequences, according to the length of the information. The order of "8, 4, 7, 6, 3, 5, 2, 9, 1" columns can also be expressed as "7, 3, 6, 5, 2, 4, 1, 8, 0," if you represent 1- the column as the 0th block.

In step 8) and in step 9) in table 1, since the last 168 bits of the 9th column group or the last column group, in the part corresponding to the information bits of the DVB-S2 LDPC code with N ₁ = 16200, K ₁ = 3240, M ₁ = 360 and q = 36 are mapped to Bose-Chaudhuri-Hocquenghem (BCH) parity bits and cannot be reduced. In fact, when developing a DVB-S2 LDPC code with N ₁ = 16200, 168 BCH parity bits are always included in LDPC information bits having a length of K ₁ and K ₂ .

The reduction order information shown in table 1 can also be briefly expressed as table 2.

table 2 Key DVB-S2 LDPC Code Variables N ₁ = 16200, K ₁ = 3240, M ₁ = 360, q = 36 K range ₂ Reduction method 1) 528≤K ₂ <3240

сокращают все m групп столбцов, соответствующих π(0)-ой, π(1)-ой, … и π(m-1)-ой группам столбцов, и дополнительно сокращают информационные биты 3240-K₂-360m из π(m)-ой группы столбцов. Здесь π обозначает функцию перестановки, означающую структуру сокращения, и взаимосвязь между ними показана в нижней части таблицы.
Однако, когда сокращают часть π(7)=8-ой группы столбцов, столбцы в положениях, соответствующих 168 битам проверки на четность BCH, не подвергают сокращению.For an integer

reduce all m groups of columns corresponding to the π (0) th, π (1) th, ... and π (m-1) th column groups, and further reduce the information bits 3240-K ₂ -360m from π (m) th group of columns. Here π denotes a permutation function, which means the structure of the reduction, and the relationship between them is shown at the bottom of the table.
However, when a portion of π (7) = the 8th column group is truncated, the columns at positions corresponding to 168 BCH parity bits are not truncated. 2) 168≤K ₂ <528 Reduce all of the π (0) th, π (l) th and π (6) th column groups and shrink all columns except the columns at positions corresponding to 168 BCH parity bits from π (7) = 8 th group of columns. In addition, 528-K ₂ information bits from π (8) = 0-th group of columns are further reduced.

π (0) π (1) π (2) π (3) π (4) π (5) π (6) π (7) π (8) 7 3 6 5 2 four one 8 0

To describe another exemplary embodiment, a DVB-S2 code for N ₁ = 16200, K ₁ = 7200, M ₁ = 360 and q = 25 will be described. The DVB-S2 LDPC code has the following position sequences with a weight of 1.

20 712 2386 6354 4061 1062 5045 5158

21 2543 5748 4822 2348 3089 6328 5876

22 926 5701 269 3693 2438 3190 3507

23 2802 4520 3577 5324 1091 4667 4449

24 5140 2003 1263 4742 6497 1185 6202

0 4046 6934

1 2855 66

2 6694 212

3 3439 1158

4 3850 4422

5 5924 290

6 1467 4049

7 7820 2242

8 4606 3080

9 4633 7877

10 3884 6868

11 8935 4996

12 3028 764

13 5988 1057

14 7411 3450

The i-th sequence sequentially presents information about the position of rows from the 1st to the i-th group of columns. Therefore, it should be understood that the DVB-S2 LDPC code consists of 20 groups of columns, and the information length is 20x360 = 7200. When the length of the codeword and the length of the information that you want to obtain as a result of the abbreviation are N ₂ and K ₂ , respectively, it is possible to find abbreviation structures close to optimal, as defined in Table 3.

Table 3 Key DVB-S2 LDPC Code Variables N ₁ = 16200, K ₁ = 7200, M ₁ = 360, q = 25 K range ₂ Reduction method 1) 528≤K ₂ <7200

сокращают все m групп столбцов, соответствующих π(0)-ой, π(1)-ой,..., и π(m-1)-ой группам столбцов, и дополнительно сокращают информационные биты 7200-K₂-360m из π(m)-ой группы столбцов. Здесь π обозначает функцию перестановки, означающую структуру сокращения, и взаимосвязь между ними, показана в нижней части таблицы.
Однако, когда сокращают часть π(18)=l9-ой группы столбцов, столбцы в положениях, соответствующих 168 битам проверки на четность BCH, не подвергают сокращению.For an integer

reduce all m groups of columns corresponding to the π (0) th, π (1) th, ..., and π (m-1) th column groups, and further reduce the information bits 7200-K ₂ -360m from π (m) th group of columns. Here π denotes a permutation function, meaning the structure of the reduction, and the relationship between them is shown at the bottom of the table.
However, when a portion of π (18) = l9th group of columns is truncated, columns at positions corresponding to 168 BCH parity bits are not truncated.

2) 168≤K ₂ <528 Reduce all of the π (0) th, π (1) th, and π (17) th column groups, and shrink all columns except the columns at positions corresponding to 168 BCH parity bits from π (18) = 19th group of columns. In addition, an additional reduction of 528-K₂information bits from π (19) = the 0th group of columns. π (0) π (1) π (2) π (3) π (4) π (5) π (6) π (7) π (8) π (9) eighteen 17 16 fifteen fourteen 13 12 eleven four 10 π (10) π (11) π (12) π (13) π (14) π (15) π (16) π (17) π (18) π (19) 9 8 3 2 7 6 5 one 19 0

In the reduction process, additional reduction can be more easily implemented if the process is sequentially performed at the back or front of the column group where additional reduction is achieved.

After step 611 in FIG. 6, when puncturing is required, the LDPC encoder 511 applies puncturing in the LDPC encoding process at step 613. The puncturing method will be briefly described below.

If the codeword length and the length of the LDPC code information are defined as N ₂ and K ₂ , respectively, then in accordance with the invention, one should seek to ultimately obtain from the DVB-S2 LDPC code with the code word length N ₁ and information length K ₂ using reduction technology and puncturing technology, and it is specified that N ₁ -N ₂ = N _Δ and K ₁ -K ₂ = K _Δ , LDPC code with a code word length N ₂ and information length K ₂ as a result of the reduction of bits K _Δ and puncturing bits (N _Δ -K _Δ ) from the DVB-S2 LDPC code parity matrix. Assuming that, for convenience, only a part of the parity check is punctured, since the length of the parity check is N ₁ -K _1, there is a way to puncture 1 bit from the parity part every (N ₁ -K ₁ ) / (N _Δ -K _Δ ) bits. However, various other methods can also be used as a puncturing technique.

For N _Δ -K _Δ = 0, there is no need to apply puncturing technology. In this case, it becomes possible to obtain an effectively abbreviated DVB-S2 LDPC code by applying a similar generation method for the DVB-S2 LDPC code using the abbreviation structure shown in Table 1.

In FIG. 7 shows a detailed example of a transmission device for implementing the DVB-S2 LDPC code reduction process. In FIG. 7 is a block diagram illustrating an example structure of a transmission device using abbreviated LDPC codes according to an embodiment of the present invention.

The transmission device includes, for example, a controller 710, an abbreviation pattern applying module 720, an LDPC code parity matrix extractor 740, and an LDPC encoder 760.

The LDPC code parity check matrix extractor 740 extracts an abbreviated LDPC code parity check matrix. The parity check matrix of the LDPC code may be extracted from the storage device, or may be defined in the transmission device, or may be generated by the transmission device.

A controller 710 controls the abbreviation structure application module 720 so that it can determine the abbreviation structure according to the length of the information. The abbreviation structure application module 720 inserts zero (0) bits at abbreviated bit positions, or removes columns corresponding to abridged bits from the parity check matrix of a given LDPC code. The method for determining the abbreviation structure can use the abbreviation structure stored in the memory, generate the abbreviation structure using a sequence generator (not shown), or use the density evolution analysis algorithm for the parity check matrix and its predetermined information length.

A controller 710 controls the abbreviation structure application module 720 so that it can abbreviate a portion of the information bits of the LDPC code in the structures shown in Table 1 through Table 3.

The LDPC encoder 760 performs encoding based on the LDPC code abbreviated by the controller 710 and the abbreviation structure application module 720.

In FIG. 8 and 9 are block diagrams illustrating structures of a transmission device and a reception device for DVB-S2 LDPC code, in which both pruning and puncturing are applied, respectively.

In FIG. 8 is a block diagram illustrating an example structure of a transmission device using abbreviated / punctured LDPC codes in accordance with an embodiment of the present invention.

The transmission device of FIG. 8 further comprises a puncturing pattern application module 880 added to the transmission device of FIG. 7. As shown in FIG. 8, it can be seen that the reduction is performed in the first stage of the LDPC encoder 760, and puncturing is performed in the output stage of the LDPC encoder 760.

A puncturing pattern application module 880 applies puncturing to the output of the LDPC encoder 760. A method for applying puncturing has been described in detail in step 613 with reference to FIG. 6.

In FIG. 9 is a block diagram illustrating an exemplary structure of a reception apparatus using LDPC codes to which abbreviation is applied in accordance with an embodiment of the present invention.

In FIG. 9 shows an example of a reception device that receives a signal transmitted from a data transmission system using the DVB-S2 LDPC abbreviated code and reconstructs the data needed by the user from the received signal when the length of the DVB-S2 LDPC abbreviated code is determined from the received signal.

The receiving device includes, for example, a controller 910, a reduction structure determination / estimation module 920, a demodulator 930, and an LDPC decoder 940.

A demodulator 930 receives and demodulates the abbreviated LDPC code and provides a demodulated signal to the abbreviation structure determination / estimation module 920 and to the LDPC decoder 940.

Module 920 determine / evaluate the structure of the reduction, under the control of the controller 910, evaluates or determines information about the structure of the reduction of the LDPC code from the demodulated signal and provides information about the position of the reduced bits in the decoder 940 LDPC. The method for determining or evaluating the abbreviation structure in abbreviation structure determining / evaluating module 920 may use the abbreviation structure stored in the memory, or may generate the abbreviation structure using a sequence generator (not shown) or using a density evolution analysis algorithm for the parity check matrix and its given length of information.

Since the probability that the abbreviated bit values are zero (0) in the LDPC decoder 940 is 1 (or 100%), the controller 910 determines whether it will decode the abbreviated bits using the LDPC decoder 940 using a probability value of 1.

The LDPC decoder 940 recovers the data needed by the user from the received signal when it determines the length of the DVB-S2 LDPC abbreviated code using the abbreviated structure determination / estimation module 920.

In FIG. 10 is a block diagram illustrating an exemplary structure of a receiving apparatus using LDPC codes, in which contraction and puncturing are simultaneously applied, in accordance with an embodiment of the present invention.

In the receiving device of FIG. 10, the contraction and puncturing structure determination / evaluation module 1020 replaces the abbreviation structure determination / evaluation module 920 of FIG. 9.

When the transmission device simultaneously applies contraction and puncturing, the contraction and puncturing structure determining / evaluating module 1020 in the receiving device may first determine / evaluate the structure for puncturing, or may first determine / evaluate the structure for puncturing, or may simultaneously determine / evaluate the structure for abbreviations and determination / assessment of the structure for puncturing.

The LDPC decoder 940 preferably has information about both pruning and puncturing to perform decoding.

In FIG. 11 is a flowchart illustrating an example receive operation in a reception device according to an embodiment of the present invention.

The demodulator 930 receives and demodulates the abbreviated LDPC code in step 1101. Thereafter, the abbreviation structure determination / evaluation unit 920 determines or performs an assessment of the abbreviation / puncturing structure (s) from the demodulated signal in step 1103.

Module 920 determine / evaluate the structure of the reduction determines at step 1105 whether there is any shortened / punctured bit. If there is no abbreviated / punctured bit, the LDPC decoder 940 performs decoding at 1111. However, if there is a abbreviated / punctured bit), the abbreviation / puncturing structure determination / evaluation unit 1020 provides information on the position of the abbreviated / punctured bits to the LDPC decoder 940 in step 1107. .

In step 1109, based on the position information of the abbreviated / punctured bits, the LDPC decoder 940 determines that the probability that the abbreviated bit values are 0 is 1 and determines that the punctured bits are deleted bits. After that, the LDPC decoder 940 proceeds to step 1111, where it performs LDPC decoding.

As is apparent from the above description, the present invention provides reduction structures, thereby making it possible, essentially, not to use some columns. In addition, the present invention can generate separate LDPC codes having different codeword lengths using information about a given parity check matrix in a communication system in which LDPC codes are applied.

The methods described above in accordance with the present invention can be implemented in the form of hardware or software, or computer code, which can be stored on a recording medium such as a CD-ROM, RAM, floppy disk, hard disk or magneto-optical disk, or be downloaded via the network so that the methods described here can be performed using such software using a general purpose computer or a special processor, or programmable or specialized devices nye agents such as ASIC (ASIC, Application Specific Integrated Circuit) or FPGA (FPGA, Field Programmable Gate Array). It should be understood that in the art, a computer, processor, or programmable hardware includes memory components, for example, RAM (RAM, random access memory), ROM (ROM, read only memory), flash memory, etc. which can store or receive software or computer code that, when accessed and executed by a computer, processor or hardware, embodies the processing methods described herein.

Although the invention has been presented and described with reference to a specific preferred embodiment thereof, it will be understood by a person skilled in the art that various changes in form and detail can be made here without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (12)

1. A channel decoding method in a system using a low density parity check code (LDPC), comprising the steps of:
demodulate the received signal,
determine the position of the reduced information bits, and
decode the demodulated signal, taking into account the specific position of the reduced information bits,
moreover, the determination of the position of the abbreviated information bits contains steps
divide information bits into many bit groups,
determining the number of reduced information bits, determining the number of reduced bit groups based on a certain number of information bits to be reduced, and
shortened bit groups are determined based on a predetermined order. 2. The method according to claim 1, wherein determining the position of the reduced information bits further comprises the step of:
determining the number of information bits to be obtained by reduction to determine the number of information bits to be reduced. 3. The method according to claim 1, wherein if the codeword is 16200 and the number of information bits is 3240, the predetermined order is as follows: 7th bit group, 3rd bit group, 6th bit group, 5- 2nd bit group, 2nd bit group, 4th bit group, 1st bit group, 8th bit group, 0th bit group. 4. The method according to claim 1, wherein if the codeword is 16200 and the number of information bits is 7200, the predetermined order is as follows: 18th bit group, 17th bit group, 16th bit group, 15- 14th bit group, 14th bit group, 13th bit group, 12th bit group, 11th bit group, 4th bit group, 10th bit group, 9th bit group, 8th bit group, 3rd bit group, 2nd bit group, 7th bit group, 6th bit group, 5th bit group, 1st bit group, 19th bit group, 0th bit group. 5. The method according to claim 1, containing stages in which
when the number of bits of each bit group is 360 and the number of information bits is 3240,
determining that all information bits in the bit groups from the 0th bit group to the (m-1) th bit group in a predetermined order are reduced, and
determining that the (3240-K ₂ -360m) information bits to m-th bit groups in a predetermined order cut,
where K ₂ is the number of information bits to be obtained by reduction, (3240-K ₂ ) is the number of information bits to be reduced, and
$$m=\lfloor \frac{3240-K_2}{360}\rfloor .$$

6. The method according to claim 1, containing stages in which,
when the number of bits of each bit group is 360, and the number of information bits is 7200,
determining that all information bits in the bit groups from the 0th bit group to the (m-1) th bit group in a predetermined order are reduced, and
determine that (7200-K ₂ -360m) information bits in the m-th bit group in a predetermined order are reduced,
where K ₂ is the number of information bits to be obtained by reduction (7200-K ₂₎ is the number of information bits that need to be cut, and
$$m=\lfloor \frac{7200-K_2}{360}\rfloor .$$

7. A device for channel decoding in a system using a low density parity check code (LDPC), comprising
a demodulator for demodulating the received signal,
an abbreviation structure determiner for determining the position of the abridged information bits, and
a decoder for decoding the demodulated signal, taking into account the specific position of the reduced information bits,
moreover, the determination of the position of the reduced information bits contains
dividing information bits into multiple bit groups,
determination of the number of reduced information bits,
determining the number of abbreviated bit groups based on a certain number of information bits to be abbreviated, and
definition of abbreviated bit groups based on a given order. 8. The device according to claim 7, in which the determinant of the structure of the reduction is configured to determine the number of information bits to be obtained by reduction, to determine the number of information bits that should be reduced. 9. The device according to claim 7, and if the length of the code word is 16200 and the number of information bits is 3240, the specified order is as follows: 7th bit group, 3rd bit group, 6th bit group, 5th bit group, 2nd bit group, 4th bit group, 1st bit group, 8th bit group, 0th bit group. 10. The device according to claim 7, and if the codeword length is 16200 and the number of information bits is 7200, the specified order is as follows: 18th bit group, 17th bit group, 16th bit group, 15th bit group, 14th bit group, 13th bit group, 12th bit group, 11th bit group, 4th bit group, 10th bit group, 9th bit group, 8th bit group , 3rd bit group, 2nd bit group, 7th bit group, 6th bit group, 5th bit group, 1st bit group, 19th bit group, 0th bit group. 11. The device according to claim 7, wherein when the number of bits of each bit group is 360 and the number of information bits is 3240, the abbreviation structure determiner determines that all information bits in the bit groups from the 0th bit group to (m-1) the ith bit group in a predetermined order is reduced, and (3240-K ₂ -360m) information bits in the m-th bit group in a predetermined order are reduced,
where K ₂ is the number of information bits to be obtained by reduction, (3240-K ₂ ) is the number of information bits to be reduced, and
$$m=\lfloor \frac{3240-K_2}{360}\rfloor .$$

12. The device according to claim 7, wherein when the number of bits of each bit group is 360 and the number of information bits is 7200, the abbreviation structure determiner determines that all information bits in the bit groups from the 0th bit group to (m-1) the ith bit group in a predetermined order is reduced, and the (7200-K ₂ -360m) information bits in the m-th bit group in a predetermined order are reduced,
where K ₂ is the number of information bits to be obtained by reduction, (7200-K ₂ ) is the number of information bits to be reduced, and
$$m=\lfloor \frac{7200-K_2}{360}\rfloor .$$

Images