RU2451987C1 - Apparatus for counting index numbers of high bits in data line - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus has n=2^k binary inputs of data line bits, where k is a positive integer, n outputs of the values of index numbers high bits in a data line, a POCCNT output of the number of high bits in a data line, n AND elements, each having an output Y, a first input X1 and a second input X2, and generates at output Y the product of X1 and X2, computing units M_ij, having adders and forming a hierarchical structure with k processing levels, where the index j varies from 1 to k=log₂n and indicates the number of the processing level, and index i varies from 1 to 2^j-1 and indicates the number of the unit on the level.

EFFECT: simplification of the apparatus while maintaining high speed of performing operations.

7 cl, 7 dwg

Description

The device relates to the field of information processing and can be used in computer technology, communication systems and information protection from unauthorized access.

соединен с r-м выходом сумматора, отличающийся тем, что содержит p мажоритарных элементов (p [n/2]), s-й которых

имеет порог, равный 2s, i-й вход

сумматора соединен с i-м входом первого элемента сложения по модулю два и 1-м входом s-го мажоритарного элемента, t-й вход j-го элемента сложения по модулю два

,

,

соединен с выходом мажоритарного элемента с порогом t∙2^j-1, (k+1)-й выход сумматора соединен с выходом мажоритарного элемента с порогом 2^k _. Known multi-input single-digit adder (US Pat. No. 2047216 Russia, G06F 7/50. Multi-input single-digit adder). A multi-input single-bit adder contains K modulo two addition elements (K [log ₂ n] n bit depth of the input binary word), the output of the rth of which

connected to the rth output of the adder, characterized in that it contains p majority elements (p [n / 2]), the s-th of which

has a threshold equal to 2s, i-th input

the adder is connected to the i-th input of the first addition element modulo two and the 1st input of the s-th majority element, the t-th input of the jth addition element modulo two

,

,

connected to the output of the majority element with a threshold t ∙ 2 ^j-1 , the (k + 1) -th output of the adder is connected to the output of the majority element with a threshold of 2 ^k _.

This multi-input single-bit adder can be used to calculate serial numbers of bits with a high logical level in a data string of length n. But for parallel processing, it is necessary to use n multi-input single-digit adders, while the total number of adders used in the device is O (n ² ).

The disadvantage of this solution is a significant complication of the circuit with parallel processing. When using sequential processing, in which each serial number is sequentially calculated using a single multi-input single-bit adder, the calculation time of the serial numbers of bits with a high logical level increases significantly.

A known method and apparatus for counting the number of bits with a high logical level (US Pat. No. 5541865 USA, G06F 7/60, 007/50. Method and apparatus for performing a population count operation). A device for calculating the number of bits with a high logical level of a data element includes: a first set of adders with conservation of transfer, consisting of the first, second, third and fourth adders, the inputs of which are connected to the inputs of the device so as to obtain the first, second, third and the fourth bit parts of the first data element, respectively, the first and second adders with saving transfer form the first multi-bit data block at their outputs, and the third and fourth adders with saving transfer pho second second multi-bit data block is outputted at its outputs; the second set of adders, consisting of the fifth and sixth adders with transfer conservation, the inputs of which are connected so as to obtain the first and second multi-bit data blocks, respectively, the fifth and sixth adders with transfer conservation form at their outputs a third multi-bit data block; a seventh adder with saving transfer, the inputs of which are connected so as to obtain a third multi-bit block of output data, which forms at its outputs a fourth multi-bit block of data; full adder, the inputs of which are connected in such a way as to obtain a fourth multi-bit data block, which generates at its outputs the number of bits with a high logical level. Each adder with conservation transfer is a 4-2 adder with conservation transfer. The full adder is a four-bit full adder.

This device can be used to calculate serial numbers of bits with a high logical level in a data string of length n. But for parallel processing, it is necessary to use n devices for counting the number of bits with a high logical level, while the total number of adders used is O (n ² ).

The disadvantage of this solution is a significant complication of the circuit with parallel processing. When using sequential processing, the calculation time of serial numbers of bits with a high logical level is significantly increased.

A device for calculating the number of bits with a high logical level (US Pat. No. 6754685 USA, G06F 5/01, 7/60, 007/00. Dynamic popcount / shift circuit). The device performs the function of calculating the number of bits with a high logical level of the input data string and the data shift function. The method underlying the operation of the device provides a balance between the load of counters of the number of bits with a high logical level and data shift schemes. This leads to an increase in the speed of the operation. The device has inputs for the bits of the first vector, the second vector, means for calculating the number of bits with a high logical level of the first vector, means for shifting the set of bits of the second vector based on the results of calculating the number of bits with a high logical level of the first vector, means for generating the third vector resulting from a shift operation. The device consists of many dynamic levels, followed by static levels. At dynamic levels, dynamic nodes are used that calculate values depending on the individual bits of the pointer and a sparse vector. The device is expanded by repeating the basic scheme, so it can be changed in accordance with the size of the pointer and the sparse vector.

This device can be used to calculate serial numbers of bits with a high logical level in a data string of length n. But for parallel processing, it is necessary to use n devices for counting the number of bits with a high logical level, while the hardware complexity of the device is O (n ² ).

The disadvantage of this solution is a significant complication of the circuit with parallel processing. When using sequential processing, the calculation time of serial numbers of bits with a high logical level increases significantly.

A device and method are known for calculating the number of bits with a high logical level (US Pat. No. 5717616 USA, G06F 7/60, 017/00 Computer hardware instruction and method for computing population counts). The device is designed to calculate the number of bits with a high logical level in long strings. In this case, the entire line is divided into smaller parts and for each of the parts the number of bits with a high logical level is calculated. To speed up the operation, adders are used with saving transfer. The device consists of a data register containing a string of bits in which the number of bits with a high logical level, a set of full adders, each of which has an output, is calculated, and sums the bits with a high logical level from a unique set of bits from a data register, a set of adders with transfer preservation , each of which has an output, and sums the bits with a high logic level from a unique set of bits from the accumulation register. Each of the adders with transfer preservation forms a unique set of output data in the destination register, where the destination register stores the number of bits with a high logical level from a subset of bits of the data register and a group of bits from the accumulating register in the sum format with transfer preservation. Many complete adders form a hierarchical structure so that the first level of adders calculates the number of bits with a high logical level stored in the data register. The inputs of the full second-level adders are connected to the outputs of the first-level adders so that each of the second-level adders adds the results at the outputs of two first-level adders, and each of the outputs of the first-level adder is connected to one input of the second-level adder. The number of full adders of the first level is half the number of bits in the data register, the number of full adders in the second level is a quarter of the number of bits in the data register. Adders with saving transfer sum the same number of bits. The role of the destination register and the accumulating register is performed by the same register.

This device can be used to calculate serial numbers of bits with a high logical level in a data string of length n. But for parallel processing, it is necessary to use n devices for counting the number of bits with a high logical level, while the total number of adders used is O (n ² ).

The disadvantage of this solution is a significant complication of the circuit with parallel processing. When using sequential processing, the calculation time of serial numbers of bits with a high logical level increases significantly.

The objective of this solution is to develop a simple device with the number of adders used no more than O (n) for calculating the values of the serial numbers of bits and the total number of bits with a high logical level in a data string of length n bits, providing high performance due to parallel data processing.

The technical result is to reduce the number of adders used in the device to 5 / 2n-2log ₂ (n) -2 while maintaining a high speed of operation.

The problem is achieved in that the device for calculating the serial numbers of bits with a high logical level in the data string, according to the solution, contains n = 2 ^k binary inputs of bits of the data string Db ₁ , Db ₂ , ..., Db _n , where k is a positive integer , n outputs Q ₁ , Q ₂ ,..., Q _n values of serial numbers of bits with a high logical level in the data string, output POPCNT of the number of bits with a high logical level in the data string, n logical multiplication elements AND ₁ , AND ₂ ..., AND _n, each of which has a Y output, the first input X1 and a second binary input X2 and forms uet output Y output data of multiplication by the X1 inputs and X2 computing units M _ij, forming a structure with k treatment levels, where the index j runs from 1 to k = log ₂ n and indicates processing level number, i the index runs from 1 to 2 ^l-1 and indicates the block number at level j, each block M _ij has an input I_NUM1 of summation results from the lower level and output O_NUM2 of summation results, each block M _ij , where j = 2, ..., k, i = 1, 2 , ..., 2j ^-1 additionally has an input I_NUM2 of the summation results from the lower level and an output O_NUM of the summation results transmitted to the upper level, each block M _ij , where j = 2, ..., k, i = 2, 3, ..., 2 ^j-1 additionally has input I_NUM of the summation results from the upper level and output O_NUM1 of the summation results, block M _{l, k} additionally has the output O_NUM1 of the summation results, the block M _{n / 2, k} additionally has the output I_NUM2 of the summation results, while the block M _{ij has} level j, where j = 1, 2, ..., k-1, i = 1, 2 ,. ..., 2 ^j-1 , output O_NUM1 is connected to input I_NUM of block M _{2i-1, j + 1} output O_NUM2 is connected to input I_NUM of block M _{2ij + 1} input I_NUM1 is connected to output O_NUM of block M _{2ij + 1} , input I_NUM2 is connected to output O_NUM of block M _{2ij + 1} for blocks M _{i, k of the} last level k, where e k = log ₂ n, i = 1, 2, ..., 2 ^k-1 output O_NUM1 is connected to the first input X1 of the logic element And _2i-1 input I_NUM1 is connected to the input Db _{2i-1 of the} device and the second binary input X2 of the logic element And _2i-1 , the output of the logic element And _{2i-1, is} connected to the output Q _{2i-1 of the} device, the output O_NUM2 of the block M _{i, k is} connected to the first input X1 of the logic element And _2i , the input I_NUM2 of the block M _{i, k is} connected to the input Db _2i devices and the second binary input X2 of the logic element AND _{2i, the} output of the logic element And _{2i is} connected to the output Q _2i , devices, the output O_NUM2 of the block M _{n / 2, k is} additionally connected to the output POPCNT devices. At block M _11, input I_NUM1 is connected to output O_NUM2. Each block of the intermediate level M _{i, j} , where j = 2, ..., k-1, i = 2 ^jl , includes an adder with the first I1 and second I2 inputs, and the output OU, and the input of the block I_NUM1 is connected to the first input the adder I1, the input I_NUM is connected to the second input of the adder I2 and with the output O_NUM1, the output O_NUM2 is connected to the output OU of the adder. Each block M _lj , where j = 2, ..., k-1 includes an adder with the first I1 and second I2 inputs and an OU output, with the input I_NUM1 connected to the first input of the adder I1 and the output O_NUM2, the input I_NUM2 connected to the second input of the adder I2, the output O_NUM is connected to the output OU of the adder. Block M _{1, k} includes an adder with first I1 and second I2 inputs and an OU output, with input I_NUM1 connected to the first input of adder I1 and output O_NUM1, input I_NUM2 connected to the second input of adder I2, output O_NUM connected to output OU adder and with output O_NUM2. Each block M _{i, k of the} last level k, where i = 2, ..., n / 2, consists of three adders, each of which has the first I1 and second I2 inputs, and the output OU, and the input I_NUM1 is connected to the first inputs I1 of the first and second adders, input I_NUM2 is connected to the second input I2 of the first adder, input I_NUM is connected to the second input I2 of the second adder and the first input I1 of the third adder, the output OU of the first adder is connected to the second input I2 of the third adder and to the output O_NUM, if any , the output O_NUM1 is connected to the OU output of the second adder, the output O_NUM2 is connected to the OU t output a third adder. Each block of the intermediate level M _{i, j} , where j = 2, ..., k-1, i = 2, 3, ..., 2 ^j-1 -1 consists of two adders having the first I1 and second I2 inputs, and OU output, with input I_NUM1 connected to the first inputs I1 of the first and second adders, input I_NUM2 connected to the second input I2 of the first adder, input I_NUM connected to the second input I2 of the second adder and output O_NUM1, output O_NUM connected to the output OU of the first adder, output O_NUM2 is connected to the OU output of the second adder.

The invention is illustrated by drawings, where Fig. 1 shows a structural-functional diagram of a device for calculating serial numbers of bits with a high logical level in a data string of length n = 8, Fig. 2 shows a block diagram of M _{i, k of the} last conversion level k, where k = log ₂ n, i = 2, 3, ..., 2 ^k-1 , figure 3 shows the block diagram of the intermediate level M _{s, t} , where 1 <t <k, a 1 <s <2 ^t-1 , figure 4 shows the block diagram M _{1, m} , where 1 <m <k, figure 5 shows the block diagram M _pq , where q = 2, ..., k-1, p = 2 ^q-1 , figure .6 shows a block diagram of M _{1, k} , Fig. 7 shows a block diagram of M _{n / 2, k} , where

M ₁₁ - the first block of the first level;

M ₁₂ , M ₂₂ - the first and second blocks of the second level;

M ₁₃ , M ₂₃ , M ₃₃ , M ₄₃ - the first, second, third and fourth blocks of the third level;

And ₁ - And ₈ - logical elements And;

X1 - the first input of the logical element And;

X2 - the second binary input of the logical element And;

Y is the output of the AND gate;

O_NUM - output of the summation results transferred to the upper level;

O_NUM1, O_NUM2 - the first and second outputs of the summation results transmitted to the lower level;

I_NUM - input of summation results from the top level;

I_NUM1, I_NUM2 - the first and second inputs of the summation results from the lower level;

Q ₁ , Q ₂ , Q ₃ , Q _4, Q ₅ , Q ₆ , Q ₇ , Q ₈ - outputs of the values of serial numbers of bits with a high logical level;

Db ₁ , Db ₂ , Db ₃ , Db ₄ , Db ₅ , Db ₆ , Db ₇ , Db ₈ - binary inputs of bits of the input data string;

POPCNT - output of the sum of bits with a high logical level;

ADD - adder;

I1, I2 - inputs of the adder;

OU - adder output.

In the General case, the proposed device has n binary inputs for receiving bits of the input data string, n outputs of the results of calculating the serial numbers of bits with a high logical level, the output of the results of calculating the number of bits with a high logical level. The proposed device contains computing blocks M _{i, j} forming a pyramidal structure with k = log ₂ n processing levels, with the index i changing from 1 to 2 ^j-1 and indicating the block number at the level, and the index j changing from 1 to k and indicating processing level number. Thus, at the first level (j = 1) there is a single block M ₁₁ , at the second level there are two blocks, at the third - four and so on to the last level (j = k) containing n / 2 blocks. The device also contains n logical multiplication elements AND ₁ , AND _{2 ...} , AND _n , each of which has an output Y, a first input X1 and a second binary input X2, while the number at the output Y is equal to the number at the input X1, if the input X2 is high logic level, if input X2 has a low logic level, then the number at output Y is zero.

Blocks M _{i, j} are divided into seven types.

1. Block M ₁₁ has an input I_NUM1 and an output J_NUM2, which are interconnected.

The remaining blocks consist of adders ADD, each of which has the first I1 and second I2 inputs for supplying the summed numbers and the output OU, on which the sum of the numbers supplied to the inputs I1 and I2 is formed.

2. Blocks M _{i, k of the} last level of transformation k, where k = log ₂ n, i = 2, 3, ..., 2 ^kl -1 consist of three adders ADD. The block diagram of M _{i, k is} shown in figure 2. Blocks М _{i, k} have the output of the summation results transmitted to the upper level O_NUM, the first O_NUM1 and the second O_NUM2 outputs the summation results transferred to the lower level, the input I_NUM of the summation results from the upper level, the first I_NUM1 and the second I_NUM2 inputs of the summation results from the lower level. The input I_NUM1 of the block M _{i, k is} connected to the first input I1 of the first adder and to the second input I2 of the second adder. The input I_NUM2 of the block M _{i, k is} connected to the second input I2 of the first adder. The input I_NUM of the block M _{i, k is} connected to the second input I2 of the second adder and to the first input I1 of the third adder. The output O_NUM of the block M _{i, k is} connected to the output OU of the first adder and to the second input I2 of the third adder. The output O_NUM1 of the block M _{i, k is} connected to the output OU of the second adder. The output O_NUM2 of the block M _{i, k is} connected to the output OU of the third adder. In figure 1, the blocks M ₂₃ , M ₃₃ correspond to the description of the block M _{i, k} , a diagram of which is presented in figure 2.

3. Blocks M _{s, t of the} intermediate level of transformation t, where 1 <t <k, and 1 <s <2 ^t-1 consist of two adders ADD. The block diagram M _{s, t is} shown in Fig.3. Blocks M _{s, t} have the output of the summation results transferred to the upper level O_NUM, the first O_NUM1 and the second O_NUM2 outputs the summation results transferred to the lower level, the input I_NUM of the summation results from the upper level, the first I_NUM1 and the second I_NUM2 inputs of the summation results from the lower level. The input I_NUM1 of the block M _{s, t is} connected to the first input I1 of the first adder and to the first input I1 of the second adder. The input I_NUM2 of the block M _{s, t is} connected to the second input I2 of the first adder. The input I_NUM of the block M _{s, t is} connected to the second input I2 of the second adder and the output O_NUM1 of the block MM _{s, t} . The output O_NUM of the block M _{s, t is} connected to the output OU of the first adder. The output O_NUM2 of the block M _{s, t is} connected to the output OU of the second adder. Figure 1 does not depict blocks that correspond to the description of blocks M _{s, t} , the scheme of which is presented in figure 3, since these blocks appear when the length of the input data string n is more than eight bits.

4. Blocks M _{1m of the} intermediate conversion level m, where 1 <m <k consist of one adder ADD. The block diagram of M _1m shown in figure 4. Blocks M _{1, m} , have the output of the summation results transmitted to the upper level O_NUM, the output O_NUM2 of the summation results transferred to the lower level, the first I_NUM1 and the second I_NUM2 inputs of the summation results from the lower level. The input I_NUM1 of the block M _{1, m is} connected to the first input I1 of the adder and with the output O_NUM2. The input I_NUM2 of the block M _{1, m is} connected to the second input I2 of the adder. The output O_NUM of the block M _{1, m is} connected to the output OU of the adder. In figure 1, the block M _I2 correspond to the description of the block M _1m , a diagram of which is presented in figure 4.

5. Blocks M _{p, q of the} intermediate level of transformation q, where 1 <q <k, p = 2 ^q-1 consist of one adder ADD. The block diagram M _{p, q is} shown in Fig.5. Blocks M _{p, q} have the first O_NUM1 and second O_NUM2 outputs of the summation results transmitted to the lower level, the input of the summation results from the lower level I_NUM1, the input I_NUM of the summation results from the upper level. The input I_NUM1 of the block M _{pq is} connected to the first input I1 of the adder. The input I_NUM of the block M _{p, q is} connected to the second input I2 of the adder and the output O_NUM1 of the block M _{p, q} . The output O_NUM2 of the block M _{pq is} connected to the output OU of the adder. In figure 1, the block M ₂₂ correspond to the description of the block M _{p, q} , a diagram of which is presented in figure 5.

6. Block M _{1, k of the} last conversion level k, where k = log ₂ n, consists of one adder ADD. The block diagram of M _{1, k is} shown in Fig.6. Block M _{1, k} has the output of the summation results transmitted to the upper level O_NUM, the first O_NUM1 and the second O_NUM2 the outputs of the summation results transmitted to the lower level, the first I_NUM1 and the second I_NUM2 inputs of the summation from the lower level. Input I_NUM1 of block M _{1, k is} connected to the first input I1 of the adder of block M _{1, k} and with output O_NUM1 of block M _{1, k} . The input I_NUM2 of the block M _{1, k is} connected to the second input I2 of the adder of the block M _{1, k} . The output O_NUM of block M _{1, k is} connected to the output OU of the adder of block M _{1, k} and with the output O_NUM2 of block M _{i, k} . In figure 1, the block M ₁₃ corresponds to the description of the block M _{1, k} , a diagram of which is presented in Fig.6.

7. Block M _{n / 2, k of the} last level of transformation k, where k = log ₂ n, consists of three adders ADD. The block diagram of M _{n / 2, k is} shown in Fig.7. Block M _{n / 2, k} has the first O_NUM1 and second O_NUM2 outputs of the summation results transmitted to the lower level, the input I_NUM of the summation results from the upper level, the first I_NUM1 and the second I_NUM2 inputs of the summation results from the lower level. The input I_NUM1 of the block M _{n / 2, k is} connected to the first input I1 of the first adder and to the first input I1 of the second adder. Input I_NUM2 of the block M _{n / 2, k is} connected to the second input I2 of the first adder. The input I_NUM of the block M _{n / 2, k is} connected to the second input I2 of the second adder and to the first input I1 of the third adder. The output OU of the first adder of the block M _{n / 2, k is} connected to the second input I2 of the third adder. The output O_NUM1 of the block M _{n / 2, k is} connected to the output OU of the second adder. The output O_NUM2 of the block M _{n / 2, k is} connected to the output OU of the third adder. In figure 1, the block M ₄₃ corresponds to the description of the block M _{n / 2, k} , a diagram of which is presented in figure 7.

The connections between the units of the device are as follows.

If the block М _{p, m is} level m, where m = 1, 2, ..., k-1; p = 1, 2, ..., 2 ^m-1 there is an output O_NUM1, then it is connected to the input I_NUM of the block M _{2p-1, m + 1 of} level m + 1. The output O_NUM2 of the block M _{p, m of} level m is connected to the input I_NUM of the block M _{2p, m + 1 of} level m + 1. The input I_NUM1 of the block M _{p, m of} level m is connected to the output O_NUM of the block M _{2p-1, m + 1 of} level m + 1, if the block M _{p, m of} level m has an input I_NUM2, then it is connected to the output O_NUM of the block M _{2p, m + 1} level m + 1. The output O_NUM1 of each block M _{i, k of the} last level k, where k = log ₂ n, ai = 1, 2, ..., 2 ^{k-1 is} connected to the first input X1 of the logic element And _2i-1 , input I_NUM1 of the block M _{i, k is} connected to the input Db _{2i-1 of the} device and the second binary input X2 of the logic element And _2i-1 , the output of the logic element And _{2p-1 is} connected to the output Q _{2p-1 of the} device, the output O_NUM2 of the block M _{i, k of the} last level k, where k = log ₂ n, i = 1, 2, ..., 2 ^kl , connected to the first input X1 of the logic element And _2i , the input I_NUM2 of the block M _{i, k is} connected to the input Db _{2i of the} device and the second binary input X2 of the logical element And _2i , logic element output And _2i connected to the output Q _{2i of the} device. The output O_NUM2 of the block M _{n / 2, k is} additionally connected to the output POPCNT of the sum of bits with a high logic level in the input line of this device.

The device operates as follows. The binary inputs Db ₁ , Db ₂ ,..., Db _{n of the} device for calculating the serial numbers of bits with a high logical level receive the bits of the input data string. After a delay time t ₃ at the outputs Q ₁ , Q ₂ ,..., Q _n , the device displays the values of serial numbers of bits with a high logical level in the input data line. The speed of the operation depends on the type of adders used. If the adder delay does not depend on the number of digits to be summed and is equal to τ, the delay t _{3 of} execution by the proposed device for calculating the serial numbers of bits with a high logical level is t _s = 2τ (log ₂ (n) -1). The delay in generating the result at the output of POPCNT is also equal to t _s .

In the blocks M _{i, j} , adders with conservation of transfer, adders with through transfer, adders with accelerated transfer and other adders described, for example, in the book of Jean M. Rabai, Ananta Chandrakasan, Borivozh Nikolic, can be used. Digital integrated circuits. Design methodology. M .: Williams, 2007, 912 p. When calculating the serial numbers of bits with a high logical level in the n bit row of data, schemes are used to sum the input data with the number of bits from 1 to log ₂ n.

In blocks M _{i, j} adders can be used, summing the input data modulo 2. In this case, the device determines the parity or oddness of the serial number of bits with a high logical level in the data line. In the general case, if adders summing the input data modulo d are used in blocks M _{i, j} , serial numbers of bits with a high logical level in the data line will also be computed modulo d.

The number of bits of the summed values in blocks is different. The block M _{p, m is} level m, where m = 1, 3, ..., k; p = 1, 2, ..., 2 ^m-1 output O_NUM1 has the number of binary digits equal to int (log ₂ (p)) + k-m + 1, where the function int (log ₂ (p)) calculates the nearest integer greater than log ₂ (p), and the outputs O_NUM2 and O_NUM have the number of binary bits equal to int (log ₂ (p)) + k-m + 2. Thus, the last adder of the last level, which forms the result at the output O_NUM2, has k + 1 bit. The block M _{p, m is} level m, where m = 1, 3, ..., k; p = 1, 2, ..., 2 ^m-1 inputs I_NUM1, I_NUM2 have the number of binary digits equal to k-m + 1. In blocks M _{p, m,} you can use the same adders with the number of bits of the summed numbers equal to k, but at the same time part of the highest bits of the part of the adders will not be used.

Note that the device can be used with values of the input data string length n different from the power of the number 2. In this case, only part of the blocks to which the bits of the input data string are sent are used. Unused blocks and logic elements And _i can be excluded from the device.

Thus, the device calculates the serial numbers of bits with a high logical level of the input binary data string. Simultaneously with the calculation of the serial numbers of bits, the device calculates the number of bits with a high logical level in the input data line. The device is characterized by a small number of adders used. The hardware complexity of the device, determined by the number of adders used, is 5 / 2n-2log ₂ (n) -2, where n is the number of bits of the input data string. This is significantly less than the number of adders needed to calculate the serial numbers of bits with a high logical level using n devices for calculating the number of bits with a high logical level. Data processing in the proposed device is performed in parallel, which provides a high speed operation.

Claims (7)

1. Device for calculating the serial numbers of bits with a high logical level in the data string, characterized in that it contains n = 2 ^k binary inputs of bits of the data string Db ₁ , Db ₂ , ..., Db _n , where k is a positive integer, n outputs Q ₁ , Q ₂ , ..., Q _n values of serial numbers of bits with a high logical level in the data line, output POPCNT of the number of bits with a high logical level in the data line, n logical multiplication elements AND ₁ , AND ₂ , ..., AND _n , each of which has an output Y, the first input X1 and the second binary input X2, and forms the result at the output Y multiplying the data at inputs X1 and X2, computational units M _q forming a structure with k processing levels, where the index j varies from 1 to k = log ₂ n and indicates the number of the processing level, and the index i varies from 1 to 2 ^j-1 and indicates the block number at level j, each block M _ij has an input I-NUM1 of summation results from the lower level and output 0-NUM2 of summation results, each block M _{i, j} , where j = 2, ..., k, i = 1, 2 , ..., 2 ^ji -1 additionally has an input I-NUM2 of the summation results from the lower level and an output O-NUM of the summation results transmitted to the upper level, each block M _{i, j} where j = 2, ..., k, i = 2, 3, ..., 2 ^j-1 additionally has an input I-NUM of the summation results from the upper level and an output O-NUM1 of the summation results, block M _{1, k} additionally has an output O -NUM1 of the summation results, the block M _{n / 2, k} additionally has an output I-NUM2 of the summation results, while the block M _{ij has} level j, where j = 1, 2, ..., k-1, i = 1, 2, ... , 2 ^j-1 , the output O-NUM1 is connected to the input I-NUM of the block M _{2i + 1} , _{j + i} , the output O-NUM2 is connected to the input I-NUM of the block M _2i , _{j + i} , the input I-NUM1 is connected to the output of the O-NUM block M _{2i-1, j + i} , the input I-NUM2 is connected to the output O-NUM of the block M _{2i, j + 1} , the blocks M _{i, k of the} last level k, where k = log ₂ n, i = 1, 2, 2 ^k-1, O-NUM1 output is connected to the first input X1 AND gate _2i-1, I-NUM1 input coupled to the input Db _2i-i devices and second binary input X2 of the AND gate _2i-1, the NAND gate output of AND _{2i-1 is} connected to the output Q _{2i-1 of the} device, the output O-NUM2 of the block M _{i, k is} connected to the first input X1 of the logic element And _2i , the input I-NUM2 of the block M _{i; k is} connected to the input Db _{2i of the} device and the second binary input X2 of the logic element AND _2i , the output of the logic element AND _{2i is} connected to the output Q _{2i of the} device, the output O-NUM2 of the block M _{n / 2, k is} additionally connected to the output POPCNT of the device. 2. The device according to claim 1, characterized in that the block M ₁₁ input I-NUM1 is connected to the output O-NUM2. 3. The device according to claim 1, characterized in that each block of the intermediate level M _{i, j} , where j = 2, ..., k-1, i = 2 ^j-1 , includes an adder with the first I1 and second I2 inputs and an OU output, wherein the input of I-NUM1 is connected to the first input of the adder I1, the I-NUM input is connected to the second input of the adder I2 and the output O-NUM1, the output O-NUM2 is connected to the output OU of the adder. 4. The device according to claim 1, characterized in that each block M _{i, j} , where j = 2, ..., k-1 includes an adder with the first I1 and second I2 inputs and output OU, and the input I-NUM1 is connected with the first input of the adder I1 and with the output O-NUM2, the input I-NUM2 is connected to the second input of the adder I2, the output O-NUM is connected to the output OU of the adder. 5. The device according to claim 1, characterized in that the block M _{1, k} includes an adder with a first I1 and second I2 inputs and an OU output, the input I-NUM1 being connected to the first input of the adder I1 and with the output O-NUM1, the INUM2 input is connected to the second input of the adder I2, the O-NUM output is connected to the OU output of the adder and to the O-NUM2 output. 6. The device according to claim 1, characterized in that each block M _{i, k of the} last level k, where i = 2, ..., n / 2, consists of three adders, each of which has first I1 and second I2 inputs, and OU output, with input I-NUM1 connected to the first inputs I1 of the first and second adders, input I-NUM2 connected to the second input I2 of the first adder, input I-NUM connected to the second input I2 of the second adder and the first input I1 of the third adder, output The OU of the first adder is connected to the second input I2 of the third adder and to the output O-NUM, if any, the output O-NUM1 is connected to the output OU of the second of the adder, the O-NUM2 output is connected to the OU output of the third adder. 7. The device according to claim 1, characterized in that each block of the intermediate level M _{i, j} , where j = 2, ..., k-1, i = 2, 3, ..., 2 ^j-1 -1, consists of two adders having first I1 and second I2 inputs and output OU, the input I-NUM1 connected to the first inputs I1 of the first and second adders, the input I-NUM2 connected to the second input I2 of the first adder, the input I-NUM connected to the second input I2 of the second the adder and with the output O-NUM1, the output O-NUM is connected to the output OU of the first adder, the output O-NUM2 is connected to the output OU of the second adder.

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