RU2423007C1 - Determined communications system - Google Patents

Abstract

FIELD: information technologies. ^ SUBSTANCE: method to control a communications system (1) of audio data transfer between each of large quantity of terminal units, includes inspection of specified terminal units (T; T1, T2, T3) identification by the specified central unit (10) during the initialisation phase, transfer of the specified data frames containing the first synchronising signal (51), a terminal address (52) of the appropriate terminal unit (T; T1, T2, T3), a field (54) of information content and the second synchronising signal (51), by the specified central unit (10) via the specified main bus (14) during the configuration phase and sending of audio data via the specified data bus (12) by one of specified several terminal units (T; T1, T2, T3) within that time interval between sample captures of audio signal, which corresponds to the interval between the specified first synchronising signal and the specified second synchronising signal. ^ EFFECT: development of a communications protocol with ultimate low losses of throughput capacity and a system for its realisation. ^ 13 cl, 8 dwg

Description

The invention relates to a deterministic communication system, namely, although not exclusively, to aeronautical electronic systems.

The system according to the invention can be used on any type of aircraft, in particular aircraft. In general, the invention may find application in real-time systems, i.e. systems of strictly time-limited communication, and also allows you to highlight those functions of the system, the implementation of which depends on the timely exchange of data.

It is known to provide a physical layer due to point-to-point connection of intermediate modules for distributed access to the bus in accordance with Ethernet technology. Bus access is determined using the well-known CSMA / CD method (multiple access with carrier control and collision resolution). However, such a system is not applicable in real time, since it can be self-locking and not be time-determined.

From the documents DE 3424866 C2 and DE 3426893 A1, a system is known containing only one common bus for all participants with a configurable order and a number of time slots for connected stations or terminal blocks. In these systems, first of all, initialization and request phases are created, during which the necessary configuration of stations is determined. In this way, time windows for data transmission can be dynamically allocated.

Authors Hammond Joseph, L.O. Reilly Peter, “Analysis of the effectiveness of local computer networks,” Scientific Readings, Massachusetts, USA, Addison-Wesley Inc. Publishing Company, 1986, pp. 193-196; ISBN 0-201-1 1530-1 describes a network with ordered polling, containing a central computer, with the help of which each station or station in the network is polled in a given sequence to provide access to the channel. A network with ordered polling works either in a circular polling mode or in a polling mode of the “ready to transmit first” type. In a circular polling, the central computer initiates a polling sequence by sending a polling message to the selected station. After the data transfer is completed by that first selected station, the central computer continues to work with the next selected station and so on. In the “ready-to-send first” type of interrogation, the central computer sends an interrogation message to the initial station and, upon completion of data transfer by the initial station, the interrogation automatically proceeds to the next station without the participation of the central computer.

However, the disadvantage of the prototype is the fact that time-out periods are inevitable in the system, since it is necessary to apply individually to each terminal block in order to then ensure data transfer. The total waiting time consists of the response time of the terminal blocks, confirmation of the transfer of the terminal address and the delay time of the bus itself, depending on the physical length of the line.

An object of the present invention is to provide a communication protocol with extremely low bandwidth losses and a system for its implementation.

This problem is solved by a communication system for transmitting audio data between each of a large number of terminal blocks and a control method of the aforementioned system according to claims 1 and 9, respectively. The dependent claims are preferred embodiments of the invention.

In accordance with the invention, there is provided a digital communication system comprising several terminal blocks and a central unit. These terminal blocks are connected to the data bus. The communication process on the bus between the terminal blocks is controlled by the specified central unit. The communication system described above has been improved with an optional bus. Accordingly, the terminal blocks are connected to the central unit via the main bus and the data bus. On the main bus, the central unit transmits exclusively commands to the terminal blocks. Therefore, the central unit is only a transmitter to the main bus. However, data from the central unit to the terminal units can also be transmitted on the main bus. On the data bus, each terminal block can transmit data to the central block. Therefore, the central unit is only a receiver on the data bus. Access to the data bus of the terminal blocks is controlled by the central unit via the main bus. If data is to be transmitted from one terminal block to another receiving terminal block, this should be done using the central block. For this purpose, the clipboard is used in the central unit to mirror and transmit the received data.

So, the central unit operates as a control device or controller or control unit for access to the data bus through any of the system modules. The data bus uses a time division multiplexing system with a double communication line. This time division multiplexing system is preferably based on the Ethernet standard for the physical layer of two separate buses. The system is intended for use in aviation electronics, namely in aircraft devices.

According to one embodiment of the invention, there is provided a method for controlling a communication system for exchanging audio data between any of the terminal blocks. The specified communication system contains:

a large number of terminal blocks for buffering audio data;

a main bus for transmitting control signals to said terminal units;

a data bus for transmitting audio data from said terminal blocks;

a central unit requesting audio data from said terminal blocks via said main bus and receiving audio data from said data bus.

The specified method is characterized in that it contains the following steps:

verification of the identification of these terminal blocks using the Central unit during the identification phase;

transmitting a given data frame, including the first synchronization signal, the address of the corresponding terminal block, the content field and the second synchronization signal, using the central unit through the main bus during the configuration phase and transmitting audio data through the data bus by one of the terminal blocks within the time interval between samples of the audio signal, which corresponds to the interval between the first synchronization signal and the second synchronization signal.

In a preferred embodiment of the method according to the invention, the terminal unit transmits a data frame via the data bus based on recognition of its address during the specified configuration phase. In this way, the procedure for requesting data from individual terminal blocks using a central unit is unified. There should be no difference between the initial request by the central unit and any of the subsequent requests for data delivery.

In another preferred embodiment of the method according to the invention, each of several terminal blocks transmits a data frame via a data bus for a predetermined period of time, which is set by the central unit. This provides terminal blocks with independence from any data request and delivery issued by the central unit, which leads to an autonomous subsystem.

Preferably, the order in which data is transmitted by the terminal blocks during the indicated content phase is pre-set by the central unit. For example, the order of data transfer by terminal blocks can be saved in a look-up table (search table), and therefore, the user can control and even edit it autonomously, i.e. away from the physical operating environment, and in advance. In general, the specified synchronization signal can be generated using a separate main clock generator. The main clock generator may or may not be integrated with the system and may be located in a separate environment in order to fulfill the requirements regarding noise immunity.

Preferably, said synchronization signal is a standard signal, in particular a signal that complies with IEEE 802.3.

More preferably, the terminal blocks recover their respective clock signals from said clock signals. The restoration of synchronization is achieved through the use of a phase-locked loop of the PLL frequency.

In particular, data exchange between terminal blocks is performed by mirroring the specified data onto the clipboard in the central unit. This makes it unnecessary to comprehensively adapt the communication protocol to data transmission both to the central unit and to another terminal unit.

According to another aspect of the invention, there is provided a switching system for transmitting audio data between each of several terminal blocks. The specified communication system contains:

a large number of terminal blocks for buffering audio data;

a main bus for transmitting control signals to said terminal blocks;

a data bus for transmitting audio data from terminal blocks and

a central unit requesting audio data from terminal blocks via the specified main bus and receiving audio data through the specified data bus.

The communication system is characterized in that the central unit checks the identification of the terminal blocks during the initialization phase; the central unit transmits a predetermined data frame including the first synchronization signal, the address of the corresponding terminal block, the content area and the second synchronization signal through the specified main bus during the configuration phase, and audio data is transmitted via the data bus through one of several terminal blocks in within the time interval between samples of the audio signal, which corresponds to the interval between the first synchronization signal and the second synchronization signal and.

In a preferred embodiment of the communication system according to the invention, the central unit comprises a terminal block configuration unit comprising a list of said terminal blocks. In other words, the identification of all terminal blocks is listed in the system, and each terminal block that is new in the system must be registered with the configuration block of the terminal blocks so as to gain authorized access to them. The term "identification" in this case should be interpreted as the presence - perhaps, among other elements - of the individual number (address) of the corresponding terminal unit, as well as permission to access it to the shared bus (s).

In particular, said terminal block configuration block is preferably connected to an exchange block to generate said data frame. By separating the generation of the data frame from the monitoring tasks, such as the identification verification performed by the configuration unit of the terminal blocks, the system becomes more flexible and due to the lack of a modular architecture can be more easily identified, which in turn increases the reliability of the system.

In particular, each of the terminal blocks of the communication system contains phase-locked loop to restore its clock signal from the specified synchronization signal. Thus, each terminal block can, if necessary, synchronize its clock pulses without any delay that could occur if a normal synchronization pulse would come from the central block.

In addition, the clipboard as part of the central block is preferably used for exchanging data between terminal blocks, which makes it possible to mirror the received data and send them to the transceiver block of the specified central block.

The invention describes, among others, the listed advantages compared to the prototype. Since the communication system according to the invention provides deterministic access to a bus that is controlled by a central control unit, a high reliability of communication is achieved. A further increase in reliability is preferably achieved due to the redundancy of the system. In this case, the first central unit of the two works, and the other is in a “hot reserve” state. If at a given moment of time a working unit is failing, then another unit comes into operation. Thus, the system is especially useful in aeronautical electronics, in particular in aircraft devices with high-speed data management and digitized analog signals, in particular, for the fast passage of audio signals. Moreover, the system according to the invention makes it possible to create a more efficient data bus structure, since two separate bus lines are used which are connected to a plurality of terminal blocks. The central unit uses the main bus only as a control bus when transmitting data from the central unit to the terminal units. The connected terminal blocks can send their data to a common bus, namely to the data bus. Further, the invention provides a simple modular structure of a communication system and, in general, data transmission is not at risk of blocking in the event of a failure of a separate terminal unit.

The invention will be described in more detail with reference to the embodiments presented in the accompanying drawings, by way of example only.

Figure 1 presents a diagram of a first embodiment of a communication system according to the invention;

figure 2 presents a functional diagram of a variant of implementation of the terminal blocks according to the invention in the communication system of figure 1;

figure 3 presents a functional diagram of a variant of implementation of the Central unit according to the invention in the communication system of figure 1;

on figa presents an embodiment of a data frame when transmitting data from the Central unit to the terminal blocks during the configuration phase according to the invention;

on figv presents an embodiment of a data frame when transmitting data from terminal blocks to the Central unit during the configuration phase according to the invention;

5A is an embodiment of a data frame for transmitting data from a central unit to terminal units during a content phase according to the invention;

FIG. 5B shows an embodiment of a data frame for transmitting data from terminal blocks to a central unit during the content phase of the invention;

figure 6 presents an embodiment of the invention when exchanging data between terminal blocks.

Figure 1 presents a block diagram of an embodiment of a communication system according to the invention. The central unit 10 is connected, on the one hand, via a data bus 12 (common bus) with TX transmitting devices of a large number of terminal blocks T, each of which is designated T1, T2 and T3, respectively. On the other hand, the central unit 10 is connected via the main bus 14 to the receivers RX of the indicated terminal blocks T. The central unit 10 serves only as a transmitter to the main bus 14, i.e. terminal blocks T only receive data from the central block 10 as passive elements. A data bus 12 is used to transmit multiplexed data from terminal blocks T1, T2, T3 to a central unit. The procedure for accessing the terminal blocks T to the bus 12 is controlled by the central unit 10.

Figure 2 presents a block diagram of a terminal block T, shown in figure 1. Each terminal block contains an RX receiver and a TX transmitter. In addition, it is equipped with an address recognition unit 21, a reception state controller 22, a PLL (PLL) 23 frames with a main clock, a 24-cycle counter, a data input buffer 25, an input / output interface 26, a data output buffer 27 and a data transfer controller 28 .

The RX receiver is adapted to recognize data signals, time signals, and address signals. In the address recognition module 21, the addresses are filtered: the response of the corresponding terminal block T is only requested to obtain the desired address, otherwise the received data is ignored.

From the received time signals, the main clock pulses are restored in the PLL 23 of the frame, and the main clock pulses are supplied from the central unit 10. The time signal from the generator 23 of the main clock pulses is distributed to all components of the terminal block T. The reconstructed clock is supplied to the counter 24 cycles, which determines the time for the next access to the bus of the corresponding terminal block T. Information about access to the bus is stored in the reception state controller 22. Also, a clock pulse from a generator 23 and a divided clock frequency from a counter of 24 cycles are supplied to the data input buffer 25.

The data frames that are received by the receiver RX of the terminal block T from the main bus 14 are processed depending on the information content transmitted with the data. The receive state controller 22 controls the flow of data received through the RX receiver. It is connected to a data transfer controller 28 and to an input / output interface 26 and a counter 24 cycles. The data that is received in each frame by the RX receiver is buffered for each bus frame in the data input buffer 25, if they are suitable for switching with other systems and system modules. The input buffer 25 is controlled by an input / output interface 26. The input / output interface 26 may comprise a digital-to-analog converter, speakers, and other control units.

If data is to be transmitted from one terminal block T to another terminal block T or to the central block 10, then this data is buffered in the data output buffer 27, from which it is then transferred to the TX transmitting device. Data is buffered for each bus frame in the data output buffer 27 in the order in which they are transmitted in the data frame. The delivery of such data to the TX transmitting device is processed at the appropriate processing steps using the data transfer controller 28 in the terminal block T.

In general, terminal blocks T are designed to perform certain functions. However, you can use several terminal blocks T with similar functions.

If the buses 12, 14 are Ethernet compliant, then the RX receiver can be designed in accordance with IEEE 802.3.

In Fig.3 presents a block diagram of a Central unit 10 shown in Fig.1. The central unit 10 comprises a terminal unit configuration controller 31, a transmitter data device memory 32, a transmitter 33, a system clock 34, a receiver 35, a receiver data memory 36, a clipboard 37, a data switch control matrix 38, a receiver configuration module 39 data and phase controller 40 of the main bus. The control unit 31 of the configuration of the terminal block contains a list of terminal blocks T, which are connected to the central block 10. This list can be easily changed when entering new data, for example, from the corresponding host controller or can be adjusted when changing operating conditions are met. The control unit 31 of the configuration is connected to the memory 32 of the data of the transmitting device, and the memory 32 is in turn connected to the transmitting device 33. In addition, the control unit 31 of the configuration determines which data from the memory 32 of the data of the transmitting device is currently to be transferred to the transmitting device 33.

The transmitting device 33 generates a complete data frame on the main bus 14, including a synchronization signal, which is valid for all terminal blocks T. As such, the synchronization signal can be controlled or can be determined by a system clock 34, which is connected to the transmitting device 33.

The receiving module 35 reads and monitors data that is received from the terminal blocks T. The data is sent to the data memory 36 of the receiving device, which acts as a buffer memory. The receiving device configuration unit 39 relates to a data receiving memory device 36. In the case of establishing a communication link between the individual terminal blocks T, data can be directly transferred to the memory 32 for data of the transmitting device via the clipboard 37. The clipboard 37 is controlled and controlled by the control matrix 38 of the data switch.

The following three phases of communication can be distinguished on buses 12 and 14:

1. The initialization phase;

2. The configuration phase;

3. The content phase.

These phases are controlled by the main bus control unit 40. Due to this structure, the data capacity of the terminal blocks T, which are connected to the bus in this order, can be adapted and optimized. During the initialization phase, the central unit 10 monitors which of the terminal units T has access to the bus 12 at a given time or at a given time. Next, it is determined what data is required on the bus 12. In particular, if there are multiple requests from the connected terminal blocks T at the same time, they can be collected and arranged according to priority using the central unit 10.

On figa presents a data frame when transmitting data from the Central unit 10 to the terminal blocks T via the main bus 14, while on figv presents a data frame when transmitting data from the terminal blocks T to the central unit 10 via the data bus 12 configuration phase time. In these figures, the length of the period is indicated by a double arrow.

Each data frame 50 on bus 14 begins with a synchronization signal 51 (Sync). Preferably, this signal is derived from or conforms to a protocol related to high level synchronization according to the IEEE 802.3 standard.

The clock signal 51 and the synchronization sequence respectively consists of a “preamble” of 7 bytes in length and an “initial sequence of data frame” of 1 byte in length. The rear end bits of the “initial data frame sequence” (“11” according to IEEE 802.3) will be used for accurate full synchronization. This determines the frame period for the sampling frequency of the audio signal of users of the system, which will become clear in the following description based on figa. In order to provide a simple way of transmitting audio data, the distance between the two clocks should correspond to the sampling period of the audio system. This means that the sampling frequency of A / D or D / A converters connected to the terminal blocks is acceptable for the system as a whole. In other words, all the terminal blocks T in the system are controlled by the same clock generator.

In the configuration phase, the central unit 10 transmits the set data frame, starting with the clock 51, as mentioned above. This clock signal 51 is used as a control clock signal for the entire system. An additional PLL system is used to restore synchronization of the quantization process of audio data and provide accurate information about the synchronization of all terminal blocks without the help of an additional sync signal transmission line or similar means. (It should be noted that, in contrast, the IEEE 802.3 standard provides only single-bit synchronization.) Therefore, the clock signal 51 can be easily changed, i.e. the frequency or the allocated time interval for the entire system can be dynamically changed based on the method of unstable synchronization. As a result, the noise immunity parameters of the entire trunk system 1 are improved.

Clock 51 follows address 52 of that specific terminal block for which the corresponding data frame is intended. In system 1, separate addresses are reserved that are not assigned to real physical terminal blocks T. These address words are used as broadcast addresses, and the subsequent configuration data 53 determines the behavior of all terminal blocks T, which are also connected.

Therefore, a certain amount of content data can be reserved in the form of, for example, audio data that is constantly transmitted further in the form of multi-channel transfer from the central unit 10 to the terminal blocks T. In the case when the specified address belongs to a specific terminal block in the system, the characteristics of this terminal block T will vary due to configuration data 53. Subsequent payload data 54 may comprise, for example, switching data for a corresponding block.

Each data frame 50 will end with a data validation sequence 55. The check sequence may be, for example, a simple check of a cyclic checksum. The described data frame 50 is then repeated again, starting with the synchronization sequence 51. The system in accordance with the present invention has the advantage that there are no time pauses on the main bus 14 during unloading when there is traffic on the same physical line from different transmitting devices T. Between field 55 and field 51 can be created gap 56 so as to adapt the overall frame length 50 to specific system requirements.

After the sampling time of the audio data by the frame in Fig. 4A is determined, a data frame is examined with reference to Fig. 4B during transmission from one of the terminal blocks T to the central block 10. During the configuration phase, the terminal block T will respond to receiving its own address by sending one data frame 60 to a common bus. This reaction is generated by an address recognition circuit. The data frame 60 also begins with a synchronization sequence 61, preferably in accordance with the IEEE 802.3 standard, however, it is not used for the synchronization system. The synchronization sequence structure according to the IEEE 802.3 standard has the advantage that modules and transmitters based on Ethernet technology can be used.

The synchronization sequence 61 is monitored by an identification field 62 from the terminal block T. The identification field 62 contains the individual address of the terminal block T and the requested amount of data content. The data field 63 of the data portion of the data unit of the terminal block, in turn, is monitored by a control sequence 64 to verify the correctness of the data. Similar to the data portion 50 from the central unit 10 to the terminal units T, the data portion from the terminal units T in the central unit 10 ends with a second synchronization field 61 with a gap of 65 between the synchronization field 61 and the control sequence 64, if necessary. The frame period depends on the actual system configuration.

At the end of the data transfer by one of the terminal blocks T, the central block 10 can access the same or another terminal block T. During this process, there is no communication on the data bus until the next address is transmitted and recognized accordingly.

During the configuration phase, the central unit 10 determines the order of the addresses of the terminal blocks T. This order does not have to be sequential. Therefore, each terminal block T must store an individual counter value, which is selected from the configuration data field 53 by the terminal block T.

After that, the central unit 10 can start the content phase with a given address of the terminal unit (which, however, is not transmitted further via the bus) and a specific configuration data field. This means that, based on the following synchronization sequence, the internal cycle counters 24 of all terminal blocks T are activated. Due to the individual counter value that is stored in each terminal block T, each terminal block T will send its own data frame to a common bus 12 at a given time. The access order to the bus is set by the central unit 10 by means of different counter values that are stored in each of the terminal blocks T.

The above configuration phase is followed by the content phase. In the content phase, the data frames on the buses 12 and 14 respectively differ from the corresponding data frames in the configuration phase in that they no longer load upon address overflow. Corresponding data frames on buses 12 and 14 are shown in FIGS. 5A and 5B. The data frame 70 from the central unit 109 in any of the terminal blocks T in FIG. 5A contains only synchronization sequences and payload sequences. It ends with a check sequence and a synchronization bit with an intermediate interval, if necessary. The period between the next two sequences of synchronization bits determines the period of obtaining a sample of audio data. Accordingly, the data frame 80 from the terminal block T to the central block 10 in FIG. 5B also contains only synchronization sequences and payload sequences, being completed with a control sequence and a synchronization bit with an intermediate interval, if necessary. The period between the next two sequences of synchronization bits determines the frame period depending on the system configuration.

Therefore, due to the different layout in the configuration phase and in the content phase, the data frames 70, 80 differ from similar frames 50 and 60 on the main bus 14 and the common bus 12, respectively. With the established procedure for accessing the bus, only the number of clock signals from the central unit determines access to the common bus. This means that there are no longer protocol overheads in the data frames, and in fact, the full bus access time is used for the payload data.

To implement the invention, components are used in accordance with the IEEE 802.3 standard (IEEE 802.3 physical layer).

For devices related to the security system, several main buses 14 can be used instead of one.

For fast transmission of audio data, the main clock generator can be implemented using PLL audio, which is synchronized with the bits of the final sequence of the clock signal. Information about the clock synchronization of the clock signal can be obtained from the integrated standard PLL systems according to IEEE 802.3 (physical layer IEEE 802.3).

Data exchange between the terminal blocks T, which are connected to the system 1, can be achieved by scaling the amount of data.

The exchange of data between the terminal blocks T is easily accomplished by mirroring the corresponding data to the exchange buffer 37 in accordance with a deterministically initiated protocol.

So, the communication system, namely: the electronic system in accordance with the invention has a modular structure in which data transmission is no longer blocked by a separate terminal unit in the event of a malfunction. Due to the shared bus structure, Ethernet components can be used at the physical layer, for example in accordance with 10BASE-T IEEE 802.3 with a physical layer specification for 10 Mbps LAN with CSMA / CD access method, IEEE 802.3 clause 14; 100BASE-T: IEEE 802.3 for a local area network with a transmission speed of 100 Mbps and with the CSMA / CD access method, IEEE 802.3 clause 22 and 28 without the detection of autocollisions, which is necessary for single-bus systems.

Moreover, the double bus structure allows for the continuous transfer of data from the central unit to separate terminal blocks, and simple tools for synchronous switching systems that can easily be adapted to transmit audio data are also offered.

In addition, data exchange between the individual terminal blocks is possible. This is explained below with reference to FIG. 6, where a multiplexed communication system with a double loop is shown. Its main component is the aforementioned data switch control matrix 38, comprising a scalable clipboard 37 on its input side and a scalable clipboard 37 on its output side. The specified control matrix 38 of the data switch is used for direct communication between terminal blocks T. The frequency band of the data is scalable and depends on the number of data frames related to the paired terminal blocks T. The number of available data frames is set and is applied to all paired terminal blocks T , which are supposed to be used when transmitting data. The amount of payload data to be exchanged between the terminal blocks T is set by the host processor CPU (not shown) of the central unit 10. Due to the set update period of the trunk system, a communication channel is opened with a guaranteed data transfer rate. Actual output data in the terminal block can then be fed to other data channels with a shorter update period according to the CAN, RS485, RS232, etc. standards, which are presented as an example in FIG. 6 as the terminal interface 91 block. The data switch control matrix 38 is preferably implemented in hardware, i.e. without the inclusion of any software components. Thus, high-speed data transmission is implemented; data exchange with a specific frame structure allows you to provide a complete hardware constructive solution to the control matrix 38 of the data switch with input and output buffers. The data transmission time between two terminal blocks T can be reduced to a duration of several frames.

If desired, the central unit 10 can be used as an access point for the existing network of terminal blocks T. In this case, the interface of the central unit 10 can be determined by the specific protocol used in aviation, such as AFDX (Ethernet duplex switched network for aircraft electronic equipment), also known as standard No. 664 ARINC (Aeronautical Radio Incorporated - aeronautical radio network corporation) and related to a multi-channel network and protocol for communication between airborne units. This is based on Ethernet with optional “quality of service” (QoS) and deterministic route determination. This interface is presented as an example in FIG. 6 as an interface 92 of the central unit.

Reference designations

10 - central unit

12 - data bus (common bus)

14 - main tire

21 - address recognition module

22 - reception state control unit

23 - clock generator

24 - cycle counter

25 - data entry buffer

26 - data input / output

27 - data output buffers

31 - terminal block configuration control unit

32 - memory for storing data of the transmitting device

33 - transmitting device

34 - system clock

35 - receiving module

36 - memory for storing data of the receiving device

37 - clipboard

38 - control matrix of the data switch

39 - receiver configuration block

40 - main bus control unit

50 - data frame in the configuration phase

51 - clock signal (clock signal)

52 - address

53 - configuration data

54 - content data

55 - check sequence

56 - gap

60 - data frame in the configuration phase

61 - configuration field

62 - identification field

63 - content data field

64 - check sequence

65 - gap

70 - data frames in the content phase

80 - data frames in the content phase

91 - terminal block interface

92 - RX interface of the receiving unit of the Central unit

T, T1, T2, T3 - terminal blocks

Claims (13)

1. A method for controlling a communication system (1) for transmitting audio data between each of a large number of terminal blocks, wherein said switching system (1) comprises:
several terminal blocks (T; T1, T2, T3) for buffering audio data;
the main bus (14) for transmitting control signals to the indicated terminal blocks (T; T1, T2, T3);
a data bus (12) for transmitting audio data from said terminal blocks (T; T1, T2, T3); and
a central unit (10) making a request from terminal blocks (T; T1, T2, T3) through the specified main bus (14) and receiving audio data through the specified data bus (12);
characterized in that it contains the following steps:
verification of the identification of the indicated terminal blocks (T; T1, T2, T3) by the indicated central unit (10) during the initialization phase;
the transmission of predetermined data frames containing the first clock signal (51), the terminal address (52) of the corresponding terminal block (T; T1, T2, T3), the content field (54) and the second clock signal (51) by the indicated central unit (10) through said main bus (14) during the configuration phase; and
transmission of audio data via the indicated data bus (12) by one of the indicated several terminal blocks (T; T1, T2, T3) within the time interval between the audio signal samples, which corresponds to the interval between the specified first synchronizing signal and the specified second synchronizing signal. 2. The method according to claim 1, characterized in that said terminal unit (T; T1, T2, T3) transmits a data frame (60) through said data bus (12) based on recognition of its own address during said configuration phase. 3. The method according to claim 1, characterized in that each of these several terminal blocks (T; T1, T, T3) transmits a data frame for a predetermined time, which is set by the specified central unit (10), via the specified bus (12) data. 4. The method according to claim 1, characterized in that the sequence of transmissions by the indicated several terminal blocks (T; T1, T2, T3) during the content phase is set by the previously indicated central unit (10). 5. The method according to any one of the preceding paragraphs, characterized in that said synchronizing signal (51) is generated by the main synchronization pulse generator (34). 6. The method according to claim 1, characterized in that the clock signal (51) is a signal in accordance with IEEE 802.3. 7. The method according to claim 1, characterized in that said terminal blocks (T; T1, T2, T3) perform synchronization restoration from the specified synchronization signal (51) by applying phase-locked loop (PLL). 8. The method according to claim 1, characterized in that the data exchange between the terminal blocks (T; T1, T2, T3) is carried out by mirroring the specified data in the exchange buffer (37) in the central block (10). 9. A communication system (1) for transmitting audio data between each of several terminal blocks, comprising:
several terminal blocks (T; T1, T2, T3) for buffering audio data;
the main bus (14) for transmitting control signals to the indicated terminal blocks (T; T1, T2, T3);
a data bus (12) for transmitting audio data from said terminal blocks (T; T1, T2, T3); and
a central unit (10) requesting audio data from said several terminal blocks (T; T1, T2, T3) through said main bus (14) and receiving audio data through said data bus (12);
characterized in that
the central unit (10) checks the identification of these terminal blocks (T; T1, T2, T3) during the initialization phase;
the central unit (10) transmits a predetermined data frame containing the first clock signal (51), the terminal address (52) of the corresponding terminal block (T; T1, T2, T3), the content field (54) and the second clock signal (51), through the specified main bus (14) during the configuration phase; and
audio data is transmitted through the indicated data bus (12) by one of the indicated several terminal blocks (T; T1, T2, T3) within the time interval between the audio signal samples, which corresponds to the interval between the specified first synchronizing signal and the specified second synchronizing signal. 10. The communication system according to claim 9, characterized in that the central unit (10) comprises a control unit (31) for the configuration of the terminal unit, comprising a list of these several terminal units (T; T1, T2, T3). 11. A communication system according to claim 10, characterized in that said terminal block configuration control unit (31) is connected to a transmission unit (33) to form said data frame. 12. A communication system according to any one of claims 9 to 11, characterized in that each of these several terminal blocks (T; T1, T2, T3) contains phase-locked loop to restore synchronization from the specified clock signal (51). 13. The communication system according to claim 9, characterized in that the exchange buffer (37) contained in the indicated central unit (10) is intended for exchanging data between terminal blocks, which provide the ability to mirror the received data and send them to the transceiver of the specified central unit ( 10).

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