RU2367002C1 - Generator of system of discrete orthogonal signals - Google Patents

Abstract

FIELD: physics, computer technology.

SUBSTANCE: invention is related to automatics and computer technology and may be used in devices for spectral analysis and communication for generation of orthogonal signals. Device comprises clock oscillator, counter, cyclic shift registers, multipliers of the first group, four limiters of signals level, multipliers of the second group, element NOT, multiplier.

EFFECT: simplification of generator and elimination of equipment duplication.

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Description

The invention relates to automation and computer engineering and can be used in spectral analysis and communication devices to generate orthogonal signals.

- номер циклического регистра сдвига), 2^m-2 умножителей первой группы, 2^m-1 пар умножителей второй группы, 2^m-1 пар умножителей третьей группы, четыре ограничителя уровня, элемент НЕ и умножитель (см. авторское свидетельство СССР №1741122, кл. G06F 1/02, 1990).A known generator of a discrete orthogonal signal system comprising a clock, counter, m-1 cyclic 2 ⁱ -bit shift registers (2 ^m is the dimension of the Haar signal system generated at the first bit output of the counter and the outputs of the multipliers of the first group,

- the number of the cyclic shift register), 2 ^m -2 multipliers of the first group, 2 ^m -1 pairs of multipliers of the second group, 2 ^m -1 pairs of multipliers of the third group, four level limiters, the element NOT and the multiplier (see USSR copyright certificate No. 1741122, C. G06F 1/02, 1990).

However, the known generator has considerable complexity and hardware redundancy, since it contains 2 ^m -1 pairs of multipliers of the third group (the number of multipliers of the third group is exactly 2 ^{m + 1} -2).

- номер циклического регистра сдвига), 2^m-2 умножителей первой группы, 2^m-1 пар умножителей второй группы, 2^m-1 умножителей третьей группы, четыре ограничителя уровня сигналов, элемент НЕ и умножитель, причем i-й разрядный выход счетчика (нумерация со стороны старшего разряда) соединен с сдвигающим входом 1-го циклического регистра сдвига, (i+1)-й разрядный выход счетчика соединен с первыми входами с (2ⁱ-1)-го по (2ⁱ⁺¹-2)-й умножителей первой группы, вторые входы которых соединены с соответствующими разрядными выходами i-го цилиндрического регистра сдвига,(m+1)-й разрядный выход счетчика соединен с входами первого и второго ограничителей уровня сигналов, выходы первого и второго ограничителей уровня сигналов соединены соответственно с вторыми входами первого и второго умножителей каждой пары умножителей второй группы, первый разрядный выход счетчика через элемент НЕ соединен с входом третьего ограничителя уровня сигналов, m-й разрядный выход счетчика соединен с входом четвертого ограничителя уровня сигналов, выходы третьего и четвертого ограничителей уровня сигналов соединены с входами умножителя, выход которого соединен со вторыми входами умножителей третьей группы, первый разрядный выход счетчика соединен с первым входом первого умножителя третьей группы, выход j-го

умножителя первой группы соединен с первым входом (j+1)-го умножителя третьей группы, выходы умножителей третьей группы соединены с первыми входами соответствующих умножителей второй группы, выходы которых являются выходами генератора (см. патент на изобретение №2022333 от 17.09.93, опубл. 30.10.94, бюл. №20).Closest to the technical nature of the present invention is a generator of a discrete orthogonal signal system comprising a clock, counter, m-1 cyclic 2 ⁱ -bit shift registers (2 ^m is the dimension of the Haar signal system generated at the first bit output of the counter and the outputs of the first multipliers groups

is the number of the cyclic shift register), 2 ^m -2 multipliers of the first group, 2 ^m -1 pairs of multipliers of the second group, 2 ^m -1 multipliers of the third group, four limiters of the signal level, the element NOT and the multiplier, and the ith bit output of the counter ( numbering from the high-order side) is connected to the shift input of the 1st cyclic shift register, the (i + 1) -th bit output of the counter is connected to the first inputs from (2 ⁱ -1) -th to (2 ^{i + 1} -2) - th multipliers of the first group, the second inputs of which are connected to the corresponding bit outputs of the i-th cylindrical register with moving, the (m + 1) -th digit output of the counter is connected to the inputs of the first and second signal level limiters, the outputs of the first and second signal level limiters are connected respectively to the second inputs of the first and second multipliers of each pair of multipliers of the second group, the first bit output of the counter through the element NOT connected to the input of the third signal level limiter, the mth bit output of the counter is connected to the input of the fourth signal level limiter, the outputs of the third and fourth signal level limiters are connected to odes multiplier, whose output is connected to second inputs of the multipliers of the third group, the first bit of the counter output is connected to a first input of a first multiplier of the third group, the output j-th

the multiplier of the first group is connected to the first input of the (j + 1) th multiplier of the third group, the outputs of the multipliers of the third group are connected to the first inputs of the corresponding multipliers of the second group, the outputs of which are the outputs of the generator (see patent for the invention No. 2022333 of 09.17.93, publ. . 30.10.94, bull. No. 20).

However, the known generator has significant complexity and hardware redundancy, as it has 2 ^m -1 multipliers of the third group.

The aim of the invention is to simplify the generator by eliminating 2 ^m - ^m -1 multipliers of the third group.

- номер циклического регистра сдвига), 2^m-2 умножителей первой группы, 2^m-1 пар умножителей второй группы, m умножителей третьей группы, четыре ограничителя уровня сигналов, элемент НЕ и умножитель, причем i-й разрядный выход счетчика (нумерация со стороны старшего разряда) соединен с сдвигающим входом i-го циклического регистра сдвига, вторые входы с (2ⁱ-1)-го по (2ⁱ⁺¹-2)-й умножителей первой группы соединены с соответствующими разрядными выходами i-го циклического регистра сдвига, (m+1)-й разрядный выход счетчика соединен с входами первого и второго ограничителей уровня сигналов, выходы первого и второго ограничителей уровня сигналов соединены соответственно с вторыми входами первого и второго умножителей каждой пары умножителей второй группы, первый разрядный выход счетчика через элемент НЕ соединен с входом третьего ограничителя уровня сигналов, m-й разрядный выход счетчика соединен с входом четвертого ограничителя уровня сигналов, выходы третьего и четвертого ограничителей уровня сигналов соединены с входами умножителя, выход которого соединен с вторыми входами умножителей третьей группы, первый разрядный выход счетчика соединен с первым входом первого умножителя третьей группы, выход первого умножителя третьей группы соединен с первыми входами первой пары умножителей второй группы, выходы умножителей второй группы являются выходами генератора, введены изменения, заключающиеся в том, что (i+1)-й разрядный выход счетчика соединен с первым входом (i+1)-го умножителя третьей группы, выход (i+1)-го умножителя третьей группы соединен с первыми входами с (2ⁱ-1)-го по (2ⁱ⁺¹-2)-й умножителей первой группы, выход j-го

умножителя первой группы соединен с первыми входами (j+1)-й пары умножителей второй группы.This goal is achieved by the fact that in a known generator of a system of discrete orthogonal signals containing a clock generator, counter, m-1 cyclic 2 ^i- bit shift registers (m + 1 - the number of bits of the counter,

is the number of the cyclic shift register), 2 ^m -2 multipliers of the first group, 2 ^m -1 pairs of multipliers of the second group, m multipliers of the third group, four signal level limiters, the element NOT and the multiplier, and the i-th output of the counter (numbering from the side senior bit) is connected to the shifting input of the i-th cyclic shift register, the second inputs from the (2 ⁱ -1) -th by (2 ^{i + 1} -2) -th multipliers of the first group are connected to the corresponding bit outputs of the i-th cyclic shift register , (m + 1) -th digit output of the counter is connected to the inputs of the first and second o signal level limiters, the outputs of the first and second signal level limiters are connected respectively to the second inputs of the first and second multipliers of each pair of multipliers of the second group, the first bit output of the counter through the element is NOT connected to the input of the third signal level limiter, the mth bit output of the counter is connected to the input of the fourth signal level limiter, the outputs of the third and fourth signal level limiters are connected to the inputs of the multiplier, the output of which is connected to the second inputs of the multiplier of the third group, the first bit output of the counter is connected to the first input of the first multiplier of the third group, the output of the first multiplier of the third group is connected to the first inputs of the first pair of multipliers of the second group, the outputs of the multipliers of the second group are the outputs of the generator, the changes are introduced, consisting in the fact that (i The +1) -th digit output of the counter is connected to the first input of the (i + 1) -th multiplier of the third group, the output of the (i + 1) -th multiplier of the third group is connected to the first inputs from (2 ⁱ -1) -th by (2 ^{i + 1} -2) -th multipliers of the first group, the output of the j-th

the multiplier of the first group is connected to the first inputs of the (j + 1) th pair of multipliers of the second group.

и

предлагаемым генератором, на фиг.3 - вид сигналов, формируемых предлагаемым генератором.Figure 1 presents a structural diagram of a generator of a system of discrete orthogonal signals, figure 2 is a timing diagram illustrating the process of generating signals

and

the proposed generator, figure 3 is a view of the signals generated by the proposed generator.

The discrete orthogonal signal system generator comprises a clock 1, a counter 2, cylindrical shift registers 3, multipliers 4 of the first group, first and second limiters 5.1 and 5.2 of the signal level, multipliers 6 of the second group, multipliers 7 of the third group, element NOT 8, the third and fourth limiters 9.1 and 9.2 of the signal level, multiplier 10.

The generator operates as follows.

In the initial state, counter 2 is reset, and codes of the form 1000 ... 0 are recorded in the cyclic shift registers 3. Under the action of clock pulses coming from the output of the generator 1, at the outputs of the m high bits of the (m + 1) -bit counter 2, a system of Rademacher signals, represented by levels of ± 1, is formed. Rademacher signals are fed to the first inputs of the corresponding multipliers 7 of the third group. The number of multipliers 7 in the proposed generator is equal to m, that is, (2 ^m -m-1) multipliers are fewer than in the prototype (see patent for the invention No. 2022333 of 09.17.94, publ. 30.10.94, bull. No. 20), which includes 2 ^m -1 multipliers 7.

During the period of generating signals at the outputs of the generator, the signal generated at the first bit output of the counter 2 goes to the input of the element NOT 8. The inverted signal from its output goes to the input of the third signal level limiter 9.1. At the same time, the input of the fourth limiter 9.2 of the signal level receives a Rademacher signal from the mth bit output of counter 2. The limiters 9 are implemented as diodes in such a way that at the output of the third limiter 9.1 the positive part of the signal from the output of the element NOT 8 appears, and at the output of the fourth limiter 9.2, the negative part of the Rademacher signal arriving from the mth bit output of counter 2 appears. Since the first input of the multiplier 10 receives the signal from the output of the third limiter 9.1, and the second input receives the signal from the output 9.2 yes fourth limiter, the output of the multiplier 10 forms a sequence of negative pulses, located on the second half-wave signal generation at the generator output. This sequence of negative pulses arrives at the second inputs of all the multipliers 7 of the third group, the first inputs of which receive the corresponding Rademacher signals. As a result of multiplication at the outputs of the multipliers 7 of the third group, signals are formed whose shape differs from the shape of the Rademacher signals.

The signal from the output of the first multiplier 7 of the third group is fed to the first inputs of the first pair of multipliers 6 of the second group. The signals from the outputs of the remaining multipliers 7 of the third group are fed to the first inputs of the corresponding multipliers 4 of the first group, the second inputs of which receive signals from the bit outputs of the shift registers 3. The width of shift register 3 and the number of multipliers 4 in the subgroup are equal to the number of signals in the subset (2 ⁱ , where i is the number of the subset) obtained from one Rademacher signal converted in the corresponding multiplier 7. In registers 3, a code of the form 1000 ... 0, bits is cyclically shifted which is specified by the "existence intervals" of the signals at the outputs of the multipliers 4. A shift by one bit is caused by each change in the sign of the Rademacher signal at the shifting input of register 3. The signals from the outputs of the multipliers 4 of the first group are fed to the first inputs, respectively Enikeev multipliers 6 of the second group.

The Rademacher signal from the output of the (m + 1) -th discharge of counter 2 goes to the inputs of the first and second limiters 5.1 and 5.2 of the signal level. The limiters 5 can be implemented as diodes in such a way that the positive part of the Rademacher signal appears at the output of the limiter 5.1, and the negative part of the Rademacher signal appears at the output of the limiter 5.2.

As a result of multiplying the signals supplied to the first inputs of the multipliers 6 of the second group, with the output signals of the limiters 5, the signals to K ^{(k) r (θ)} and L ^{(k) r (θ)} are completely identical to the signals formed prototype (see patent for invention No. 2022333 dated 09/17/94, class G06 1/02).

и

.Figure 2 shows the timing diagrams illustrating the process of forming the proposed signal generator

and

.

The diagrams show the temporary status of the outputs:

a) clock generator 1;

b) (m + 1) th category of counter 2;

c) the first limiter 5.1 signal level;

d) the second limiter 5.2 signal level;

d) the first category of the counter 2;

e) element NOT 8;

g) the third limiter 9.1 signal level;

h) m-th category of the counter 2;

i) the fourth limiter 9.2 signal level;

j) a multiplier of 10;

k) the second category of the counter 2;

k) a multiplier 7.2 of the third group, the first input of which receives a signal from the output of the second discharge of counter 2, and the second input receives a signal from the output of the multiplier 10;

m) the multiplier 4.2 of the first group;

;m) the corresponding multiplier 6 of the second group, on which the signal is formed

;

.o) the corresponding multiplier 6 of the second group, on which the signal is formed

.

Figure 3 shows the signals generated by the proposed generator. From the drawing it can be seen that these signals are completely identical to the signals generated by the prototype.

Using the invention allows to significantly simplify the device generator by eliminating 2 ^m - ^m -1 multipliers of the third group.

Claims (1)

A generator of a discrete orthogonal signal system, comprising a clock generator, a counter, m-1 cyclic 2 ^i- bit shift registers (m + 1 is the number of bits of the counter, i = 1,

is the number of the cyclic shift register), 2 ^m -2 multipliers of the first group, 2 ^m -1 pairs of multipliers of the second group, m multipliers of the third group, four signal level limiters, the element NOT and the multiplier, and the i-th output of the counter (numbering from the side senior bit) is connected to the shifting input of the i-th cyclic shift register, the second inputs from the (2 ⁱ -1) -th by (2 ^{i + l} -2) -th multipliers of the first group are connected to the corresponding bit outputs of the i-th cyclic shift register , (m + 1) -th digit output of the counter is connected to the inputs of the first and second o limiters, signal level, the outputs of the first and second signal level limiters are connected respectively to the second inputs of the first and second multipliers of each pair of multipliers of the second group, the first bit output of the counter through the element is NOT connected to the input of the third signal level limiter, the m-th bit output of the counter is connected with the input of the fourth signal level limiter, the outputs of the third and fourth signal level limiters are connected to the inputs of the multiplier, the output of which is connected to the second inputs of the multiplier of the third group, the first bit output of the counter is connected to the first input of the first multiplier of the third group, the output of the first multiplier of the third group is connected to the first inputs of the first pair of multipliers of the second group, the outputs of the multipliers of the second group are generator outputs, characterized in that in order to simplify the generator into it changes have been introduced, consisting in the fact that the (i + 1) -th digit output of the counter is connected to the first input of the (i + 1) -th multiplier of the third group, the output of the (i + 1) -th multiplier of the third group is connected to the first inputs with ( 2 ⁱ -1) -th by (2 ^{i + l} -2) -th multipliers of the first group, the output of the j-th

the multiplier of the first group is connected to the first inputs of the (j + 1) th pair of multipliers of the second group.

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