RU2360282C2 - Programmable serial bus controller - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: present invention relates to input-output devices for processors and microcontrollers, and more specifically to serial interface controllers SPI, Microwire, I2S, and SPORT. The device contains control and state registers of the receiver and transmitter, frequency dividers for the receiver and transmitter, units for generating clock pulses of the receiver and transmitter, each of which consists of a clock signal multiplexer and a clock signal converter, a unit for generating control signals for the receiver and transmitter, each of which consists of a control signal generator and a control signal converter, a transmitter unit, consisting of a write buffer, counter and multiplexer, a receiver unit, consisting of read buffer, exchange logic unit, receiving register, counter and a decoder, output control unit and output control register.

EFFECT: more functional capabilities of the device due to functional combination of a range of serial interfaces.

1 dwg

Description

The present invention relates to the field of input-output devices for processors and microcontrollers and more particularly relates to controllers for serial interfaces SPI, Microwire, I2S, SPORT.

At the present stage of development of digital computer technology, the acute problem is the lack of external outputs of the microcircuit, as well as the problem of organizing the exchange of processor data with peripheral devices without distracting the processing power of the processor. The second problem is solved by shifting the task of controlling transmission and data processing to the peripheral interface controller, as well as by introducing DMA (direct memory access) channels for this controller. The first task is solved by functional integration of interfaces. However, in most cases, a method is used in which the controllers of various interfaces are hardware-separated and combined by multiplying the signals at the outputs, which leads to an unreasonable increase in hardware costs. In addition, the problem of completely combining the functions of the controllers of the SPI, I2S, and SPORT interfaces in one controller has not been solved. The situation is aggravated by the fact that there is no full compatibility of the SPI (Motorola) [1] and Microwire (National Semiconductor) [2] standards, because MOSI / MISO serial data outputs for SPI can have an input or output direction, depending on whether the device is a master or a slave, and the direction of Microwire's SDO, SDI outputs is strictly fixed.

The classic implementation of the SPI interface is made in the Motorolla microcontroller M68HC11. An obvious drawback of the controller - the lack of buffering in the direction of transmission, which does not allow continuous transmission, due to the fact that the recording of new data during the transfer leads to data loss, was corrected in the QSPI standard. The QSPI standard assumes buffering both in the transmission direction and in the receiving direction, which allows writing and reading data directly during transmission.

However, combining SPI with other interfaces is either done by multiplying the outputs from the hardware-separated controllers, or the circuit is implemented using the logic of capturing external signals to the system clock signal, which significantly reduces the maximum transmission frequency on this interface.

The closest technical solution to the claimed invention (the closest analogue) is a serial bus controller, which is part of the ADSP-BF537 microcircuit [3], manufactured by Analog Devices, which includes the functionality of the SPORT and I2S controllers.

However, in chips manufactured by Analog Devices, the SPI controller is still made separately from the combined SPORT-I2S controller. This is explained by the fact that the SPORT-I2S controller has several disadvantages that make it difficult to combine with SPI. One of them is the fact that after receiving the last bit, the port needs another edge of the clock signal to write data to the buffer, and when transmitting via the SPI bus with the arrival of the last bit, the formation of the clock signal may stop. It is not possible to use the control signal SS to control the writing to the buffer when it comes to a controller that combines several interfaces.

In addition, the SPORT-I2S controller is designed as an independent transmitter and receiver, and the standard SPI bus exchange involves controlling the reception and transmission of one master device, which uses a set of control signals SS (slave selection) to select the slave, the behavior of which is fundamentally different from the control signals TWS (selection of the transmission channel), RWS (selection of the reception channel) in the I2S standard [4], which also excludes the possibility of full functional combination of the SPORT-I2S controller with the SPI controller.

In an effort to make the processor more versatile, several SPI controllers and several SPORT-I2S controllers are implemented on the integrated circuit. This leads to an increase in the number of necessary conclusions of the microcircuit, as well as to an increase in its area. In real tasks, only a certain part of these controllers is involved, so such hardware costs are irrational. A logical step is to implement a group of controllers on the circuit, each of which can work with a wide range of interfaces, which leads to a more flexible and efficient use of the circuit.

The object of the invention according to the present application is a block diagram of a programmable controller for serial buses, functionally combining the ability to work on interfaces SPI, Microwire, I2S and SPORT.

A block diagram of a programmable serial bus controller according to the present invention is shown in the drawing, where

1 - transmitter control register

2 - transmitter status register

3 - receiver control register

4 - receiver status register

5 - pin control register

6 - transmitter unit

7 - write buffer

8 - transmitter bit counter

9 - output multiplexer

10 - receiver unit

11 - read buffer

12 - reception register

13 - block logic exchange

14 - receiver bit counter

15 - decoder

16 - transmitter frequency divider

17 - receiver frequency divider

18 - transmitter clock generation unit

19 - transmitter clock multiplexer

20 - transmitter clock signal converter

21 - receiver clock generation unit

22 - receiver clock multiplexer

23 - receiver clock

24 - transmitter control signal generation unit

25 - transmitter control signal shaper

26 - transmitter control signal converter

27 - receiver control signal generation unit

28 - receiver control signal shaper

29 - receiver control signal converter

30 - terminal control unit

The controller circuit is functionally divided into two parts - a receiver and a transmitter. At the same time, the receiver and transmitter can work both independently (operating on different interfaces and at different frequencies), and in a dependent state (in this case, the control and clock signals of the transmitter are duplicated for the receiver), which allows the receiver and transmitter to use one control and one clock signal when the port works on one interface.

The external terminals TCLK, TCS, TD are respectively the conclusions of the clock, control signals and serial data of the transmitter, and the external terminals RCLK, RCS, RD are respectively the conclusions of the clock, control signals and serial data of the receiver. In the same configuration, they can be used in SPI mode, however, there is the possibility of flexible pin configuration, which allows the transmitter to use both TCS and RCS pins as a two-bit bus for selecting the slave SS [1: 0]. It is also possible to change the direction of the terminals TD and RD.

Directly, the transmitter unit 6 consists of a write buffer 7 made in the form of a FIFO and a counter 8-controlled bit 8 of the multiplexer 9, through which the transmitted bit is sampled.

A feature of the transmitter unit is that the data for transmission is selected directly from the write buffer 7. Such an organization allows receiving serial data at the output of the transmitter immediately after writing the transmitted word to the write buffer. The selection of bits for transmission over the serial interface is carried out from the write buffer through a multiplexer 9, controlled by the counter of bit 8. The counter is enabled by the TEN signal (transmission permission), reading from the write buffer is performed on the edge of the tclk clock signal with the enable signal ReadWB (read permission from the buffer) , counter reset is carried out by trst signal (transmitter counter reset).

The receiver unit 10 consists of a read buffer 11 made in the form of a FIFO, a receive register 12, an exchange logic 13 embedded between the receive register and a read buffer 11, as well as a bit counter 14 and a decoder 15. To determine the bit of the register into which the received data, a decoder 15 is used, controlled by the counter of bit 14. The counter is enabled by the REN signal (receive permission), the write to the read buffer is performed on the edge of the rclk clock signal, with the enable signal WriteRB (write permission to the read buffer), the counter is reset is triggered by the rrst signal (receiver counter reset).

The exchange logic 13, which is part of the receiver, performs zeroing or addition of the value of the senior bit of the excess bits. This avoids additional software processing and possible errors when receiving words less than the length of the reception register.

Also, the exchange logic performs the function of combining data from the receive register and the last received bit, the value of which is taken directly from the external output. This allows you to write the received data to the FIFO along the read edge for the last bit simultaneously with writing the last bit to the receive register, without waiting for the next edge of the clock signal.

The fact that the data for transmission is ready immediately after writing the transmitted word to the write buffer, and the received data is written to the read buffer at the same time as the last bit is written to the receive register, allows you to use the above-described transmit and receive blocks for working in any SPI, SPORT modes without modifications and I2S.

Sampling data through a multiplexer and recording using a decoder allows you to transfer words of arbitrary length with both the most significant and the least significant bit forward with minimal hardware costs.

The fact that the receiver and transmitter are controlled by six universal signals that are independent of the selected transmission protocol and are triggered by a fixed edge of the clock signal allows us to significantly simplify the logic of the receiver and transmitter and use the same blocks for transmitting data on different interfaces. It also allows you to use the clock and control signals without capturing them to the system clock, which as a result makes it possible to transmit with an external clock frequency equal to FCLK / 2, where FCLK is the frequency of the system clock.

The control registers 1, 3 allow independent programming of the transmitter and receiver.

The state registers of the transmitter and receiver 2, 4 contain information about the status of the read buffer and the write buffer, as well as interrupt flags.

Pin Management Register 5 contains bits that let you specify the direction of each pin.

Frequency dividers 16, 17 allow you to generate clock signals for the receiver and transmitter by dividing the frequency of the system clock.

The clock generation unit of the transmitter 18 consists of a clock multiplexer of the transmitter 19 and a clock converter of the transmitter 20.

The transmitter clock multiplexer allows you to use both an external clock signal and a clock signal received from the transmitter frequency divider to control the transmitter unit.

The transmitter clock signal inverts the clock signal when the transmitter needs to operate on a negative edge.

The clock generating unit of the receiver 21 consists of a clock multiplexer of the receiver 22 and a clock converter of the receiver 23.

The receiver clock multiplexer allows you to use both the clock signal received from the terminal control unit (which, in turn, can either be received from the external output or duplicate the transmitter clock signal) or the clock signal received from the receiver frequency divider to control the receiver unit.

The receiver clock signal inverts the clock signal when the receiver needs to work on a negative edge.

The use of clock converters allows the use of receiver and transmitter blocks in the circuit, which operate on a fixed clock edge.

The control signal generation unit of the transmitter 24 consists of blocks of a control signal generator of the transmitter 25 and a control signal converter of the transmitter 26.

The transmitter control signal generator, in accordance with the output settings, either generates a control signal for the selected interface (in this case, the clock signal received from the clock generation logic is used) or it is received from the external terminals of the circuit.

The transmitter control signal converter converts the interface control signal received from the transmitter control signal generator to three universal control signals: TEN (transmit permission), ReadWB (read permission from the write buffer) and trst (transmitter counter reset).

The transmitter control signal generation unit contains the logic for generating a two-bit slave select bus. In this case, the lowest bit of the bus is sent to the output of the control signal of the transmitter, and the senior bit to the output of the control signal of the receiver, thus allowing in full duplex SPI mode to work with two parallel connected slave devices.

The control signal generation unit of the receiver 27 consists of blocks of the control signal generator of the receiver 28 and the control signal converter of the receiver 29.

The driver control signal generator, in accordance with the output settings, either generates a control signal for the selected interface (in this case, the clock signal received from the clock generation logic is used) or it is received from the external terminals of the circuit.

The receiver control signal converter converts the interface control signal received from the receiver control signal generator to three universal control signals: REN (receive permission), WriteRB (write write buffer enable) and rrst (receiver counter reset).

The control signals generated by the control signal generation blocks for the receiver and transmitter are universal and do not depend on the selected transmission protocol. This allows the use of universal receiver and transmitter units in the circuit, which significantly simplifies the logic of the circuit. In addition, control signals are generated automatically, which allows the controller to transmit data without the participation of the processor.

The blocks for generating the control signals of the receiver and transmitter also contain the logic for automatically detecting the channel for operation in I2S mode, and the block for generating the control signals of the transmitter contains the logic for generating a two-bit signal for selecting the slave for full duplex SPI mode.

The controller includes two FIFO type buffers - a write buffer 7 and a read buffer 11. Both buffers are dual-port memory. In this case, one port is controlled by system bus requests, and the other by requests generated by the controller during the transfer. FIFO blocks also play the role of the only link between the two block domains: the receiver / transmitter and the system bus. This avoids synchronization problems when the device is in slave mode. In addition, both buffers allow you to write and read both words and half-words, which allows the port to work in the packing / unpacking mode.

The presence of read and write buffers allows to read already received data directly or to write data for a new transfer directly during transmission.

The terminal control unit 30 allows for flexible configuration of the terminals, setting the direction for each terminal, and duplicating the control and clock signals of the transmitter for the receiver. In addition, it is possible to redirect data from the output of the transmitter to the output of the receiver and from the output of the transmitter to the input of the receiver, which makes it possible to organize transmission in SPI mode both according to the Microwire standard (SDO, SDI) and Mototrola standard (MOSI, MISO). This block also contains logic that allows the entire controller to work in full duplex SPI mode, using the TCS and RCS pins to select two slaves, or in the independent SPI receiver and SPI transmitter mode. In the latter case, the receiver and transmitter can separately work both in the slave mode and in the master mode, using each of its own slave selection signal (TCS pin for the transmitter and RCS for the receiver).

In general, the receiver and transmitter can operate independently. However, it is possible for the receiver to operate in a transmitter-dependent mode.

If the transmitter is turned on and writing to the recording buffer has been made, then since the data for transmission is selected directly from the recording buffer, the first bit (or the last one, depending on the selected bit transmission order) of the transmitted word and the transmitter immediately appears on the output of the serial data of the transmitter ready for data transfer with the arrival of the first edge of the clock signal. The number of the transmitted bit is determined by the status of the transmitter bit counter. The counter is incremented along the edge of the clock signal when the "transmit enable" signal is set. If the value of the transmitter bit counter has become equal to the length of the transmitted word, then the counter is reset and the "Reading permission from the write buffer" signal is generated by the transmitter control signal generation unit, after which the next transmitted word appears at the output of the write buffer. The transmitter bit counter can also be reset by the “transmitter counter reset” signal, which is generated either when the transmitter is switched off programmatically or when a certain combination of external signals is detected (for example, switching to a high SS bus level in SPI mode).

If the receiver is turned on, then with the arrival of a negative edge of the clock signal, the received bit is written to the reception register. The bit number of the reception register to which recording will be made is determined by the status of the receiver bit counter. The counter is incremented along the edge of the clock signal when the "receive permission" signal is set. If the value of the receiver bit counter is one less than the length of the transmitted word, then the “Write Write Buffer Enable” signal is generated by the receiver control signal generation unit and with the arrival of the next negative edge of the clock signal, the last bit is simultaneously recorded in the reception register and all received words to the reading buffer. In the next measure, the counter is reset. The receiver bit counter can also be reset by the “receiver counter reset” signal, which is generated either when the receiver is switched off programmatically or with a certain combination of external signals (for example, switching to a high SS bus level in SPI mode).

The blocks for the generation of clock pulses and the generation of control signals of the receiver are used to control the receiver. The blocks for generating clock pulses and generating control signals of the transmitter are used to control the transmitter. The receiver and transmitter are independently configured.

At the output of the transmitter frequency divider, a clock signal is generated with a frequency equal to the frequency of the system clock signal divided by the value of the transmitter frequency divider. Further, if the direction of output of the clock signal is set as the output, then the signal from the output of the divider is supplied to the clock converter, the same signal is fed to the output of the clock signal TCLK, if the direction of the output of the clock signal is set as input, the clock is supplied to the input of the clock converter signal directly from the TCLK pin. If the port is programmatically configured to work on a negative edge or the SPI mode is selected, which assumes working on a negative edge, an inverted clock signal is generated at the output of the transmitter clock signal converter, otherwise the clock signal is transmitted to the output without changes.

The clock signal thus generated is transmitted to the transmitter unit and the transmitter control signal generation unit.

At the output of the receiver frequency divider, a clock signal is generated with a frequency equal to the frequency of the system clock signal divided by the value of the receiver frequency divider. If the clock duplication bit is set in the receiver control register, then the signal from the transmitter clock output is supplied to the receiver clock converter, otherwise, if the clock output direction is set as output, the divider output signal is sent to the clock converter, this the signal is fed to the RCLK clock signal output, if the direction of the clock signal output is specified as the input, then the clock signal Directly from RCLK output. If the port is programmatically configured to work on a negative edge or the SPI mode is selected, which assumes operation on a negative edge, an inverted clock signal is generated at the output of the receiver clock signal converter, otherwise the clock signal is transmitted to the output without changes.

The clock signal thus generated is transmitted to the receiver unit and the receiver control signal generation unit.

If the direction of the output of the control signal of the transmitter TCS is specified as the output, then the control signals are generated by the transmitter of the control signal of the transmitter and transmitted to the input of the Converter control signal of the transmitter and directly to the output of the control signal TCS. Otherwise, a signal taken directly from the TCS pin is fed to the input of the transmitter control signal converter. The control signal converter contains logic transforming the interface control signals supplied to its input to three universal control signals used to control the transmitter unit. In the case of operation in SPI mode, the control signal generation unit by multiplying the control signal received at the output of the transmitter control signal generator by the control register bits responsible for selecting the slave generates a two-bit slave selection bus. In this case, the lowest bit of the bus is sent to the output of the control signal of the transmitter, and the senior bit to the output of the control signal of the receiver, thus allowing in the full-duplex SPI mode to work with two parallel connected slaves.

If the control signal duplication bit is set in the receiver control register, then the signal from the control signal of the TCS transmitter is supplied to the input of the control signal converter of the receiver, otherwise, if the direction of the output of the control signal of the RCS receiver is specified as the output, then the control signals are generated by the driver control signal of the receiver and transmitted to the input of the Converter control signal of the receiver and directly to the output of the control signal RCS, if the direction in Water control signal RCS receiver is set as an input, the input control signal receiver transducer signal is taken directly from the output RCS. The control signal converter contains logic transforming the interface control signals supplied to its input to three universal control signals used to control the transmitter unit.

In SPI mode, the device can be used as a full-duplex SPI controller, while control signals are generated by the transmitter control signal generation unit and are duplicated for the receiver. In this case, the generation unit generates a “slave select” control signal, which is converted into a two-bit “slave select” bus, the lowest bit of the bus goes to the output of the TCS transmitter, and the second to the output of the RCS receiver (the direction of both outputs is specified as the output). To form a two-bit bus "slave selection", two bits of the transmitter control register are used, which contain information about which slave device is selected.

The invention according to this example can be implemented both in FPGAs, for example, firms Xilinx and Altera, and as part of VLSI microcontrollers and microprocessors.

Information sources

¹ http://www.freescale.com/files/microcontrollers/doc/ref_ manual / M68HC11RM.pdf

² http://www.national.com

³ http://www.analog.com/en/prod/0,2877,ADSP-BF537,00.html

⁴ http://www.nxp.com/acrobat_ download / various / I2SBUS.pdf

Claims (1)

A programmable serial bus controller containing a receiver unit consisting of a read buffer, a receive register, a bit counter and a decoder, a transmitter unit consisting of a write buffer, a bit counter and a multiplexer, a transmitter control register, a receiver control register for programmatically setting the transmitter and receiver , transmitter status register, receiver status register, containing information on the status of the read buffer and the write buffer and interrupt flags, the frequency divider of the transmitter, in One of which receives the system clock signal, and the output is connected to the input of the transmitter clock signal multiplexer of the transmitter clock generation unit, the output of which is connected to the input of the control signal generator of the transmitter control signal generation unit and the input of the transmitter unit, the receiver frequency divider, to the input of which the system clock signal is received and the output is connected to the input of the receiver clock multiplexer of the receiver clock generation unit, the output of which is connected to the input of the the driver signal control unit of the receiver control signal generation and the input of the receiver unit, the external outputs of the device: the external output of the receiver clock signal associated with the output of the receiver clock multiplexer, the external output of the transmitter clock signal associated with the output of the transmitter clock multiplexer, the external output of the receiver control signal associated with the output of the shaper of the control signals of the receiver, the external output of the control signal of the transmitter associated with the output of the shaper control signal transmitter, an external output of serial data of the receiver associated with the input of the receiver unit, an external output of serial data of the transmitter associated with the output of the transmitter unit, characterized in that the receiver unit further includes an exchange logic unit, the input of which is connected to the output of the receive register, and the output is connected to the input of the read buffer, the output of which is connected to the system bus, the input of the receiver unit is connected to another input of the exchange logic unit and the input of the decoder, the output of which is connected n with the input of the reception register, the control input of the decoder is connected to the output of the bit counter, the clock conversion block is included in the receiver clock generation block, the input of which is connected to the output of the clock multiplexer, and the output is connected to the output of the receiver clock generation block to the control signal generation block the receiver includes a control signal conversion unit, the input of which is connected to the output of the control signal driver, and the outputs on which control signals are generated from the counter "," permission to receive "and" permission to write to the read buffer "are connected respectively to the counter reset input, the counter operation enable input and the write enable input to the read buffer; the clock conversion block is included in the transmitter clock generation block, the input of which is connected with the output of the clock multiplexer, and the output with the output of the transmitter clock generation unit, the control signal conversion unit, the input of which is included in the transmitter control signal generation unit It is connected to the output of the driver of the control signal, and the outputs on which the control signals “counter reset”, “transmit enable” and “read permission from the write buffer” are generated are connected respectively to the counter reset input, the counter operation enable input and the buffer read enable input recording, the input of which is connected to the system bus, the output is connected to the input of the multiplexer, the output of which is connected to the output of the transmitter unit, the control input of the multiplexer is connected to the output of the bit counter, in the device circuit The terminal control unit is connected to the bi-directional external terminals of the clock and control signals of the transmitter, the clock and control signals of the receiver, the bi-directional external terminals of the serial data of the transmitter and receiver, the input and output of the receiver clock signal generating unit, the input and output of the transmitter clock signal generating unit, the input and output of the receiver control signal generation unit, the input and output of the transmitter control signal generation unit, the output of the serial data of the transmitter unit, the input of the serial data of the receiver unit, an additional connection is established between the serial data output of the transmitter unit and the external serial output of the receiver, an additional connection is established between the serial data input of the receiver unit and the external serial output of the transmitter, an additional connection is established between the high-order output two-bit control signal of the driver of the control signal of the control signal generation unit transmitter with an external output of the control signals of the receiver.