RU2305374C1 - Method for hybrid commutation and adaptive routing and device for realization of the method - Google Patents

Abstract

FIELD: computer networks.

SUBSTANCE: in accordance to invention, in set up connection phase the message is recorded in common memory, message length is measured and compared to threshold value. If the length of message exceeds threshold value, then the message is transferred in channel commutation mode, in opposite case the message is divided onto packets, rewritten to buffer memory and transferred in packet commutation mode via channels with maximal throughput in accordance to routing table. Method is realized on computer engineering elements, comparison circuit, control trigger and electronic keys, information inputs of which are connected to common memory, and controlling inputs - to trigger outputs. In original condition, packet commutation mode is used, and change of mode is realized by transfer of trigger to second stable condition from output of comparison circuit.

EFFECT: increased efficiency of network resource usage and improved time-probability characteristics of information exchange.

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Description

FIELD OF THE INVENTION

The invention relates to the field of computer networks, in particular to a method of hybrid switching and adaptive routing, and can be used in the design of digital integrated service networks.

State of the art

A known method of hybrid switching, based on the integration of switching equipment necessary for the implementation of each switching method: channels and packets. A feature of this method is that the redistribution of resources between switching modes is carried out by the central processor (see Jenny Christian J. Kummerle Karl, Burge Helmut. Network node With integrated circuit / Pachet Switching capabilities. "Communes, - Network Eur. Comput. Conf., London, 1975. Oxbridge 1975, 207-228).

However, when the channel switching mode is established, the information flow is controlled without the participation of the central processor. This means that the transition from one switching mode to another occurs without taking into account the current state of the network, which can lead to its blocking, or to unjustified denial of service, or to inefficient use of network resources when transmitting long messages. In addition, the transmission of long messages in packet switching mode will inevitably lead to a violation of the time scale.

A known method of hybrid switching, allowing you to switch channels in synchronous circuit mode (channel switching) and in synchronous and asynchronous packet mode (packet switching). This method is based on the use of time sharing between subscribers, and the access time interval is assigned to different subscribers in the packet switching mode, which limits the required RAM memory of the switching centers (see EPO Patent (EP) A1, No. 0403911, class H04L 12/64, 1991).

However, this method does not provide efficient use of communication channels, since with such control there are pauses between the moment the message was sent and the moment the sender issued the next message.

The closest in technical essence to the method chosen as a prototype is the adaptive switching method based on the organization of connections in the channel switching mode on the network with the simultaneous transmission of messages in the packet switching mode. With this method, the bandwidth of the network paths is redistributed between the message flows transmitted in both modes. The algorithms provide the ability to download pauses that occur when using the channel switching mode. Messages are recorded in shared memory and transmitted by successive blocks of fixed length (frames), and the transmission time of frames in all paths is the same regardless of the available bandwidth, which leads to inefficient use of communication channels.

The packet processing processor analyzes the packets formed in the memory and determines their further route according to the routing tables.

The block diagram of an adaptive switching unit contains an input processor, shared memory, a subscriber interaction processor associated with the shared memory, a packet processing processor, the input of which is connected to the output of the shared memory, and the output with the input of the control processor, the outputs of which are connected to the inputs of the input processor, processor interaction with subscribers, and the output processor associated with the input with shared memory, the output buses of which are inputs of the output paths (see Samoilenko S.I. Adaptive switching method // Electr. freeze. - 1981. - No. 6).

The disadvantage of this device is the low efficiency of using the bandwidth of the output paths.

Disclosure of invention

The objective of the invention is to develop a method of hybrid switching and adaptive routing and devices for its implementation, increasing the efficiency of using output paths and improving the probabilistic-temporal characteristics of information exchange.

The technical result that can be achieved using the present invention is to increase the efficiency of the use of output paths and improve the probability-time characteristics of information exchange.

The technical result is achieved using the method of hybrid switching and adaptive routing, in which, in the phase of establishing a connection, information about the address of the called message is received and the message is recorded in the shared memory, the message length L is measured and compared with the threshold L _p , and if the message length exceeds the threshold value L> L _p , then a physical connection is established and the transmission is carried out in the channel switching mode, and with a message length L <L _{p the} message is divided into packets, rewritten in a buffer pa wrinkle and transmit in packet switching mode on channels with maximum throughput in accordance with the routing table.

Since the message length is critical in this method, and the buffer volume is strictly dosed and is selected according to the conditions of solving the network optimization problem by the minimum average delay time, it is impractical to break messages whose length exceeds a certain value L _p into packets, since this will lead to a worse probability -time characteristics of information exchange. Sending packets on routes that have the maximum throughput will lead to a quick release of buffers.

The technical result is achieved using a hybrid switching device and adaptive routing, comprising a subscriber interaction processor and a control processor associated with the shared memory, as well as an output processor, while a computing device, a comparison circuit, a control trigger and the first and second electronic keys are introduced into it whose control inputs are connected to the inverse and direct outputs of the control trigger, the unit input of which is connected to the output of the comparison circuit, and the installation input is zero connected to the first output of the control processor, the second output of the control processor through the computing device is connected to one input of the comparison circuit, the other input of which is connected to the third output of the control processor and the third output of which is connected to the control input of the output processor, while the output of the shared memory is connected to information inputs keys, the outputs of which are connected to the information inputs of the output processor, connected by the outputs to the output paths.

Thanks to these features, the device stores the message, measures its length in the control processor and compares it with the critical length generated by the computing device, and further switches the switching modes using, for example, a control trigger.

Brief Description of the Drawings

Figure 1 shows a structural diagram of a device for implementing the proposed method.

Figure 2 shows graphs explaining the algorithm for implementing the method.

The implementation of the invention

The device comprises a subscriber interaction processor 1 and a control processor 2 associated with a common memory 3, as well as an output processor 4 connected by a control input to the first output of the control processor 2, a computing device 5 connected by an input to the second output of the control processor 2, and the output with one of the inputs of the comparison circuit 6, the other input of which is connected to the third output of the control processor 2, the control trigger 7, the unit input of which is connected to the output of the comparison circuit 6, and the installation input is zero Din with the fourth output of the control processor 2. The direct and inverse outputs of the control trigger 7 are connected to the control input of the first and second electronic keys 8 and 9, respectively, and the information inputs are connected to the output of the shared memory 3. The outputs of the electronic keys 8 and 9 are connected through the output processor 4 to the output paths 10.

In this device, the subscriber interaction processor 1 is part of a system that performs the procedure for access of subscriber complexes to the core data exchange network, which are determined by the protocols of work on the data transmission path. The control processor 2 controls the processes of writing (reading) information into memory, registers the address and length of the message, determines the direction of transmission of the message, and also has information about the status of buffers and output paths. The output processor 4 solves the problems of addressing and routing messages. The control processor 2 and the output processor 4 can interact over the network with neighboring switching nodes or with a common routing center when implementing centralized adaptive routing. Computing device 5 solves the problem of calculating the threshold L _p based on data received from the control processor.

Examples of specific implementation of the method of hybrid switching and adaptive routing

Example. In an example implementation of the circuit, computing device 5 is an identification unit, a threshold value of L _p can be calculated by the formula

where L _cr - the critical message length specified for a particular network as a result of solving the optimization problem;

m is the total amount of buffer memory;

m ₃ (t) is the current value of the occupied amount of buffer memory;

- производная по времени от занятого объема памяти;

- time derivative of the occupied memory;

β is the coefficient of proportionality.

In this case, only information about the state of this node (the used amount of buffer memory) is used. The time derivative of the occupied amount of buffer memory takes into account the trend in buffer memory and depends on the change in the schedule.

If the true message length is expressed in units of voltage U, then it is fed to one of the inputs of the comparison circuit (comparator) 5, to the other input of which the quantity

where k is the coefficient that converts the threshold message length to voltage. If the message length L _p is expressed in bits, then k in dimension represents the value [volt / bit].

Comparison scheme 6 goes into the second stable state if U> U _p . The high potential that appears at the output of the comparison circuit will trigger 7 on the second long-term stable state, while at its direct output the potential will become high, which will lead to the opening of the second key 9. As a result, the channel switching mode will be implemented.

The trigger 7 is returned to its original state at the command of the control processor 2 by supplying a single pulse to the input of the installation to zero. In the future, the packet switching mode will be carried out until the voltage U at the output of the control processor 2 exceeds a threshold value U _p generated at the output of the computing device 5.

The device implements local adaptive routing. The information necessary to make a decision on the direction of transmission is:

1. Preloaded routing tables.

2. Information about the current state of the output paths.

3. Data of packet queues awaiting transmission on each channel.

Information about the state of other network components by the host is not used.

The output device 4 calculates the current weight of the branch

V _Ti = V _i + m _bi ,

and then determines the probability P _i with which the connected processor 9 should open packets in the i-th direction

where n is the number of branches into which the message can be sent;

V _i - a priori weight of the branch, for example, in units of throughput;

m _bi - the amount of free buffer memory (measured in the number of packets that can still be stored in the buffer).

It is advisable to forward packets to the i-th branch, for which

To avoid trigger jumps, the connected processor (output processor 4) can distribute packets into branches in accordance with the calculated probability values. In the first case, packet transmission over a virtual channel is implemented; in the second, the datagram method is used.

The use of local information about the state of the switching node is justified by the fact that the optimization result at the network level allows us to determine the values of the information flows F _ij of the channel throughputs V _ij , the total number of channels n _i and the buffer volume for each node m _i . In this case, it is enough to solve one of the equations (see Fomin L.A., Budko P.A. et al. Optimization of the bandwidth of W-ISDN links with limited network resources // Elektrosvyaz. - 2002. - No. 2):

where the form of the function is determined by the relation

Optimization by χ _ij allows you to vary the values of V _ij and n _ij depending on the class of the graph (F _ij ), choosing any set of channels with a variable width of bit rates, forming each time a virtual channel with variable bandwidth and maintaining the values of probability-time characteristics ( minimum average message delay time and probability of denial of service due to lack of free places in the buffer) at a given level.

An example of a numerical calculation of the implementation of the hybrid switching method and adaptive routing and a device for its implementation. The advantages of the invention in comparison with the prototype and other known technical solutions can be determined from the diagrams depicted in figure 2. Here are combined dependency graphs.

which are nomograms for graphical solutions to network problems and can be used to quantify the benefits of the proposed hybrid switching method.

The analysis shows that the main qualitative indicators of the network in the optimal case depend on the number of channels n in the selected direction of transmission and the number of buffers m at the entrance to each channel, and for optimality, the values of n, m should be strictly dosed and issued in software. For example, with the number of channels n = 4 and m = 15 (see the 3rd quadrant), the optimal value of the channel load factor is χ = 0.55.

This means that the stream transmitted over the network reaches F ₁₂ = 20 Mbit with a throughput of V = 36 Mbit. If it is necessary to transmit a message with a length of L = 795 bytes, then the volume of the buffer m = 15 is sufficient to split the message into 15 parts and place them in the buffer memory (one ATM cell is 53 bytes) without violating the optimality.

If the transmitted message is longer, for example, L = 1166 bytes, then 22 buffers are required to write them, which will lead to a decrease in the channel load factor χ = 0.43, and, therefore, resource efficiency will decrease by 22%.

An attempt to keep the channel load factor at the same level will increase the average delay time (curve A in the first quadrant). At the minimum point, the delay time is T = 10 ms, while when shifted upward, it gives a delay time of T = 13 ms, which leads to an increase in the delay time by 30%.

Thus, the stated objective of the invention is to increase the efficiency of the use of output paths and to improve the probability-time characteristics of information exchange — achieved by using the proposed method.

The invention in comparison with the prototype and other known technical solutions has the following advantages:

- improving the efficiency of using channels on the network;

- improving the efficiency of the use of memory buffers in the switching nodes of the network;

- reducing the time delay of packets on the network;

- determination of the optimal switching mode on the network;

- varying the bandwidth, channels and the number of buffers depending on the class of the graph, choosing any set of channels with a variable width of bit rates, forming each time a virtual channel with a variable bandwidth and maintaining the values of probability-time characteristics at a given level.

Claims (2)

1. A method of hybrid switching and adaptive routing, comprising the phase of establishing a connection with receiving information about the address of the called message and writing the message to the shared memory, characterized in that the message length L is measured and compared with the threshold L _n , and if the message length exceeds the threshold value L > L _n, the physical connection is established and the transfer is in the mode of circuit switching, and when the message length L <L _n - the message is broken into packets, rewritten in the buffer memory and transferred to the regime ommutatsii packets through the channels with the maximum capacity in accordance with the routing table. 2. A hybrid switching and adaptive routing device, comprising a subscriber interaction processor performing a procedure for accessing subscriber complexes to a core data exchange network, a control processor for managing memory, registering address and message length, determining a message transmission direction, having information about the status of buffers and output paths associated with shared memory, as well as an output processor for addressing and routing messages, connected by a control input to the first output a control processor, characterized in that a computing device for calculating the threshold L _n is connected thereto, connected by an input to the second input of the control processor, and by an output to one of the inputs of the comparison circuit, the other input of which is connected to the third output of the control processor, control trigger, input installation to the unit of which is connected to the output of the comparison circuit, and the input of the installation to zero is connected to the fourth output of the control processor, the first and second electronic keys, the control inputs of which are connected to inverse and direct the outputs of the control trigger, respectively, while the output of the shared memory is connected to the information inputs of the keys, the outputs of which are connected to the information inputs of the output processor, connected by the outputs to the output paths.

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