RU2290706C1 - Cache memory reading device - Google Patents

Abstract

FIELD: computer engineering; data processing devices; reduced instruction set microprocessor systems.

SUBSTANCE: cache memory reading device contains address forming unit, pipeline latches 1A, 1B, 2A, 2B, address conversion unit, data memory, tags memory, comparison unit, control unit with two outputs, and timing pulse generator with two outputs.

EFFECT: increased performance of pipeline microprocessor system with reduced instruction set, reduced time of cache hit flag generation, and reduced power consumption.

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Description

The invention relates to computing, in particular to data processing devices, and may find application in microprocessor systems with a reduced set of instructions.

A device for reading from the cache, for example, contained in the microprocessor 79R3081 company IDT (USA). The specified device includes an address generation unit, conveyor latch registers 1A, 1B, 2B, an address conversion unit, a data memory, a tag memory, a comparison unit, a control unit and a clock generator, wherein the output of the address generation unit is connected to the input of the conveyor register latch 1A whose output is connected to the address conversion unit, the output of the address conversion unit is connected to the input of the conveyor register-latch 1B, the output of which is connected to the address inputs of the data memory and tag memory and to the input of the compare a signal to the other input of which the output of the tag memory is connected, the output of the comparison unit and the output of the data memory are connected to the input of the 2 V latch conveyor register, the output of the control unit is connected to the control inputs of the data memory and tag memory, the synchronization of the circuit is set by the clock generator, which has two output, (see "The IDT79R3071, IDT79R3081 RISC Controller Hardware User's Manual" Revision 2.0 April 4, 1994).

A disadvantage of the known device is that a signal from the output of the latch register 1 V is supplied to the address inputs of the data memory and the tag memory, thus leaving a period of time of only two phases for reading from the tag memory and comparing the contents of the tag memory with the physical address received from the output of the latch register 1B, which does not allow to increase the speed of the microprocessor system as a whole.

Closest to the patented cache reader is a device that is part of the 64-bit microprocessor 79RC64574 / 64575. The cache reader includes an address generation unit, 1A, 1B, 2V conveyor register-latches, an address conversion unit, data memory, tag memory, a comparison unit, a control unit and a clock with two outputs, and the output of the address generation unit is connected to the input of the conveyor register-latch 1A, the output of which is connected to the input of the address conversion unit and to the address inputs of the data memory and tag memory, respectively, the output of the address conversion unit is connected to the input of the conveyor register-latch 1B, the output of which is connected to the input of the comparison unit, the output of the tags memory is connected to another input, the data memory output is connected to the input of the latch conveyor register 2B, the output of the comparison unit is connected to the other input, the output of the control unit is connected to the control inputs of the data memory and memory tags, the timing of the circuit is set by the clock generator, which has two outputs, one output of the clock generator is connected to one of the inputs of the control unit and the input of the register 1A, and the other output of the generator clock pulses connected to another input of the control unit and the inputs of the registers 1B and 2B. In this device, the indexing of data memory and tag memory is carried out by the virtual address, i.e. on the output of register 1A, which is formed one phase earlier than the physical address. This solution allows you to eliminate the address translation time from the critical path of the pipeline at this stage. The data memory and tag memory parameters are the same and the timing diagram of accessing the data memory and tag memory is also the same. This approach is easier to implement technically, since the memory is built on cells of the same type. In addition, with a single timing diagram, the control scheme for two types of memory is much simpler (see "79RC64574 / 64575 User Reference Manual", Version 1.0 April 2000 http://www.idt.com/docs/79RC64574_MA_63402.pdf).

However, this approach of simultaneous reading has a drawback: since, from the point of view of the microprocessor logic, the contents of the tags memory should be much earlier than the contents of the data memory, since the contents of the tags are used by the comparison unit to form a sign of getting into the cache memory. With this approach, performance requirements are automatically imposed on both compact and fast tag memory and data memory, which are significantly larger in volume, which leads to increased power consumption and footprint and is a limiting factor in speed.

The objective of the invention is to increase the speed of the conveyor system of the microprocessor with a reduced set of instructions and reduce power consumption.

The technical result is the separation of the read cycles of the data memory and the memory tags of the microprocessor cache memory, which allows you to form a sign of getting into the cache memory half a phase faster than the contents of the data memory will be available while reducing the requirements for the speed of the data memory.

The aforementioned task and technical result are achieved in a reader from the cache memory, including an address generation unit, conveyor register latches 1A, 1B, 2A, 2B, an address conversion unit, data memory, tag memory, a comparison unit, a control unit and a clock with two outputs, and the output of the address generation unit is connected to the input of the conveyor register-latch 1A, the output of which is connected to the input of the address conversion unit and to the address inputs of the data memory and tag memory, respectively, the output of the conversion unit address is connected to the input of the conveyor register-latch 1B, the output of which is connected to the input of the comparison unit, the output of the tags memory is connected to the other input, the output of the data memory is connected to the input of the conveyor register of the latch 2B, one output of the clock generator is connected to one of the inputs of the block control and inputs of registers 1A and 2A, and the other output of the clock generator is connected to another input of the control unit and the inputs of registers 1B and 2B, the control unit has two outputs, one of which is connected to the memory input data, and the other to the tag memory input, and the output of the comparison unit is connected to the input of the conveyor register-latch 2A.

The accelerated formation of the flag of getting into the cache memory allows to reduce the time of formation of the stop signal of the pipeline, which allows to increase the clock frequency of the entire pipeline. At the same time, reducing the speed requirements for data memory will reduce power consumption and the footprint of this unit.

To accomplish the stated tasks and technical result, the cache reader provides the formation of a cache hit signal and writes it to the pipeline register latch by the second signal phi_A and reads the contents of the data memory and writes it to the pipeline register latch by the second signal phi_B from the moment of formation addresses.

Figure 1 shows a block diagram of a patented cache reader.

Figure 2 - block diagram of the address translation.

Figure 3 - the shape of the clock pulses.

Figure 4 is a timing diagram of the operation of reading cache memory by a patented device.

A cache reader contains the following nodes:

1 - block forming the address,

2 - conveyor register latch 1A,

3 - block address translation,

4 - conveyor register latch 1 V,

5 - block comparison

6 - conveyor register latch 2A,

7 - tag memory,

8 is a clock generator,

9 - control unit,

10 - data memory,

11 - conveyor register latch 2 V,

moreover, the output 12 of the address forming unit 1 is connected to the input 13 of the conveyor register-latch 1A position 2, the output 14 of which is connected to the input 15 of the address translation unit 3 and to the address inputs 16 and 17 of the data memory 10 and the tag memory 7, respectively, the output 18 of the conversion unit address 3 is connected to the input 19 of the conveyor register-latch 1 To position 4, the output 20 of which is connected to the input 21 of the comparison unit 5, the output 23 of the tag memory 7 is connected to the other input 22, the output 24 of the data memory 10 is connected to the input 25 of the latch conveyor 2 to position 11 , the synchronization of the circuit is set by the clock generator 8, which has two outputs 26 and 27 connected to the inputs 28 and 29, respectively, of the control unit 9, as well as to the inputs 30 and 31 of registers 1A and 2A of position 2 and 6, and with inputs 32 and 33 registers 1B and 2B of positions 4 and 11, respectively, control inputs 34 and 35 of data memory 10 and tag memory 7 are connected to separate outputs 36 and 37 of control unit 9, respectively, and output 38 of comparison unit 5 is connected to input 39 of the conveyor register latches 2A position 6.

The address generation unit 1 is designed to generate a virtual address by which it is necessary to read the contents of the cache memory, and consists of a 32-bit counter. The output of the address generation unit is a 32-bit address from the virtual address space of the microprocessor.

The conveyor register-latch 2 is designed to keep the 32-bit virtual address in a stable state during phase 1B by latching the input signal on the trailing edge of the phi_A signal in cycle 1, and consists of a 32-bit register of the latch type.

The address translation unit 3 is intended for generating a 32-bit physical address based on a 32-bit virtual address. The block consists of 64-line fully associative memory. The scheme and principle of operation of the address translation unit are described in J. Hennesy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publisher, Inc., San Francisco, CA, Second edition, 2001, chapter 5.

The output of the address translation unit is a 32-bit physical address.

The conveyor register-latch 4 is designed to keep the 32-bit physical address in a stable state during phase 2A by latching the input signal on the trailing edge of the signal phi_B in step 1, and consists of a 32-bit register of the latch type.

Comparison block 5 is designed to compare the upper 20 bits of the physical address with the contents of the tag memory and consists of a 20-bit comparator. In case of coincidence, the comparison unit generates an active TagEq signal level.

The conveyor register latch 6 is designed to keep the TagEq address match signal in a stable state during a 2 V phase by latching the input signal along the trailing edge of the phi_A signal in cycle 2, and consists of a 1-bit latch register.

Tag memory 7 is a standard asynchronous memory with a capacity of 4 KB and a word width of 20 bits. The memory is designed to store tags. In this scheme, increased performance requirements are placed on the memory. The tag memory output is a 20-bit Tag bus.

The clock generator 8 is designed to generate clock signals phi_A and phi_B. The waveform of these signals is shown in FIG. It should be noted that the time interval between active high levels of phi_A and phi_B signals is at least 1 ns.

The control unit 9 is designed to generate control signals to read the tag memory and data memory. The algorithm for generating reference signals provides the reading of the contents of tags earlier than the contents of the data memory. The block is built on the basis of a programmable logic matrix (PLM). The output of the block is the signals for reading the data memory D_Rd and reading the memory of the Tag_Rd tags.

Data memory 10 is a standard 4 KB asynchronous memory with a 32-bit word width. The memory is intended for data storage. In this scheme, the memory does not have performance requirements, which reduces power consumption and footprint. The tag memory output is a 32-bit Data bus.

The conveyor register-latch 11 is designed to keep the Data bus in a stable state during phase 3A by latching the input signal along the trailing edge of the signal phi_B in step 2, and consists of a 32-bit register of the latch type.

The reader from the cache works as follows. During phase 1A, the address generating unit 1 generates an address based on the previous value by increasing it by 4. The output 12 of the address generating unit 1 goes to input 13 of the latch register 1A, position 2, which ensures the stability of the virtual address VA during phase 1B. Next, the senior bits [31:12] of the virtual address VA are input 15 of the address translation unit 3, where they are converted into physical addresses of the RA in accordance with the circuit depicted in figure 2. The lower 12 bits [11: 0] of the virtual address VA are supplied to the address inputs 16 and 17 of the data memory 10 and the tag memory 7, respectively. During phase 1 B, the virtual address of VA is converted to a physical RA in address translation unit 3, and the reading cycle of tag memory 7 and data memory 10 starts. By the end of phase 1 B, a physical address is generated at the output 18 of address 3 translation unit, which arrives to input 19 and latches into latch register 1B, position 4, which ensures the stability of the physical address during phase 2A. In the same phase, the control unit 9 at the output 37 generates an active state of the Tag_Rd signal, which allows the contents of the tag memory 7 to be transmitted to the 20-bit Tag bus, which connects the output 23 of the tag memory to the input 22 of the comparison unit 5, to the other input 21 of which the older bits of the physical address of the RA. The comparison unit 5 generates an active signal Tag_Eq, if the contents of the tag memory 7, read in this cycle, coincides with the upper bits of the physical address. The signal Tag_Eq must be received at the input 39 of the register of the latch 2A, position 6 until the end of phase 1A in order to be available for further processing in phase 2B. Also, during phase 2B, the control unit 9 generates a signal D_Rd, which allows the contents of the data memory 10 to be output to the 32-bit Data bus, which connects the output 24 of the data memory to the input 25 of the register-latch 2B, position 11, by the time the phase 2B ends to be available for further processing in phase 3A.

Claims (1)

A cache reader containing an address generation unit, conveyor latch registers 1A, 1B, 2A, 2B, an address conversion unit, a data memory, a tag memory, a comparison unit, a control unit and a clock with two outputs, the output of the unit the address generation is connected to the input of the conveyor register-latch 1A, the output of which is connected to the input of the address conversion unit and to the address inputs of the data memory and tag memory, respectively, the output of the address conversion unit is connected to the input of the conveyor register-z 1B slots, the output of which is connected to the input of the comparison unit, the tag memory output is connected to the other input, the data memory output is connected to the input of the conveyor register of the latch 2B, one output of the clock generator is connected to one of the inputs of the control unit and the inputs of registers 1A and 2A, and the other output of the clock generator is connected to the other input of the control unit and the inputs of the registers 1V and 2B, characterized in that the control unit has two outputs, one of which is connected to the input of the data memory, and the other to the input of the tag memory s, and the output of the comparison unit is connected to the input of the conveyor register-latch 2A.

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