RU2269199C2 - Pulse counter - Google Patents

Abstract

FIELD: digital computer engineering.

SUBSTANCE: proposed pulse counter that can be used for digital automation and control of various processes and is designed to execute various logical operations (left shift of one codes, subtraction of pulses, code inversion, and reception of ones in all counter bits) has RS flip-flop, three AND gates, three NOT gates, three OR gates, and three control buses in each bit.

EFFECT: enhanced speed, reduced hardware and power requirement in steady state operation.

2 cl, 1 dwg

Description

The invention relates to the field of digital computing and automation.

The known pulse counter (hereinafter referred to as the object), constructions based on triggers with a counting input (see. I. Bukreev, B. M. Mansurov and V. I. Goryachev. Microelectronic circuits of digital devices, 1973, "Sov. Radio", p. 137, Fig. 5.1). The disadvantage of this object is the counting trigger, which includes elements of the time delay of the counting pulses, which reduces the speed of its work and complicates the manufacturing technology of the trigger and increases the requirements for the formation of the parameters of the counting pulses (edge steepness, duration and other parameters).

Also known is an object made on the basis of only three logical elements (LE) AND, OR, NOT, which eliminates the shortcomings of the above device (see ibid., Pp. 135-150, Fig.5.7). In the named object, triggers are assembled based on (ЛЭ) AND-NOT or OR-NOT (RS-triggers). This object is the closest prototype to the proposed object.

The object proposed for the prototype contains main and auxiliary registers based on RS triggers, AND, OR, NOT logic elements and a counting pulse bus connected to the first inputs of the first and second elements AND the least significant bit of the object.

Its disadvantages are: relatively low speed, determined by the total propagation time of the maximum end-to-end transfer and switching of two RS-flip-flops, a significant amount of equipment, determined by the total number of inputs of logic elements (Quine Price), relatively high power consumption and only one pulse counting operation.

The aim of the invention is to eliminate the disadvantages of known objects, namely: increasing the speed of work, expanding the list of operations, reducing equipment and power consumption by the object.

For this, each binary bit contains one RS-trigger, three AND elements, three NOT elements and one OR element, a counting pulse bus, while the outputs of the first and second elements AND are connected to the inputs of the first and second elements NOT, the outputs of which are connected to "zero "and the" single "inputs of the RS-trigger, the" single "output of which is connected to the first input of the first OR element, and its output is connected to the first input of the third AND element, its second input is connected to the" single "RS-trigger input, and the third input third element And connected to the bus potential To transfer the signal from the first least significant bit, the output of the third AND element is a potential transfer bus entering the first senior bit and is connected to the input of the third element NOT and to the first input of the first AND element of this discharge, the second input of this AND element is connected to the bus of counting pulses, the output of the third element is NOT connected to the first input of the second element And, the second input of the second element And is connected to the output of the first element And the first low order.

A distinctive part of the claims consists in introducing a second OR element and a second control bus to carry out an additional operation in each bit of the object, while the control bus is connected to the first input of the second OR element, and the potential transfer bus from the first low order is connected to its second input, the output of the second element OR is connected to the third input of the third element I.

A distinctive part of the claims consists in introducing a third OR element and a third control bus in each discharge of the object to perform the second additional operation, the bus being connected to the first input of the third OR element, the output of the first element And the first low order bit connected to the second input of this element OR is connected to the second input of the second AND element of this category, as well as in the introduction of a code reception bus into each bit of the object with its connection to the third input of the third OR element.

The proposed facility allows to increase the speed of work, reduce the number of logical elements, expand the list of operations and reduce energy consumption.

The speed of the pulse counting operation is achieved by eliminating the time from the work cycle for switching the second RS-trigger, which is absent in the proposed object. If in the prototype the total counting time of one pulse is

Here n is the number of binary bits of the object,

τ is the time delay of one AND element (one OR element),

ttr is the switching delay time of one RS trigger,

t and - the duration of the counting pulse,

tp - the duration of the pause between pulses.

We assume that 2nτ = ti, tp = ti, ttr = ti

In the proposed facility, the counting time of one pulse is determined by this ratio

Comparing relations (1) and (2), it is seen that the counting time of one pulse was reduced by approximately 30%. There is one more advantage of the object, which consists in the fact that the result of counting pulses recorded in RS-triggers after the arrival of each counting pulse appears after a time equal to t, i.e. after the time of switching one trigger. In the prototype, this time is 3t. (Note that this time delay in the passage of information when counting a single pulse is similar to the so-called “backlash” in mechanical counters).

The indicated advantages of the object are achieved in that a potential transfer signal is generated during a pause between the counting pulses, and the bus of the counting pulses is connected to the first inputs of the first elements AND of all binary bits.

Decrease in the total number of inputs of logic elements, i.e. a decrease in the equipment of the device by approximately 15% is determined by the exclusion from the composition of the equipment of the second trigger register.

Expanding the list of operations (shifting unit codes, inverting codes, subtracting impulses, receiving units into all bits of the counter) is achieved by introducing two OR elements and two control buses to the equipment of the object. The code shift operation of individual units (101001 ...) allows you to use the object as a pulse distributor, i.e. sequential switching of triggers and the issuance of appropriate potentials to control other electronic devices, blocks, circuits. This operation is performed by including a second OR element and a second control bus in the equipment of the facility. The operation of inverting the codes in the register allows you to develop a control potential using the through transfer scheme when any given number is received in the counter. This operation is performed by using the third OR element and the third control bus. The operation of receiving units in all digits simultaneously allows you to generate a control signal upon receipt of the first counting (or first command) pulse. This uses the third element, the third control bus.

Power consumption is achieved by eliminating one RS trigger. In the prototype, in each binary digit, the consumed current is 2I (I is the current of the open element NOT). In the proposed object, depending on the presence and absence of the transfer signal, the potential current can be equal to 2I or I. The average value is 1.5I, thus, there is a decrease in current consumption by about 25%.

To explain the operation of the described object, the drawing shows a functional diagram of its two binary digits.

In the drawing, the following notation:

1, 2, 3 - elements And;

4, 5, 6 - elements NOT;

7, 8, 9 - elements of OR;

10 - RS-triggers;

11 - bus counting pulses;

12 - bus pulse transfer from the least significant to the first senior;

13 - a bus of potential end-to-end transfer from a low order to a high order;

14 - bus potential control operations shift unit and invert;

15 - bus pulse control inversion;

16 - trigger output bus.

17 is a numerical code reception bus.

The proposed object is as follows.

In each category of the counter, the first inputs of I1 are connected to bus 11, the second inputs are connected to input HE6 and output I3, the output of the mentioned element And is connected to inputs HE4, OR7, i-th category and input OR9 of i + 1-st category, output HE4 connected to the "zero" input of trigger 10. The first input I2 is connected to output HE6. The second input I2 is connected to the output OR9, the first, second and third inputs of which are connected to the buses 15, 17 and 12. The output I2 is connected to the input HE5, the output of which is connected to the "single" input of the trigger 10 and to the second input I3. The second input OR7 is connected to a single output of the trigger 10, and the output of this element is connected to the first input And3. The first input OR8 is connected to the bus 14, its second input is connected to the bus 13, and its output is connected to the third input And3. Output I3 is connected to input HE6 of the i-th category and OR8 i + 1-th category. Consider the principle of operation of the object when performing the entire list of operations.

Operation "addition of impulses". In the initial position, all the triggers store the code "0", the potential of the count command is applied to bus 13. In the first category of the object tires 11 and 12 are combined. The first counting pulse on the circuit OR9, I2, NOT5 is fed to the "1" input Tr10 and to the second input I3. Thus, for the duration of the counting pulse, the passage of signals through I3 to bus 13 and input HE6 is prohibited. After Tr10 is switched to unity, its potential through OR7 enters the first input of I3, but does not pass to the senior discharge. The trigger 10 stores the code "1". After the expiration of the time equal to the duration of the counting pulse (ti), a potential corresponding to the code "1" appears at 1, 2 and 3 inputs of I3, i.e. the transfer signal, which also goes to the inputs I1, NOT6 of the first category, enters the senior bit.

The second counting pulse on the bus circuit 11, I1, HE4 is fed to the “0” input Tr10 of the first category and sets it to “0” and through the circuit OR9, I2, HE5 is fed to the “1” input Tr10 of the second category and sets it to “unit " Since HE5 “forbade” the transfer to the third digit, the transfer signal, even after Tr10 switches to “1”, will not pass to the indicated digit. After the counting pulse ends, I3 will be prepared for the passage of the transfer signal received on the bus 13.

The third counting pulse sets Tr10 of the first discharge to "1" and, after its end, during the period between the pulses, the transfer potential along the I3 circuit of the first discharge, OR8, I3 of the second discharge will go to the bus 13 of the third discharge. Further, the pulse counting is performed similarly to that considered.

Operation "shift codes individual 1". (Here we will talk about bits with "units", in the nearest higher and lower bits which are always "zeros", i.e. 101001010 ...... 10). Suppose, in the initial position, the code “1” is entered in the first bit of the counter, for example, via bus 12, 15 or 17. In all other bits, Tr10 is in position “0”. A sign of the operation of shifting the codes of individual "1" is the potential received on the bus 14. In those bits in which the code "1" is stored, the potential of the bus 14 via the I8, I3 circuit is fed to the input I1 and HE6. The shear pulse received on the bus 11, through the circuit of elements I1, HE4 will go to the "zero" input Tr10 and set it to "0". At the same time, this impulse along the OR7, I3 circuit will “maintain” the potential at the second input of I1 and will go to the first senior discharge, where through OR9, I2, HE5 it will set Tr10 to “one”. Thus, the code "1" will be shifted one bit to the left. (To carry out this operation, it was required to introduce one OR element into two inputs into the equipment, i.e., equipment measured by the number of inputs increased by 2).

Operation "invert". Suppose that the code "10" is stored in two bits of the counter. The potential of the operation flag is supplied to the bus 14. The executive pulse of the code inversion is supplied simultaneously to the buses 11 and 15. In the first bit, the code "0" is stored in Tr10, i.e. at the second input of I1 there will be low potential, at the second input of I2 there will be high. The executive impulse along the I9, I2, NOT5 circuit will go to the “single” input Tr10 and set it to “1”.

In the second digit in Tr10, the code "1" is stored, i.e. the output I3 will have a high potential, allowing the passage of the pulse from the bus 11 through the circuit I1, HE4 to the "zero" input Tr10, the executive pulse will set it to "0".

Thus, in Tr10 of the first and second digits the code “01” will be set, i.e. Now in triggers the inverse code will be stored. (To perform this operation, it was required to introduce one OR element into two equipment inputs, i.e., the equipment grew by two units). The operation "subtraction of pulses", i.e. deduction account. This operation involves the first inversion, pulse counting and second inversion. Consider example 9-5 = 4; 1001-0101 = 0100.

first invert ...... 10110;

count of five pulses ...... 11011;

second inversion ...... 00100.

The operation is completed. (No additional equipment is required to complete this operation!).

The operation "counting from" 0 "to" X ", where X = 2 ⁿ ; n is the number of binary bits of the counter. This operation is widespread in the digital automation device. It consists in the following: the number to which the count must be resolved in parallel binary code , is entered into the triggers 10, previously set to "0", via the buses 17. (This EO can also be performed by counting), then the operation "invert" is performed, then the pulses are counted until the transfer appears in the last high order.

Let's look at an example. To develop a control potential through a time interval, for example, equal to 9 pulses (events). In triggers 10, previously set to "0", the code 01001 is received, the invert operation is performed, 10110, the pulses are counted until the transfer potential appears in the last high order. (To perform this operation, only one input is required, i.e., the total number of inputs of logic elements is increased by 1). Thus, the proposed object while saving hardware costs by 15% increases the speed of its work by 1.5 times; expands the list of operations by five times, reduces electricity consumption by about 25%.

Claims (2)

1. A totalizing counter based on RS-triggers and AND, OR, NOT elements, characterized in that each binary digit of the counter contains one RS-trigger, the first, second and third AND elements, the first, second and third NOT elements, the first , the second and third elements OR, the bus of the counting pulses, while in each category the outputs of the first and second elements AND are connected to the inputs of the first and second elements NOT, the outputs of which are connected to the “zero” and “single” inputs of the RS-trigger, “single output »Which is connected to the first input of the first elem nt OR, the second input of which is connected to the output of the first AND element, and the output of the first OR element is connected to the first input of the third And element, the second input of which is connected to the "single" input of the RS-trigger, the third input of the third And element is connected to the output of the second OR element , the first input of which is connected to the bus for controlling the operations of unit shift and inversion, and to the second input is the bus of potential transfer from the least significant bit, the output of the third element And is connected to the potential transfer bus to the next highest bit a chick, with the input of the third element NOT and with the first input of the first element AND, the second input of which is connected to the bus of the counting pulses, the output of the third element is NOT connected to the first input of the second element AND, the second input of which is connected to the output of the third element OR, to the first input of which the invert pulse control bus is connected, and the output of the first AND element of the previous least significant bit is connected to the second input, and in the counting mode in the first least significant bit of the counter, the transfer pulse bus is combined with the counter impulse bus lsov. 2. The summing counter according to claim 1, characterized in that in each binary digit, the third input of the third OR element is connected to the numeric bus.