RU224225U1 - Multifunction Display Processor with Architectural Attenuation - Google Patents

Abstract

The utility model relates to computing technology, namely to processor modules for multifunction displays with the implementation of architectural attenuation (hereinafter referred to as the processor module), with the ability to detect anomalous behavior of COTS components of a multifunction display when using a COTS-based GPU, and can be used in areas with increased safety requirements, for example, in aviation.

Description

The utility model relates to computer technology, namely to processor modules for multifunctional displays with the implementation of architectural attenuation (hereinafter referred to as the processor module), providing processing of input information, generating and issuing output information and generating and issuing images in multifunctional displays, and can be used in the areas that impose increased safety requirements, for example, in aviation.

Multifunctional displays are multi-mode devices for displaying various graphic and television information produced by external devices, systems and sensors. Most modern multifunction displays use commercial off-the-shelf (COTS) CPUs and GPUs in the processor modules.

COTS - Commercial-Off-The-Shelf (commercial ready component). In this document, a complex digital component (processor, graphics controller, etc.).

Although the hardware of CPUs and GPUs has the required level of reliability, these COTS have such a complex structure that it is impossible to simulate or check all possible states in static or dynamic operation for errors made during design and manufacturing, so there is a possibility of occurrence of their abnormal behavior. In addition, CPUs or GPUs may contain various microcodes that, given certain inputs, may also exhibit anomalous behavior that may result in incorrect information being displayed on the display screen.

A situation in which unreliable information is provided to the consumer cannot be identified by the operator independently, which can lead to catastrophic consequences, therefore there are a number of regulatory documents, for example, a guide to guaranteeing the design of on-board equipment KT-254 [1], which require the mandatory implementation of the weakening of complex and highly complex COTS when developing products that require a high level of safety.

To improve display security, redundant circuitry is created to provide architectural attenuation and is used to monitor the operation of the primary circuitry.

The architecture of the processor module for multifunctional displays is known, described in the Russian Federation patent RU 215288 U1 dated December 7, 2022, IPC G06T 1/00 (2006.01), adopted as a prototype. This architecture contains two processing channels for the main channel and a control channel implemented on the FPGA. The main channel provides data reception, necessary calculations, image formation and display. In order to detect abnormal behavior of the central processor, a copy of the input data is transmitted to the control channel and to the central processor. A copy of the input data is processed in the central processor using known algorithms. The control channel carries out the same sequence of operations on a copy of the input data as the central processor. The calculation result is compared in the control channel. Based on the comparison results, the resulting signal is output to external equipment.

The disadvantages of this device are the inability to detect anomalous behavior of the entire computing path, as well as limited functionality caused by the narrow focus of the FPGA (Programmable Logic Integrated Circuit) GPU.

The problem that this utility model aims to solve is to identify the anomalous behavior of a COTS multifunction display when using a COTS-based GPU.

The technical result consists in expanding the functionality of a processor module with architectural weakening.

The specified technical result is achieved due to the fact that the processor module for multifunctional displays with the implementation of architectural attenuation contains a central processor connected by bidirectional exchange buses with a data receiving node, RAM (random access memory) and a graphics processor, a graphics processor connected to video RAM via bidirectional exchange bus, as well as a data output node connected by a bidirectional exchange bus to the central processor, wherein the processor module contains a display controller connected by a graphical interface to the graphics processor and a data control node connected by a bidirectional exchange bus to the data receiving node and the central processor, graphical interface with a display controller, and through a digital interface with a data output unit, while the display controller is based on an FPGA, and the control unit is based on a programmable logic integrated circuit or a processor with an architecture different from the architecture of the central processor.

Using the method of architectural attenuation [1], aimed at identifying the specified anomalous behavior of the COTS of the central processor, graphics processor, RAM and video RAM, a redundant control node, independent of the main computing process, based on an FPGA or having a different processor architecture, was introduced into the processor module. which increases the ability to detect anomalous COTS behavior.

In fig. 1 shows a block diagram of the claimed processor module for multifunction displays, where:

1 - processor module;

2 - data receiving unit;

3 - central processor;

4 - random access memory (RAM);

5 - video RAM;

6 - graphics processor;

7 - FPGA-based display controller;

8 - data control unit based on FPGA or having a different processor architecture;

9 - data output unit;

10 - data display device;

11 - external equipment.

Processor module 1 contains a data receiving unit 2, connected via digital interfaces to external equipment 11, as well as two data processing channels - the main and control ones.

The main data processing channel consists of a central processor 3 connected by bidirectional exchange buses to the data receiving node 2 and RAM 4, a graphics processor 6 connected to video RAM 5 via an exchange bus, and a display controller 7 connected via graphical interfaces to the graphics processor 6 and data display device 10.

The control channel consists of a data control node 8, connected by bidirectional exchange buses to a data receiving node 2 and a central processor 3, a graphical interface with a display controller 7, and also to a data output node 9 via a digital interface.

The processor module operates as follows.

Operation of the main channel of the processor module.

During operation, input data from external equipment 11 via on-board interfaces enters the data receiving unit 2, where, after processing, it is placed in registers available for reading by the central processor 3. The input data is read and placed in RAM 4. The central processor 3 performs the necessary calculations with the input data, using RAM 4 during intermediate calculations and, based on the calculation results, generates commands for constructing the main image frame. The generated commands are transmitted through a bidirectional exchange bus to the graphics processor 6. The graphics processor 6, based on the commands of the central processor 3, forms a graphic image frame, placing it in the video RAM 5. At the right time, the graphics processor 6 copies the image from the video RAM 5 and via digital transmits the video channel to the display controller 7. The display controller receives the image and transmits it with the necessary time parameters to the data display device 10.

During operation, the central processor 3, via a bidirectional exchange bus, issues processed information to the data output node 9, and then the information is sent to external equipment 11.

Operation of the control channel of the processor module.

In order to detect abnormal behavior of the central processor 3, graphics processor 6, RAM 4, video RAM 5, the data receiving node 2, at a predetermined time interval, copies the input data into special registers intended for control, accessible for reading by the central processor 3 and via a bidirectional exchange bus a copy of the input data is transmitted to the data control node 8. The central processor 3 reads the input data from the registers intended for control and performs a series of control calculations, including addition, multiplication, logical operations, as well as communication operations with input/output devices and RAM , generates commands for constructing reference images corresponding to the read input data. The result of the operations of the central processor 3 is transmitted to the data control node 8, commands for constructing control images are transmitted to the graphics processor 6.

The graphics processor 6, based on commands from the central processor 3, generates graphic images with the addition of a control line consisting of a graphic image of the control data values in the invisible area of the image and transmits them to the display controller 7. The display controller 7 extracts the control images from the invisible area of the main image frame, brings the resolution and timing parameters of the main frame to the required ones and transmits it to the data display device 10. The display controller 7 transmits the extracted control line to the data control unit 8.

The data monitoring node 8, with a copy of the input data intended for control received from the data receiving node 2, performs the same sequence of operations as the central processor 3, after which the completed calculation results are compared with the calculation result received from the central processor 3.

The data control node 8 converts the graphic images of the control data values received from the display controller 7 into a numerical value format and compares it with a copy of the input data received from the receiving node 2.

Based on the results of comparing the calculation result of the central processor 3 and the values of graphic images of data from the display controller 7 with the data calculated in the data control unit 8, the resulting signal is issued to the data output unit 9 and then the resulting control signal is issued to consumers in external equipment 11.

Thus, the introduction into the claimed processor module of a display controller based on an FPGA and a data control unit that provides control of the entire main channel involved in image formation, independent of the main computing process, allows for architectural weakening of the COTS of the central processor, graphics processor, RAM and video RAM, which made it possible to exclude a highly specialized FPGA-based graphics processor, thereby increasing the versatility of the processor module.

1. Guide to guaranteeing the design of on-board equipment KT-254, page 66.

Claims (1)

A processor module for multifunctional displays with the implementation of architectural attenuation, containing a central processor connected by bidirectional exchange buses to a data receiving node, RAM and a graphics processor, a graphics processor connected to video RAM via a bidirectional exchange bus, and a data output node connected by a bidirectional exchange bus with a central processor, characterized in that the processor module contains a display controller connected by a graphical interface to the graphics processor, and a data control unit connected by a bidirectional information exchange bus to the data receiving unit and the central processor, a graphical interface to the display controller, and through a digital interface - with a data output unit, wherein the display controller is based on a programmable logic integrated circuit, and the control unit, which implements the architectural attenuation of complex digital components, is based on a programmable logic integrated circuit or a processor with an architecture different from the architecture of the central processor.