RU2242013C2 - Correlation analyzer of frequency properties of linear system - Google Patents

Abstract

FIELD: technology for evaluation of frequency interferences.

SUBSTANCE: device has multiplexer, correlator, comparing block and control block. Operation of analyzer is based on comparison of auto-correlation function of input signal to auto-correlation function of output signal. Evaluation of value of frequency interferences is reduced to evaluation of level of change of auto-correlation function of signal passing through analyzed circuit.

EFFECT: higher efficiency, higher precision.

6 cl, 4 dwg

Description

The invention relates to the field of radio measurements and is intended to evaluate the frequency distortion introduced by the linear inertial system into the original random signal. In particular, the analyzer can find application in the problems of controlling spectral distortions arising in sound amplification paths.

To assess the frequency distortion, analyzers of amplitude-frequency characteristics (AFC) are widely used, which make it possible, by means of a special test action on the linear system under study (four-terminal), to trigger a reaction that determines the ability of the object under investigation to amplify signals of different frequencies. The result of the assessment, as a rule, is the function Y (ω) - normalized frequency response, which is a normalized frequency-dependent gain. The frequency response analyzer (prototype) consists of a test signal generator and a spectrum analyzer, the output of which is the information output of the frequency response analyzer, whose test input is the input of the spectrum analyzer [Rosenberg V.Ya. Radio engineering methods for measuring the parameters of processes and systems. M .: Publishing house of the committee of standards, measures and measuring instruments, 1970, pp. 123-124].

The use of the prototype analyzer allows you to judge the introduced frequency distortion by visual assessment of the shape of the frequency response. In addition to this, the maximum deviation of the function Y (ω) from a straight line within the operating range is often also measured, which is the only quantitative indicator that the known approach gives. However, the distortions of the original signal do not depend on the gain K (ω _i ) at the frequency ω _i , for which it was established that K (ω _i ) has a minimum or maximum value at this point, but depends on the shape of the frequency response in the entire frequency range, i.e. on the function K (ω) defined in the entire range. Consequently, the applied quantitative indicator of frequency distortions is uninformative. Another very important disadvantage of the prototype is the need to generate and use a special test signal - white noise, frequency-modulated harmonic signal or pulse sequence. It follows from the above that, in order to analyze the frequency properties of the system, it should be put into test mode and, of course, interrupt the execution of useful “regular” functions.

The technical result achieved when using the present invention is to increase the information content of the analysis of the frequency properties of the analyzed (tested) linear system, as well as to provide the possibility of analyzing the system without interrupting its operation and transferring it to a special test mode.

The technical result is achieved by the fact that the correlation analyzer of the frequency properties of the linear system according to the invention comprises a multiplexer, a correlator, a comparison unit and a control unit, the input of which is the start input of the analyzer, the first test input of which is the first information input of the multiplexer, the second information input of which is the second test input analyzer, the multiplexer output is connected to the information input of the correlator, the output of which is connected to the information input of the CPA unit neniya whose output is the data output of the analyzer, the address input of the multiplexer, the clock and reset inputs of the correlator, as well as control inputs comparison unit connected to the respective outputs of the control unit, the address output of which is connected to a single address bus and comparing the correlator unit.

The comparison unit, designed to work with discrete quantities, can be made in the form of a device that calculates the average value of the difference module of the compared values, in the form of a device that calculates the sum of the difference modules of the compared values, in the form of a device that calculates the rms value of the difference of the compared values, in the form of calculating the average ratio of the compared values.

In addition, the comparison unit, designed to work with discrete quantities and designed as a device that calculates the average value of the difference module of the compared values, can contain two random access memory devices, a subtraction unit and an averaging unit, the output of which is the output of the comparison unit, the address input of which is combined address inputs of random access memory devices, the information inputs of which are also combined and serve as the information input of the comparison unit, the information outputs of the first o and the second random access memory are connected respectively to the first and second inputs of the subtraction unit, the output of which is connected to the input of the averaging unit, the combined inputs of the write control of the random access memory serve as the first control input of the comparison unit, the second and third control inputs of which are the chip selection inputs, respectively, of the first and a second random access memory.

The invention is illustrated by drawings. Figure 1 shows a functional diagram of a correlation analyzer of the frequency properties of a linear system with a connected test amplifier. Figure 2 shows a functional diagram of one of the options for implementing the correlator. Figure 3 shows a functional diagram of one of the options for implementing the comparison unit. Figure 4 shows a functional diagram of one of the embodiments of the control unit.

The functional diagram of the meter of figure 1 contains an analog multiplexer 1, a correlator 2, a comparison unit 3, a control unit 4 and a test amplifier 5 with a connected load R _L. The output of the tested amplifier 5 is connected to the first information input of the multiplexer 1, the second information input of which is combined with the input of the amplifier 5, the output of the multiplexer 1 is connected to the information input of the correlator 2, the output of which is connected to the information input of the comparison unit 3, the output of which is the information output of the meter, address the input of the multiplexer 1 is connected to the output M (Mode) of the control unit 4, the clock and zeroing inputs of the correlator 2 are connected respectively to the outputs CLK and RST of the unit 4, the first, second and third The control inputs of the comparison unit 3 are connected respectively to the outputs WR / RD, CS1, and CS2 of unit 4, the address output A of which is connected to a single address bus of the correlator 2 and the comparison unit 3, the input of the control unit 4 serves as the input of the meter start CO.

The functional diagram of the correlator 2 (Fig. 2) contains an analog-to-digital converter (ADC) 6, a delay line 7, a group of 8 multipliers, a group 9 of accumulating adders, a multiplexer 10 and a normalization unit 11, the output of which is the output K (τ) of the correlator 2, the input of which is the information input of the ADC 6, the output of which is connected to the input of the delay line 7 and the combined first inputs of the multipliers 8, the outputs of which are connected to the information inputs of the corresponding accumulating adders from group 9, the outputs of which are connected to the corresponding the information inputs of the multiplexer 10, the output of which is connected to the first input of the rationing unit 9, the second input of which is connected to the output of the accumulating adder 9-1, the clock inputs of the adders 9 are combined and make up the clock input CLK of the correlator 2, the zeroing inputs of the adders 9 are also combined and make up zeroing the RST input of correlator 2, the second input of the multiplier 8-1 is combined with the first, and the second inputs of the multipliers 8-2 - 8-N are connected to the corresponding outputs of the multi-tap delay line 7, the address input of the multiplexer 10 is address bus of the correlator 2. Block 11 normalization can physically be made in the form of a division unit, with the first input of block 11 is the input of the dividend, and the second input is the input of the divider.

Block 3 comparison (figure 3) contains random access memory (RAM) 12 and 13, block 14 subtraction and block 15 averaging. The outputs of the RAM 12 and 13 are connected to the corresponding inputs of the subtracting unit 14, the output of which is connected to the input of the averaging unit 15, the output of which is the output of the comparison unit 3, the information input DI of which is the combined information inputs of the RAM 12, 13, the combined recording control inputs WR / RD which serve as the first control input of block 3, the second CS1 and third CS2 control inputs of which are the CS inputs of RAM 12 and 13, respectively, the address inputs of RAM 12, 13 are combined and make up the address bus of the comparison unit 3.

The control unit 4 (Fig. 4) contains counters 16, 17, 18, a decoder 19, OR elements 20, 21, 22, 23, 24, AND elements 25, 26, 27, 28, a single vibrator 29 and a clock generator 30. The bit outputs of the counter 16 are connected to the corresponding bit inputs of the decoder 19, the first output of which is connected to the first input of the OR element 21, the second output is connected to the combined first inputs of the elements OR 22 and AND 27, the third output is connected to the second input of the element OR 21, the fourth output is connected with the second input of the OR element 22 and the first input of the AND element 28, the fifth output is connected to the combined third input of the OR element 22, the first input of the OR element 23, the first input of the OR element 24, the second inputs of the elements AND 27, 28 are combined and under are connected to the output of the And 26 element, the first input of which is combined with the first input of the And 25 element and connected to the output of the clock pulse generator 30, the second inputs of the And 25, 26 elements are connected to the outputs of the OR elements 21, 22, respectively, the outputs of the And 25, 26 elements are connected to the counting inputs of the counters 17, 18, respectively, the outputs of the transfers of the counters 17 and 18 are connected to the first and second inputs of the OR element 20, respectively, the resetting input of the counter 17 is connected to the transfer output of the specified counter, the resetting input of the counter 18 is connected to the transfer output of the counter shown, the counter input of counter 16 is connected to the output of the OR element 20, the third input of which is the input CO of the start of control unit 4, whose output RST is the output of the single vibrator 29, the input of which is connected to the third output of the decoder 19, the third output of the decoder 19 serves as a mode output M block 4 and is designed to connect to the address input of the multiplexer 1, the address output A of block 4 is the multi-bit information output of the counter 18, the clock output CLK of block 4 is the output of the element And 25, the output WR / RD controls For recording, the fifth output of the decoder 19 serves, the outputs CS1 and CS2 are the outputs of the OR elements 23, 24, respectively, with the second input of the OR element 23 connected to the output of the AND element 27, and the second input of the OR element 24 connected to the output of the AND element 28.

The analyzer’s principle of operation is based on the idea of calculating the autocorrelation functions of the input x (t) and output y (t) signals and then comparing them. The measure of introduced frequency distortion will be the functional Ф (R _xx , R _yy ), which depends on the autocorrelation functions R _xx (τ), R _yy (τ) of the input and output signals, respectively.

It is known that the parameters of random signals after passing through linear inertial systems change and depend on the properties of these systems. The autocorrelation functions of stationary random signals at the input and output of a linear inertial system are interconnected by the expression [Zinoviev A.L., Filippov L.I. Introduction to the theory of signals and circuits. M .: Higher School, 1975, pp. 183-187]

where R _h (α) is the autocorrelation function of the impulse response h (θ) of the system.

From the above relation it follows that the correlation properties of the output signal of the linear inertial system are determined by its impulse response h (θ). In turn, the Fourier transform for the impulse response h (θ) gives us the complex transfer coefficient of the system K (jω), which uniquely and comprehensively determines its frequency properties. In addition, there is a relationship between the function R _yy (τ) and the energy spectrum of the input signal G _x (ω), which depends on the transfer coefficient K (jω)

which shows that in the ideal case of the absence of frequency distortion, when | K (jω) | = K, the autocorrelation functions R _xx (τ), R _yy (τ) at the input and output will differ only by a constant coefficient K ²

because

и

It follows from the presented dependences that the problem of estimating frequency distortions can be reasonably reduced to a correlation analysis of separately input and output stationary random signals of a linear system, namely, to the calculation of normalized autocorrelation functions

and

The analysis process consists of three main stages. At the first stage, the normalized autocorrelation function K _yy (τ) of the output signal of the tested amplifier is calculated; at the second stage, the normalized autocorrelation function K _xx (τ) of the input signal is calculated. At the third stage, the obtained values of K _yy (τ) and K _xx (τ) are compared.

According to the triggering pulse at the input of CO (Fig. 1) - the beginning of stage I - in the correlator 2, the calculation of the function K _yy (τ) begins, since the signal y (t) is supplied to the information input of the correlator 2 through the first input of multiplexer 2, and block 4 In response to the CO pulse, the control unit generates a packet of clock pulses clocking the correlator, the number of which determines the duration of the observation interval T. After time T, block 4 stops supplying clock pulses and proceeds to control transmission to block 3 for comparing the calculation results K _yy (τ). To this end, the control unit 4 starts enumerating the addresses on a single address bus A, turning sequentially to the memory cells of the correlator 2, each of which contains one ordinate of the function K _yy (τ). At the same time, the memory cells are also accessed in the comparison block 3, where the calculated values of K _yy (τ) are copied. At the end of the transmission of information from the correlator 2 to block 3, the memory of the correlator 2 is reset and its timing resumes, which means the beginning of stage II. In addition, a logic unit is set at the mode output M, which leads to switching to the output of the multiplexer 1 of the signal x (t). At this stage, the function K _xx (τ) is calculated. The second stage is completed in the same way as the first, by transferring the estimate K _xx (τ) to the memory of the comparison unit 3, after which the meter proceeds to the stage of comparing normalized autocorrelation functions (stage III).

The comparison of the functions K _yy (τ _i ) and K _xx (τ _i ) in the example illustrated by the circuit of Fig. 3 (in the digital version when discrete values are compared) is performed by calculating the average deviation M [ΔK _xy ] = Ф (R _xx , R _yy )

where N is the number of ordinates calculated (sample size);

τ _i is the delay discretely introduced by line 7.

With the maximum possible similarity of the processes x (t) and y (t), when x (t) = ky (t) (k is a constant coefficient), the value of M [ΔK _xy ] will be 0. With an increase in the degree of difference between the input and output signals the average value of the difference M [ΔK _xy ] of their autocorrelation functions will also grow. Thus, during the operation of the comparison unit 3 according to algorithm (1), the quantity M [ΔK _xy ] should be considered a quantitative indicator of the introduced frequency distortions.

Of course, the comparison of K _yy (τ _i ) and K _xx (τ _i ) can be made not only by calculating the average deviation (1), but also by other methods, for example, by finding the total deviation, for which the factor 1 should be excluded in the right-hand side of (1) / N; it is possible to calculate the average ratio K _yy (τ ₁ ) / K _xx (τ _i ), etc. In each of the cases, the structure of the comparison block 3 corresponding to the selected algorithm is used. The only thing that remains unchanged for all cases is that in order to estimate the level of frequency distortions it is necessary to find out how much the autocorrelation functions of the input and output signals differ. In the general case, in the absence of distortions, Φ (R _xx , R _yy ) = 0.

As a correlator 2, a parallel type device (but not necessarily) (Fig. 2) containing N processing channels (according to the number of ordinates calculated) can be used. The principle of operation of such devices is well known and consists in generating N signals delayed for a time τ _i = (i-1) Δτ (Δτ is the delay discret), then multiplying the signal x (t _j ) (y (t _j )) by the signal x (t _j -τ _i ) (y (t _j -τ _i )) and computing N sums of the form

or

where t _j = t ₀ + jΔt (j = 1, 2, ... M);

t ₀ is the initial moment of time;

Δt is the sampling period of signals x (t), y (t) in ADC 6.

M - the number of samples in the sample for time T.

To obtain the ordinates of the normalized autocorrelation function, the sum S _i should be divided by a similar value at zero delay (τ ₁ = 0), i.e., calculate the ratio

for different values of τ _i (for the function K _yy (τ _i ) it is necessary to perform the same operations with replacing x (t) with y (t)). Amounts of the form (2), which are used in (3), are formed at the outputs of accumulating adders 9-1 - 9-N. For switching each value of S _i to the input of the normalization block 11, a multiplexer 10, controlled by a single address bus by block 4, serves. In the process of sorting the addresses, the values of K _yy (τ _i ) (K _xx (τ _i )) for all i, Since in block 11 the results are normalized by dividing the sums of S _i without prior averaging, block 11 can be simplified to the level of the division block.

The purpose of the comparison unit 3 (Fig. 3) is to calculate expression (1), for which it is necessary to perform two basic operations: obtain the difference modulus for different τ _i and average the obtained values. Calculation of the difference modulus | K _yy (τ _i ) -K _xx (τ _i ) | occurs in block 14 subtraction. The averaging unit 15 may consist of an accumulating adder and a constant division device N, the input of the accumulating adder being the input of the averaging unit, the output of which is the output of the division device, the input of which is connected to the output of the accumulating adder.

When the comparison unit 5 is used, RAM 12 is activated in the first stage, for this the control unit 4 supplies the pulses CS1 to the corresponding RAM input 12. In the second stage, the unit 4 stops supplying the CS1 pulses and starts supplying the CS2 pulses to select the RAM 13. As a result, the value of the function K _yy (τ _i ) are written to RAM 12, and the functions K _xx (τ _i ) are written to RAM 13. At the stage of comparison, RAM 12, 13 are put into reading mode, for this the control unit 6 generates logical levels: (WR / RD) = 1, CS1 = CS2 = 1; on address bus A, the RAM addresses are sequentially sorted and the extracted data is sent to the subtraction block 14 in a tactful manner, and then to the averaging block 15.

To control the operation of the above nodes is a dedicated control unit 4 (figure 4), the principle of which is as follows.

In the initial state, the entire serial logic of block 4 is reset. The control unit 4 for controlling a short pulse at the input of CO is launched, in response to which the counter 16 commands sets the code corresponding to the decimal unit on its bit outputs (at the low-order digit, it is a logical unit, on the others - zeros). In this case, the logical unit appears at the output DO1 of the decoder 19 (zeros at the other DO outputs), which leads to the fact that the CLK output of block 4 starts to receive clock pulses, which serve to control the correlator 2. The observation time T, during which the output CLK clock pulses operate, it is counted by the counter 17, the conversion factor of which is selected so that a pulse appears after the transfer output P after counting M clock pulses (see formula (2)). According to the transfer pulse, the counter 17 is reset, the counter 16 increments its contents, the distributions DO2 = 1, DO0 = DO1 = DO3 = DO4 = DO5 = 0 are established at the outputs of the decoder 19, and clock pulses cease to arrive at the CLK output. When DO2 = 1, the address counter 18 is started, which, after iterating over the specified amount of addresses on bus A (the number of addresses must be at least the number of channels N of correlator 2), is reset, and then the pulse from the transfer transfer output of counter 18 affects the counter input of counter 16 commands, as a result, at the outputs of the decoder 19, the logical levels DO3 = 1, DO0 = DO1 = DO2 = DO4 = DO5 = 0 are set. With a positive voltage drop at the output D03 of the decoder 19, a zeroing pulse (output RST) is generated, which is generated by a single-shot 29, which only works on positive edges. The zeroing impulse is fed into the correlator 2, the accumulative adders 9 are reset there and this should be considered the end of the first and the beginning of the second stage.

At the second measurement stage, unit 4, as before, outputs a packet of clock pulses to the CLK output, after which (with DO4 = 1) the address counter 18 is turned on to access the memory of correlator 2 and comparison unit 3. At this stage, pulses CS2 of RAM selection 13 are generated, in the cells of which the ordinates of the function K _xx (τ _i ) are written. Next, with a transfer pulse at the output of counter 18, the code at the output of counter 16 is incremented by a unit of the least significant bit, and the following levels DO0 = DO1 = DO2 = DO3 = DO4 = 0, DO5 = 1 are set at the outputs of the decoder 19. When DO5 = 1, the control unit 4 switches to the meter control mode in the third stage. This stage is characterized by the fact that (WR / RD) = CS1 = CS2 = 1, and therefore, the RAM 12, 13 are put into read mode and the counter 18 sequentially issues addresses to the address bus, from which the operands are extracted from RAM 12, 13 to obtain result of the form (1). With the advent of the transfer pulse at the output of the counter 18, it is reset to zero, and the logic outputs are set to low logic levels at the DO outputs of the decoder 19: the control unit 4 has completed a given cycle and is ready for the next, for which a start pulse should be applied to the input of the CO. We also note that each next measurement cycle should begin with zeroing the accumulating adders, which are both part of the correlator 2, and in the averaging block 15, and also with resetting the counter 16.

The advantages of the analyzer compared to known devices of a similar purpose are as follows:

- determination of the autocorrelation functions of the input and output signals, and then the calculation of the functional depending on them, allows to obtain a quantitative criterion of frequency distortion, taking into account changes at all points of the spectrum along its entire width, which increases the information content of the analysis;

- since a useful signal is used as a measuring signal, which arrives at the input of the system under study in its normal, operating mode, then the analysis process can be performed without putting the system into a special test mode;

- algorithmic features of the analyzer allow it to be used as a device for continuous monitoring of frequency distortions, for example, as an integrated unit in the amplification paths of audio signals.

Claims (6)

1. A correlation analyzer of the frequency properties of a linear system, characterized in that a multiplexer, a correlator, a comparison unit and a control unit are introduced into it, the input of which is the analyzer start input, the first test input of which is the first information input of the multiplexer, the second information input of which is the second test analyzer input, the multiplexer output is connected to the information input of the correlator, the output of which is connected to the information input of the comparison unit, the output of which is info analyzer output, multiplexer address input, clock and zero correlator inputs, as well as control inputs of the comparison unit are connected to the corresponding outputs of the control unit, the address output of which is connected to a single address bus of the correlator and the comparison unit. 2. The analyzer according to claim 1, characterized in that the comparison unit, designed to work with discrete quantities, is made in the form of a device that calculates the average value of the difference module of the compared values. 3. The analyzer according to claim 1, characterized in that the comparison unit, designed to work with discrete values, is made in the form of a device that calculates the sum of the difference modules of the compared values. 4. The analyzer according to claim 1, characterized in that the comparison unit, designed to work with discrete quantities, is made in the form of a device that calculates the rms value of the difference of the compared values. 5. The analyzer according to claim 1, characterized in that the comparison unit, designed to work with discrete values, is made in the form of a device that calculates the average ratio of the compared values. 6. The analyzer according to claim 1 or 2, characterized in that the comparison unit, designed to work with discrete quantities, contains two random access memory devices, a subtraction unit and an averaging unit, the output of which is the output of the comparison unit, the address input of which is the combined address inputs random access memory devices, the information inputs of which are also combined and serve as the information input of the comparison unit, the information inputs of the first and second random access memory devices are connected respectively but to first and second inputs of the subtracting unit, whose output is connected to the input of block averaging, the combined operational inputs write control memory devices are a first control input of the comparator, the second and third control inputs of which are the selection inputs of the crystal of the first and second random access memories.

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