RU2237373C1 - Method for organizing clocking system for digital signal transfer in network communication center - Google Patents

Abstract

FIELD: communications engineering.

SUBSTANCE: in order to eliminate impact of relative phase wandering between output signals of internal generators of communication units and digital signals being received onto characteristics of digital signal transfer between communication units proposed method includes reception of clocking signal generated by relevant clock generator during reception of digital signal by reception interface; accumulation of phase deviations between reception clocking signal and digital signal received by reception interface; tuning of reception clock generator to eliminate phase deviations between reception clock signals and digital signal being received; transmission of digital signal to transmission interface using transmission clocking signal. Novelty is that reception clocking signal generated by relevant clock generator upon tuning and elimination of phase distortions is used as transmission clocking signal.

EFFECT: enhanced reliability of eliminating phase distortions.

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Description

The proposed method relates to communication technology, more specifically to the transmission of digital signals and synchronization systems, and can be used in the construction of synchronization systems of communication networks, in the equipment of network nodes, in particular in switching equipment and equipment of digital signal transmission systems. The most effective use of the proposed method for organizing the joints of communication networks of various operators while maintaining the existing quality parameters of the transmission of digital signals in the network of each operator. The proposed method provides independent development of communication networks of various operators.

The main causes of phase distortion are:

- discretization processes in transmitting communication equipment,

- changes in the propagation delay of the signals associated with changes in the temperature of the cable lines,

- the frequency difference of the generators of the transmitting and receiving communications equipment,

- wandering phase signals of internal generators, etc.

Such phase distortions in communication technology are divided into jitter and wander phases of signals, as described in ETSI EN 300 462-1-1: “Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 1- 1: Definitions and terminology of synchronization networks "(European Institute of Telecommunication Standards, European Telecommunication Standard 300 462-1-1" Transmission and Multiplexing (TM); General requirements for synchronization networks; Part 1: Definitions and terminology for synchronization networks ").

In the interfaces of the reception of communication equipment, it is necessary to implement methods that provide error-free reception of digital signals with phase distortion.

Examples of such methods are given in ITU-D, Report on Question 16/2-Fascicle 1-New technologies supporting new networks. Chapter 5.2002 (International Telecommunication Union. - Development Sector. Report on Question 16/2. Edition 1. New technologies for new networks. Chapter 5.2002.)

Reducing the negative effect of phase wandering of the received signals is achieved through the use of a "first-in-first-out" FIFO buffer in the receive, slip control interface and tuning of the internal oscillator of the receiving communication equipment .

The influence of phase jitter of the received signal is eliminated by controlling the reception clocks and also by using the mentioned FIFO buffer in the reception interface.

Variants of how to control receive clocks are also described in ITU-D, Report on Question 16/2-Fascicle 1-New technologies supporting new networks. Chapter 5.2002 (International Telecommunication Union. Development Sector. Report on Question 16/2. Edition 1. New Technologies for New Networks. Chapter 5.2002.)

In general terms, the methods of controlling the reception cycles are reduced to the following actions performed cyclically:

- the formation of clock cycles,

- comparison of the phase of the clock cycles and the time limits of the existence of bits of information in the received signal,

- adjustment of the phase of the reception clock when the phase of the reception clock approaches the time limit of the existence of the information bit in the received signal.

Variants of the technical implementation of the methods for controlling the clock strokes may be different. For example, in Technical Description 4a2.104.282 TO 4. "Hub APK-1000. ET-L Block" describes the structure and principle of operation of the exchange terminal ET-L unit, which is an interface unit for receiving and transmitting PCM digital signals with speed of 2048 kbit / s. In the ET-L block, the reception clocks are controlled using the so-called “clock selector” included in the receiving part of the matching device. The clock allocation in ET-L is based on the well-known method using an oscillatory circuit tuned to a frequency of 2048 kHz.

Transmission timing is usually done from an internal communications equipment generator.

Closest to the proposed method for the combination of essential features is the method described in US patent No. 5923704 "Transmit clock generation system and method", 07/13/1999, selected by the authors as a prototype. The communication system proposed in it consists of at least two communication units containing internal generators. The generator of the second communication unit is the master, and the generator of the first communication unit is the slave. The second communication unit transmits, and the first communication unit receives a data signal. In the first communication unit, the phase difference between the received data signal and the reception clocks is determined. As the phase difference increases, the reception clock is tuned. Information about these adjustments is accumulated and used to adjust the internal generator of the first communication unit. The signal from the output of the internal generator is fed to the frequency division / multiplication device, which generates a transmission clock signal.

However, this method has the following significant drawback.

In the method selected as a prototype, the synchronization of the generator of the first communication unit is carried out from the generator of the second communication unit according to the “master-slave” principle, which ensures error-free transmission of digital signals between these blocks due to the absence of large values of the amplitude of the relative phase wander between the output signals of the internal block generators .

In the case when the internal generators of the communication blocks are synchronized from different sources of synchronization signals or on different synchronization circuits (for example, belong to communication networks of various operators), errors may occur during the transmission of digital signals due to the large relative phase wander between the output signals of the internal generators of the communication blocks and received digital signals.

If the relative phase wander between the output signals of the internal block generators and the received digital signals exceeds 18 μs, error-free transmission of digital signals between the blocks is not ensured, as indicated in ETSI Recommendation EN 302 084 V1. 1.1 (2000-02) Transmission and Multiplexing (TM); The control of jitter and wander in transport networks. Thus, the magnitude of the relative phase wandering affects the quality of the transmission of digital signals between communication units.

The objective of the present invention is to eliminate the influence of the magnitude of the relative phase wander between the output signals of the internal generators of the communication units and the received digital signals on the quality of transmission of digital signals between the communication units.

In order to solve this problem, it is proposed to generate the transmission clock signal not from the output signal of the internal generator, but from the reference reception clocks.

Summarizing the above features, we can state that the essence of the proposed method is as follows.

A method of organizing a digital signal transmission clock system is implemented in a network communication node, which comprises, in particular, a signal transmission interface, a signal receiving interface and a reception clock signal generator used to receive a digital signal, and consists in the following sequence of actions:

- receiving a digital signal in a reception interface using a reception clock signal generated by a reception clock signal generator,

- accumulation of phase deviations between the reception clock signal and the received digital signal in the reception interface,

- tuning the generator of the reception clock signal to eliminate phase deviations between the reception clock signal and the received digital signal,

- transmitting a digital signal in a transmission interface using a transmission clock signal.

The method differs from previously known in that the transmission clock in the transmission interface uses not a signal generated by the internal generator, but a reception clock signal generated by the reception clock signal generator after adjusting and eliminating phase distortion.

In communication equipment, a digital signal for transmission may have time characteristics different from those of a transmission clock signal. To avoid bit errors during the transmission of this digital signal, it is additionally proposed to use a buffer with the FIFO structure in the transmission interface. The operation algorithm of this buffer is similar to the operation algorithm of the FIFO buffer in the reception interface, except that the digital signal intended for transmission is written to the buffer with clocks having the time characteristics of the digital signal itself, then the transmitted digital signal is read from the mentioned FIFO buffer with clock cycles determined by the transmission timing signal.

The general sequence of actions in the proposed method is presented in figure 1. Figure 2 shows an embodiment of a method using a FIFO buffer.

In practice, the method can be implemented, for example, when it is used in a signal adapter installed at the joints between communication networks. In one embodiment, such an adapter may have two digital transmit / receive interfaces. One interface can be connected to communication equipment of one network, and the second interface can be connected to communication equipment of another network. Inside the adapter, signals received at one of the interfaces are transmitted to the second interface for transmission.

The block diagram of the adapter at the junction of two communication networks is presented in figure 3. In the receive-transmit interface No. 1, the clocks are extracted from the received 2048 kbit / s signal from the communication network No. 1.

A transmission timing signal generated from a reception timing signal is used to transmit a digital signal to communication network No. 1.

On the receive-transmit interface No. 2, the clocks are extracted from the received 2048 kbit / s signal from the communication network No. 2. A transmission timing signal generated from a reception timing signal is used to transmit a digital signal to communication network No. 2.

Using the proposed method of organizing a clock system for transmitting a digital signal on both adapter interfaces, the influence of the phase characteristics of digital signals received from one network on the transmission quality of these signals in another network can be eliminated.

Implementation of the proposed method will reduce the cost of organizing joints between communication networks (including various operators), while ensuring their independent development.

The economic effect of the implementation of the proposed method can be shown by example.

The development of communication networks leads to a change in their structural parameters and, as a result of this, in most cases, to an increase in the magnitude of the relative phase walks at the junctions between the networks. To ensure error-free transmission of digital signals requires the installation of additional equipment at such joints. This equipment should eliminate the effects of relative phase wandering signals. The currently used equipment of the secondary master oscillators (VZG) or adapters / splitters of synchronization signals (APCC) only partially eliminates this influence, since they implement the method of the described prototype.

Implementation of the proposed method will not only completely eliminate the influence of the relative phase wander of the signals, but also significantly reduce the cost of additional equipment.

The estimated cost of the device that implements the proposed method does not exceed 32,000 rubles. The minimum cost of certified VZG exceeds 580,000 rubles. The minimum cost of certified ARSS is about 102,000 rubles. Thus, the economic effect can range from 70,000 p to 550,000 rubles for each joint.

Claims (2)

1. A method of organizing a clock system for transmitting a digital signal in a network communication node, which contains a signal transmission interface, a signal receiving interface and a reception clock signal generator used to receive a digital signal, which comprises receiving a digital signal in a reception interface using a reception clock signal generated by reception clock signal generator, accumulation of phase deviations between the reception clock signal and the received digital signal in the reception interface, a generator of a reception clock signal to eliminate phase deviations between a reception clock signal and a received digital signal, transmitting a digital signal in a transmission interface using a transmission clock signal, characterized in that a reception clock signal generated by a signal generator is used as a transmission clock signal in a transmission interface timing of reception after adjustment and elimination of phase distortion. 2. The method according to claim 1, characterized in that the transmission interface of the network node contains a buffer that operates on the principle of "first-in-first-out" (first-in first-out) FIFO, from which a digital signal intended for transmission is read from using the signal generated by the reception clock signal generator.

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