RU2230414C2 - Microprocessor device for automatic frequency reduction - Google Patents

Abstract

FIELD: relay engineering; automatic control of power system frequency under emergency situations. SUBSTANCE: proposed microprocessor unit designed to prevent abnormal frequency drop in power system and its recovery to desired level by disconnecting some of loads in case of active power shortfall, as well as to automatically throw disconnected loads on line upon elimination of active power shortfall has comparison unit, inhibit unit, microprocessor, two memory registers, counter, timer, and input/output unit. Device is intended for installation indoors on centralized control boards and unit-type group relay boards of power stations. EFFECT: simplified design, reduced size, and facilitated maintenance while retaining basic functions. 1 cl, 4 dwg

Description

The invention relates to techniques for relay protection and emergency automation and is intended to prevent an accidental decrease in the frequency in the power system and its restoration to a predetermined level by automatically turning off part of the consumers when there is a shortage of active power (automatic frequency unloading) and to automatically turn off the disconnected consumers after eliminating the emergency power shortage .

Known switch remote control system [A.C. US H 02 H 3/30, H 02 J 13/00, No. 4965694, B.I. No. 4, 1990], containing separate control lines, switches, AND elements, a processor, a switch, allows you to control the switches by means of starting signals, but has limited functionality in terms of frequency unloading and large dimensions.

A known device for blocking the inclusion of a sectional switch [A.S. H 02 H 11/00, No. 1702480, B.I. No. 48, 1991], containing two transformers, a controlled key, a diode, a smoothing circuit, a reacting organ and a relay, allows you to control the switches as needed, has small dimensions, but has limited functionality in terms of frequency unloading.

The closest technical solution is a microprocessor-based multifunctional device of the frequency relay [Patent RU G 01 R 23/00, H 02 H 3/46, No. 2171475, Bull. No. 21, 07/27/01], containing an analog-to-digital converter, a scale amplifier, a unit comparison, two memory registers, a microprocessor, an input-output unit and a microprocessor system, allows you to organize the frequency unloading of various power systems in the conditions of an emergency shortage of active power.

The prototype also has a relatively large size, a fairly complex device layout and the difficult interaction of maintenance personnel with it during operation.

The purpose of the invention is to simplify the circuit of the device, reducing its overall dimensions and simplifying operation while maintaining the basic functions.

This goal is achieved by the fact that in a known device containing a comparison unit, a prohibition unit, two memory registers, a microprocessor and an input / output unit, the outputs of the first register connected to the inputs of the second register, the output of the comparison unit connected to the second input of the microprocessor, the output of which is connected with the input of the prohibition block, the group of inputs / outputs of the microprocessor is connected to the group of inputs of the first register and the group of outputs of the second register, the second group of inputs of which is connected to the first group of outputs of the microprocessor ora, the first group of outputs of the input-output unit is connected to the group of inputs of the microprocessor, the second group of outputs of the input-output unit is the group of relay outputs of the device, the group of inputs of which is the first group of inputs of the input-output unit, a counter and a timer are introduced, and the input of the counter is connected to output from the microprocessor input-output group, the second group of outputs of which is connected to the second group of inputs of the input-output unit, the input-output group of which is connected to the group of inputs and outputs of the microprocessor and to the group timer outputs, the first input of which is connected to the counter output, the second timer input is connected to the output of the comparison unit, the first and second inputs of which are device inputs, the first microprocessor input is connected to the timer output, the third input of which is connected to the output of the input-output unit, the third group the inputs of which are connected to the third group of microprocessor outputs, the first and second group of timer inputs are connected, respectively, to the group of outputs of the first register and to the first group of outputs of the microprocessor.

Figure 1 shows the structural diagram of the device.

Figure 2 is an example implementation of a comparison unit.

Figure 3 is an example implementation of an input / output block.

Figure 4 is an example implementation of the prohibition block.

Figure 1 marked:

1 - microprocessor, for example AT 89C52-24PI or similar with ports P0, P1, P2 and control inputs (outputs) ALE, PME, WR, RD, INT, T1 (a quartz resonator and a reset circuit RST are not shown);

2 - counter, for example K561IE16 or similar;

3 - block comparison;

4 - block prohibition;

5 - the first memory register, for example KR1554IR22 or similar;

6 - second memory register;

6-1 - for example, KR537RU13 or similar;

6-2 - for example KM573RF4 or similar;

7 - timer, for example K580VI53 or similar;

8 - input-output unit;

9 - a group of input circuits of discrete signals from the object;

10 - group of output control and signaling circuits;

11 - a group of input signal circuits from port P1 of the microprocessor;

12 - microprocessor backbone (address / data, synchronization signals).

Figure 2 marked:

K - a comparator, for example K554SAZA or similar;

R - resistors, for example C2-33 or similar;

V - diodes, for example KD521A or similar;

C - capacitors, for example K10-17 or similar;

T is a transistor, for example KT315A or similar;

DV - transistor optocoupler, for example SFN608-2 of the company "SIEMENS" or similar;

Tr - transformer.

Figure 3 marked:

13 - decoder, for example KR1554ND14 or similar;

14 is a register, for example KP1554IR23 or SN74HC374 or similar;

15 - a register, for example KR1554IR41 or similar;

16 - keys (amplifiers), for example K1109XT22 or similar;

17 - relays with contacts K, for example RM83-1021-35-1024 of the company "Relpol" or similar;

R - resistors, for example C2-33 or similar;

T - transistor, for example KT814B or similar;

18 - control panel:

18-1 - indicators (I), LEDs (C);

18-2 - keyboard;

19 - coordination unit;

D1 - diode, for example 2D510A or similar;

D2 - a zener diode, for example B255C39 or similar;

V - transistor BC547 or similar;

R - resistors, for example C2-33 or similar;

DV - optocoupler, for example Н608-2 or similar;

20 - Schmitt trigger, for example K155TL1 or similar.

In figure 4 are indicated:

T1 is a transistor, for example KT3102A, or similar;

T2 - transistor, for example KT837E, or similar;

R - resistors, for example C2-33 or similar.

The microprocessor device for automatic frequency unloading comprises a comparison unit 3, a prohibition block 4, two memory registers 5 and 6, a microprocessor 1, an input-output block 8, a counter 2 and a timer 7, the outputs of the first register 5 being connected to the inputs of the second register 6, the output of the block comparison 3 is connected to the second input "T1" of the microprocessor 1, the output "P2-4" of which is connected to the input of the prohibition block 4, the group of inputs / outputs 12 of the microprocessor 1 is connected to the group of inputs of the first register 5 and the group of outputs of the second register 6, the second group of inputs which with it is one with the first group of outputs "WR, RD" of microprocessor 1, the first group of outputs of input-output unit 8 is connected to the group of inputs "P1-2" of microprocessor 1, the second group of outputs 10 of input-output unit 8 is a group of relay outputs of the device, group of inputs 9 of which is the first group of inputs of the input-output unit 8, the input of the counter 2 is connected to the output "ALE" from the group of inputs-outputs 12 of the microprocessor 1, the second group of outputs "P2" of which is connected to the second group of inputs of the input-output unit 8, the group of inputs -output which is connected to a group in odes-outputs 12 of microprocessor 1 and a group of outputs of timer 7, the first input of "C2" of which is connected to the output "12" of counter 2, the second input of the timer "CEO" is connected to the output of the comparison unit 3, the first and second inputs of which are inputs of the device, the first input "INT" of microprocessor 1 is connected to output "Q2" of timer 7, the third input of "CS" of which is connected to the output of input-output unit 8, the third group of inputs of which is connected to the third group of outputs "P1-1" of microprocessor 1, the first "A "and the second" RD, WR "group of inputs of the timer 7 are connected, respectively, with the group in 5 moves the first register and outputs the first group "WR, RD, PME" microprocessor 1.

The device effectively disconnects the load at the beginning of a frequency accident when the specified settings for frequency, speed, time are reached, and automatically switches back on frequency when the settings are reached.

The device implements four functioning algorithms:

AChR1 - automatic frequency unloading without time delay with the possibility of blocking by the rate of frequency reduction;

AChR2 - automatic frequency discharge with time delay;

AChRS - automatic frequency unloading at the rate of frequency reduction;

ChAPV - automatic re-inclusion in frequency when certain conditions are met.

The device performs load shedding according to the AChP1 algorithm if the network frequency decreases below the value of the AChP1 setpoint in frequency, and the frequency of the decrease in frequency is less than the value of the setpoint blocking the action of AChP1 in speed.

The device disconnects the load according to the AChR2 algorithm after reducing the network frequency below the setting value for the starting frequency and maintaining the return frequency for some time.

The device performs load shedding according to the ASF algorithm if the rate of change of frequency exceeds the setpoint value for a certain number of periods of the controlled voltage.

When executing the ChAPV algorithm, the device issues three independent commands for connecting loads disconnected by the AChR1, AChR2 and AShR algorithms under certain conditions.

With the appropriate setting of the settings for the rate of frequency reduction in the network, it is possible to trigger all unloading algorithms in the process of one frequency accident.

The device measures the following parameters:

- frequency F;

- rate of change of frequency S;

- controls the lower voltage level of the network (0.4U _nom ) at which the reliability of the measurements may be violated. The frequency of the signal is measured by the sum of the durations of half-periods of voltage

where T ₁ - the duration of the odd half-cycle,

T ₂ is the duration of an even half-period.

The rate of change of frequency is calculated as the first derivative of the frequency of the time signal

where dF is the frequency increment over time dt;

dt is a short time interval.

To estimate the first derivative of the frequency, the method of numerical differentiation of data is applied.

To estimate the frequency of a periodic signal, a time measurement method is used.

The hardware-based implementation of the algorithms is implemented as follows: the controlled signal enters the comparison unit 3 through a transformer Tr, which provides harmonic isolation, to the comparator K and the optocoupler DV with the transistor T, which provide control of the lower voltage level of the network by generating a signal at the input S of the comparator K, while the comparator , in case of violation of the input voltage level, gives a signal to microprocessor 1, through which the microprocessor generates a control signal from port P2-4 to the inhibit block 4, which relieves voltage e with the relay 17 of the input-output unit 8, and the display And receives certain information. If the lower level of the input voltage is normal, then the comparator generates a sequence of rectangular pulses with the frequency of the controlled analog signal, i.e. the binary signal "meander" is formed from the original signal, which switches between itself two channels for measuring time intervals (microprocessor timer T1 and timer 7). Timer 7 is synchronized by an ALE signal divided by counter 2 to the half-cycle frequency. Thus, one timer measures the duration of an even half-cycle, and the other an odd one. Each transition of the monitored voltage through zero activates the inclusion of one of the timers, stops counting the second timer and reads its value. This implementation allows you to correctly handle possible fluctuations in the control signal "meander" type 0-1-0 in the zone of transition through zero of the controlled voltage. At each time point, N estimates of the half-cycle duration in timer samples are stored in the microprocessor memory.

T _i = K _t · t _i , i = 1 ... N

where T _i is the current estimate of the duration of the half cycle of cycles,

To _t - the duration of quantization in time.

The current estimate of the signal frequency is calculated once per period according to the formula

where f $\genfrac{}{}{0ex}{}{\text{T}}{\text{i}}$ - current frequency estimate;

T _i - the duration of the current half-cycle;

T _i-1 - the duration of the previous half-cycle.

To reduce the effects of noise and random processes, the primary frequency information is smoothed taking into account the weight coefficients

where F _i is the smoothed estimate of the frequency,

K ₁ , K ₂ , K ₃ - weighting factors.

The selection of weights is carried out at the development stage according to the results of modeling and prototype tests.

Measuring the rate of change of frequency.

The initial information for measuring the rate of change of frequency are arrays of N smoothed estimates of the frequency and duration of half-periods.

The speed estimate is calculated once per half period according to the formula

where s $\genfrac{}{}{0ex}{}{\text{N}}{\text{i}}$ - a current estimate of the rate of change of frequency based on N frequency samples,

F _i - the current estimate of the rate of change of frequency,

F _in - estimate of the frequency change rate for the last N ^th period,

t _iK is an estimate of the duration of N half-periods.

The measurement results are stored in the microprocessor memory

1. Here, port P0, via bus 12, receives information on the status of discrete inputs from input-output unit 8, and information from port keys 18-2 of the input-output block comes to port P1-2. The microprocessor performs logical processing of the incoming information (comparing the measured parameters of the controlled analog signal with the settings, counting the time delays, etc.) and generates alarm commands that are transmitted via bus 11 to the LEDs C of the control panel 18 and to the output relays 17 installed in the unit input-output 8. In addition, the microprocessor 1 prepares information for display on the display indicators And 18-1. The display register 15 and the data register 14 are controlled by a microprocessor through a decoder 13.

Thus, the device, in addition to measuring with high accuracy and in accordance with the frequency algorithms:

1) measures the rate of change of frequency and controls the lower voltage level of the network;

2) provides:

- automatic frequency unloading without time delay with the possibility of blocking by the rate of frequency reduction, i.e. performs load disconnection after lowering the mains frequency below the limit of the frequency response setting value and does not disconnect the load if the voltage decreases at a speed higher than the setting value for the voltage frequency decrease rate;

3) load shedding according to the AChR2 algorithm after reducing the network frequency below the setting value for the start frequency and maintaining the return frequency for some time;

4) automatic reconnection by frequency of the ChAPV when certain conditions are met, for example:

a) the corresponding AFR algorithm worked;

b) the network frequency is set higher than the set point, etc .;

5) local input, storage and display of settings.

For reliability, the device has a self-diagnosis system, which consists of two subsystems - background self-diagnosis, which provides control over the operability of the main components of the device during the entire period of operation, and a set of tests run on call.

Background self-diagnosis is carried out continuously, throughout the entire operation of the device, providing control over the operability of all major nodes. Self-diagnosis results are analyzed by a microprocessor. The diagnostic composition includes:

- verification of discrete inputs;

- display testing (software known methods);

- keyboard testing (software known methods).

Thus, the device has a simple circuit (a large-scale amplifier, an analog-to-digital converter and a microprocessor system are excluded), respectively, smaller (twice) dimensions and simpler operation (control of four function buttons - entering settings, reading settings on eight-segment indicators) and provides the implementation of the basic functions of frequency unloading.

Claims (1)

A microprocessor-based device for automatic frequency unloading, comprising a comparison unit, a prohibition unit, two memory registers, a microprocessor that performs logical processing of the incoming information, compares the measured parameters of the controlled analog signal with the settings, counts the time delays and generates alarm commands, and the input-output unit, and outputs the first register is connected to the inputs of the second register, the output of the comparison unit is connected to the second input of the microprocessor that performs logical processing after fallen information, comparing the measured parameters of the controlled analog signal with the settings, counting the time delays and generating alarm commands, the output of which is connected to the input of the prohibition block, a group of inputs and outputs of the microprocessor that performs logical processing of the incoming information, comparing the measured parameters of the controlled analog signal with the settings, counting time delays and the formation of signaling commands, connected to the group of inputs of the first register and the group of outputs of the second register, second the group of inputs of which is connected to the first group of outputs of a microprocessor that performs logical processing of the incoming information, comparing the measured parameters of the controlled analog signal with the settings, counting the time delays and generating alarm commands, the first group of outputs of the input-output block is connected to the group of inputs of the microprocessor that performs the logical processing of the incoming information, comparison of the measured parameters of the controlled analog signal with the settings, the countdown of the time delays and signaling commands, the second group of outputs of the input-output unit is a group of relay outputs of the device, the group of inputs of which is the first group of inputs of the input-output unit, characterized in that a counter and a timer are introduced into it, and the input of the counter is connected to the output from the group of inputs the outputs of a microprocessor that performs logical processing of the incoming information, comparing the measured parameters of the controlled analog signal with the settings, counting the time delays and generating alarm commands, the second group the outputs of which are connected to the second group of inputs of the input-output unit, the group of inputs and outputs of which are connected to the group of inputs and outputs of a microprocessor that performs logical processing of the incoming information, compares the measured parameters of the controlled analog signal with the settings, counts the time delays and generates alarm commands, and a group of timer outputs, the first input of which is connected to the output of the comparison unit, the first and second inputs of which are inputs of the device, the first input of the microprocessor, logically processing the incoming information, comparing the measured parameters of the controlled analog signal with the settings, counting the time delays and generating alarm commands, it is connected to the output of the timer, the third input of which is connected to the output of the input-output block, the third group of inputs of which are connected to the third group of outputs of the microprocessor, performing logical processing of the incoming information, comparing the measured parameters of the controlled analog signal with the settings, the countdown of the time delays and signaling commands, the first and second groups of timer inputs are connected respectively to the group of outputs of the first register and to the first group of outputs of a microprocessor that performs logical processing of the incoming information, compares the measured parameters of the controlled analog signal with the settings, counts the time delays and generates alarm commands.

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