RU2123765C1 - System for transmitting and receiving information by variable-length code - Google Patents

Abstract

FIELD: communications engineering; telemechanics, telemetering; data transmission over communication channels by codes of various correcting capacities. SUBSTANCE: system that has on sending end switch 5, clock generator 7, polynomial coder 8, frequency oscillator unit 9, variable-frequency allocator 10, coding unit 12, channel state estimating unit 13, matching unit 14; and on receiving end, matching unit 17, frequency coder 18, variable-frequency allocator 21, AND gates 22_f-22_H, decoding units 22_f-22_H, and data output unit 25 is provided, in addition, with trigger-starting unit 4, address shaper 6, and sync signal shaper 11 on sending end, as well as sync signal selector 19, clock pulse generator unit 20, and address decoder of receiving end. EFFECT: reduced utilization factor of communication channel due to transfer from endless-loop to random data transmission mode enabling increase in number of sources and receivers of messages transmitting information over allocated channel. 21 dwg

Description

 The present invention relates to the field of communication technology and can be used in telemechanics, telemetry, when transmitting data via communication channels with codes of various corrective ability, which meets the various requirements for the levels of reliability of message transmission from various sources.

 A known system for transmitting and receiving information with a variable-length code (see ed. Certificate of the USSR N 824464, M. cl. 3 H 04 J 3/16, H 04 L 5/22, published in the official letter OIPOTE N 15 from 04/23/81), containing on the transmitting side a signal driver, an AND element, an OR element, a distributor, an encoder, an encoding unit, a control unit, a clock generator, a matching unit, while the inputs of the signal conditioners are system inputs, the outputs of the signal conditioners are connected to the first the inputs of the elements AND, the outputs of the distributor are connected to the inputs of the cipher torus, control unit and with the second inputs of AND elements, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the information input of the coding unit, the output of the clock pulse generator is connected to the clock inputs of the control unit and the coding unit, the encoder outputs are connected to the group of control inputs of the block encoding, the first output of the control unit is connected to the control input of the distributor and to the first control input of the coding unit, the second output of the control unit is connected to the second control in the coding unit, the output of which is connected to the input of the matching unit, the output of which is connected to the input of the communication channel, and on the receiving side, the matching unit, control unit, distributor, I elements, decoding units, a decision unit, while the output of the communication channel is connected to the input matching unit, the information output of which is connected to the information input of the decision unit and the first inputs of AND elements, the clock output of the matching unit is connected to the clock inputs of the control unit, the decision unit and decoding units , the outputs of the distributor are connected to the inputs of the control unit, with the group of control inputs of the decision block and the second inputs of the elements And, the outputs of which are connected to the corresponding groups of inputs of the decision block, the output of the control unit is connected to the control input of the distributor and the control input of the decision block, the outputs of which are the outputs of the system .

 The disadvantage of this system is that it does not provide adaptation to the changing characteristics of the communication channel, and can also be applied only in a cyclic mode of information transfer.

 Signs of an analogue that coincide with the features of the claimed technical solution on the transmitting side are a polynomial encoder, a coding unit, a clock, a matching unit and on the receiving side a matching unit, AND elements, decoding blocks, a solving unit.

 The reasons that impede the achievement of the required technical result are the peculiarities of the implementation of the known system, which do not allow changing the corrective ability and code length depending on the channel condition, as well as ensure sporadic synchronous operation of the transmitting and receiving devices and determining the number of the source transmitting the message.

 A known system for transmitting and receiving information with a variable-length code (see ed. Certificate of the USSR N 1124436, M. cl. 3 H 04 L 1/10, published in official bulletin BI N 42 of 11/15/84), containing side, code converters, AND elements, signal distributor, OR element, coding unit, clock pulse generator, tunable distributor, communication channel status estimator, polynomial encoder, frequency generator block, control signal decoder, signal conversion unit, while the inputs of the code converters are system inputs the outputs of the code converters are connected to the first inputs of the AND elements, the outputs of the distributor are connected to the second inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the information input of the coding block, the output of the clock generator is connected to the clock inputs of the tunable distributor and coding block, the first output of the tunable distributor is connected to the inputs of the channel condition estimator, the distributor and the first control input of the coding block, the second output One tunable distributor is connected to the second control input of the coding block, the outputs of the communication channel state estimation block are connected to the inputs of the tunable distributor, frequency generator block, and polynomial encoder, the outputs of which are connected to the control input group of the coding block, the output of which is connected to the first input of the signal conversion block, the second input of which is connected to the output of the return channel, the output of the frequency generator unit is connected to the third input of the signal conversion unit, the first output for which it is connected to the input of the direct channel, the second output of the signal conversion unit is connected to the input of the control signal decoder, the outputs of which are connected to the inputs of the channel condition estimator, and on the receiving side, the signal conversion unit, code number decoder, I elements, decoders, tunable distributor , a reception distributor, a data output unit, a control signal generator, wherein the output of the direct channel is connected to the first input of the signal conversion unit, the first output of which is connected to the input return channel, the second output of the signal conversion unit is connected to the information input of the data output unit and the first inputs of AND elements, the third output of the signal conversion unit is connected to the clock inputs of the tunable distributor, data output unit and decoders, the group of outputs of the signal conversion unit is connected to the inputs of the code number decoder the outputs of which are connected to the inputs of the tunable distributor and the second inputs of the elements And, the outputs of which are connected to the information inputs of the decoders, g output groups of which are connected to the corresponding input groups of the data output unit and control signal generator, the output of which is connected to the second input of the signal conversion unit, the output of the tunable distributor is connected to the control input of the data output unit and the input of the receive distributor, the outputs of which are connected to the group of control inputs of the output unit data whose outputs are system outputs.

 However, in this system, when choosing codes, various requirements for the fidelity of transmitting messages from various sources are not taken into account, in addition, it is difficult to use the system with the most economical sporadic mode of information transfer.

 Signs of an analogue that coincide with the features of the claimed technical solution on the transmitting side are a channel condition estimation unit, a clock pulse generator, a tunable polynomial encoder distributor, a coding unit, a frequency generator unit, a signal conversion unit, and on the receiving side a signal conversion unit, a number decoder code, tunable dispenser, AND elements, decoding blocks, data output unit.

 The reasons that impede the achievement of the required technical result are the peculiarities of the implementation of the known system, which do not allow changing the corrective ability and code length depending on the importance of the transmitted message, as well as provide sporadic synchronous operation of the transmitting and receiving devices and determining the number of the source transmitting the message.

 The closest to the proposed combination of functional and design features is an adaptive information transmission system (see ed. Certificate of the USSR N 1109927, M. class. 3 H 04 L 5/22, published in official bulletin BI N 31 of 23.08. 84), containing on the transmitting side of the signal conditioner, AND elements, OR element, signal distributor, channel status estimator, coding unit, tunable distributor, clock generator, encoder, frequency generator unit, matching unit, while the signal conditioner inputs are inputs system outputs, the outputs of the signal conditioners are connected to the first inputs of the AND elements, the outputs of the distributor are connected to the inputs of the channel state estimation unit and the second inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the information input of the coding unit, the output of the clock generator is connected with clock inputs of tunable distributor and coding block, outputs of channel condition estimator are connected to inputs of frequency generators block, tunable distributor and an encoder whose outputs are connected to the group of control inputs of the encoding unit, the first output of the tunable distributor is connected to the input of the signal distributor and the first control input of the encoding unit, the second output of the tunable distributor is connected to the second control input of the encoding unit, the output of which is connected to the first input of the matching unit, the output of the block of frequency generators is connected to the second input of the matching block, the output of which is connected to the input of the communication channel, and on the receiving side I agree unit, decoder, AND elements, data output unit, tunable distributor, decoding blocks, signal distributor, while the output of the communication channel is connected to the input of the matching unit, the information output of which is connected to the information input of the data output unit and the first inputs of the I elements, clock output matching unit is connected to the clock inputs of the data output unit, tunable distributor and decoding units, the control outputs of the matching unit are connected to the inputs of the decoder, the outputs of which are connected to the inputs of the tunable distributor and the second inputs of AND elements, the outputs of which are connected to the information inputs of the decoding blocks, the groups of outputs of which are connected to the corresponding groups of inputs of the data output unit, the output of the tunable distributor is connected to the control input of the data output unit and the input of the distributor, the outputs of which are connected to a group of control inputs of the data output unit, the outputs of which are system outputs.

 In this system, when choosing the correcting ability of the code, both the importance of the transmitted message and the interference situation in the channel are taken into account.

 However, the known system cannot be applied in the most effective from the point of view of using the channel sporadic mode of information transfer, in which messages are transmitted to the channel as they occur, which is a significant drawback of the system.

 Signs of an analogue that coincide with the features of the claimed technical solution on the transmitting side are a channel condition estimation unit, a clock pulse generator, a tunable distributor, a polynomial encoder, a coding unit, a frequency generator unit, a matching unit, and on the receiving side, a matching unit, a decoder tunable distributor, AND elements, decoding blocks, data output unit.

 The reasons that impede the achievement of the required technical result are the peculiarities of the implementation of the known system, which do not allow for sporadic synchronous operation of the transmitting and receiving devices and determining the number of the source transmitting the message.

 The problem to which the invention is directed, is to increase the efficiency of use of the communication channel by reducing the time spent on sending messages.

 The technical result from the application of the invention is to reduce the utilization rate of the communication channel due to the transition from cyclic to sporadic transmission of information from sources with variable-length codes. This allows you to increase the number of users (sources and recipients of messages) transmitting information on a dedicated channel.

 To achieve a technical result in a system for transmitting and receiving information with a variable-length code, containing on the transmitting side a switch, a channel status estimator, a coding unit, a tunable distributor, a clock generator, a polynomial encoder, a block of frequency generators, a matching unit, and a group of information the inputs of the switch is a group of information inputs of the system, the information output of the switch is connected to the first information input of the coding unit, the output of the clock cycle output pulses is connected to the clock inputs of the tunable distributor and coding unit, the group of control outputs of the channel state estimation unit is connected to the group of control inputs of the frequency generator block, tunable distributor and polynomial encoder, the group of control outputs of which is connected to the group of control inputs of the coding block, the first control output of the tunable the distributor is connected to the first control input of the coding unit, the second control output of the tunable distributor The device is connected to the second control input of the coding unit, the information output of which is connected to the first information input of the matching unit, the control output of the frequency generator unit is connected to the control input of the matching unit, the channel output of which is connected to the input of the communication channel, and on the receiving side, the matching unit, decoder frequencies, AND elements, data output unit, tunable distributor, decoding blocks, while the output of the communication channel is connected to the channel inputs of the frequency decoder and the block the information output of which is connected to the first inputs of the elements And, the group of control outputs of the frequency decoder is connected to the group of control inputs of the tunable distributor and the second inputs of the elements And, the outputs of which are connected to the information inputs of decoding blocks, the outputs of the first group of control outputs of the tunable distributor are connected respectively to the first the control inputs of the decoding blocks, the outputs of the second group of control outputs of the tunable distributor are connected to responsibly with the second control inputs of the decoding blocks, the control output of the tunable distributor is connected to the control input of the frequency decoder and the third control inputs of the decoding blocks, the first groups of information outputs of which are connected to the corresponding groups of information blocks of the data output unit, the groups of information outputs of which are the groups of information outputs of the system, In addition, a start-up unit, an address former and the clock signal, while the group of control inputs of the start-up unit is the group of control inputs of the system, and the group of control outputs of the switch is the group of control outputs of the system, the group of control outputs of the start-up block is connected to the groups of control inputs of the channel state evaluation unit, the switch, and the first group of control inputs of the address generator the information output of which is connected to the second information input of the coding unit, the first and second control inputs of the connection switch respectively, with the third and second control outputs of the tunable distributor, the control output and input of the start-up block are connected respectively to the control input and the first output of the tunable distributor, the group of control outputs of which is connected to the second group of control inputs of the address shaper, the fourth and fifth control outputs of the tunable distributor are connected respectively with the first and second control inputs of the clock driver, the information output of which connected to the second information input of the matching unit, and on the receiving side, the clock selector, clock generator unit, address decoder, while the information input of the clock selector is connected to the information output of the matching unit, the control output of the clock selector is connected to the control input of the tunable distributor and the first control the input of the clock generator block, the second control input of which is connected to the control output of the tunable For, the output of the clock generator block is connected to the clock inputs of the tunable distributor and decoding blocks, the second groups of information outputs of the decoding blocks are connected to the corresponding groups of information inputs of the address decoder, the control outputs of the decoding blocks are connected to the corresponding inputs of the group of control inputs of the address decoder, the group of control outputs of which connected to the group of control inputs of the data output unit.

 The presence of a causal relationship between the technical result and the features of the claimed invention is proved by the following logical premises.

 The most expensive part of any information transmission system is the communication channel, so the effectiveness of the system is determined primarily by the efficiency of the use of the channel. The most effective use of the channel occurs in the sporadic mode of information transfer, when sources are not polled cyclically, and messages are transmitted to the communication channel as they arise. In this case, it is necessary to introduce a start-up unit on the transmitting side, which would ensure that the system starts when messages occur, and was also an arbiter when messages from several sources occur simultaneously. In addition, to ensure synchronous operation of the transmitting and receiving devices of the system, it is necessary to introduce a clock driver on the transmitting side, and a clock selector, as well as a clock pulse generator operating in the start-stop mode, on the receiving side. Finally, to identify the sources and recipients of messages in the system, you must enter the source address generator (on the transmitting side) and the address decoder (on the receiving side).

 In the future, for definiteness, we assume that a pulse is used as a clock signal, the duration of which is U times the duration of an elementary signal; a sequential decoding mode according to the correction code syndrome is used (see Dmitriev V.I. Applied Information Theory. - M .: Higher School, 1989), in which the decoding time is 2N ticks, where N is the code length.

The essence of the proposed embodiment of the invention is illustrated by drawings. Figure 1 shows the structural diagram of the transmitting device of the system, figure 2 is a structural diagram of the receiving device of the system, figure 3 is a functional diagram of the start-up unit 4, figure 4 is a functional diagram of the switch 5, in fig. 5 is a functional diagram of an address generator 6; FIG. 6 is a functional diagram of a polynomial encoder 8; FIG. 7 is a functional diagram of a frequency generator unit 9; FIG. 8 is a functional diagram of a tunable distributor 10 of a transmission device; FIG. 9 is a functional diagram of a clock driver 11, FIG. 10 is a functional diagram of a coding unit 12, in FIG. 11 is a functional block diagram of a channel condition estimator 13, FIG. 12 is a functional diagram of a matching unit 14 of a transmitting device, FIG. 13 is a functional diagram of a receiver matching unit 17, FIG. 14 is a functional diagram of a frequency decoder 18, FIG. 15 is a functional diagram of a clock selector 19, in FIG. 16 is a functional block diagram of a receiver pulse generator 20; FIG. 17 is a functional diagram of a tunable distributor 21 of a receiving device; FIG. 18 is a functional diagram of a decoding unit 23 ₂ , in FIG. 19 is a functional diagram of an address decoder 24, FIG. 20 is a functional diagram of a data output unit 25, in FIG. 21 is a timing diagram explaining the operation of the system.

The structural diagram of the transmitting device of the system (see figure 1) contains: 1 ₁ -1 _B -group of control inputs; 2 ₁ -2 _B - group of information inputs; 3 ₁ -3 _B - group of control outputs; 4 - start-up block; 5 - switch; 6 - address generator; 7 - clock generator; 8 - polynomial encoder; 9 - block frequency generators; 10 - tunable dispenser; 11 - shaper clock; 12 - coding unit; 13 - channel state estimation unit; 14 - block matching; 15 - channel output.

The structural diagram of the receiving device of the system (see figure 2) contains: 16 - channel input; 17 - matching unit; 18 - frequency decoder; 19 - clock selector; 20 is a block of a clock generator; 21 - tunable distributor; 22 ₁ -22 _H - elements And; 23 ₁ -23 _H - decoding blocks; 24 - address decoder; 25 - data output unit; 25 _I1 -26 _IW , I = 1, B, -B groups of information outputs of the system.

Functional diagram of the starting unit 4 (see figure 3) contains: 1 ₁ -1 ₃ - a group of control inputs; 27 - control input; 28 ₁ -28 ₃ , 30 ₁ -30 ₃ - the first and second groups of RS triggers, respectively; 29 ₁ -29 ₃ , 31 ₁ -31 ₃ - respectively, the first and second groups of elements And; 32 - element OR; 33 - shaper of the leading edge of the pulses; 34 ₁ -34 ₃ - group of control outputs; 35 - control output.

Functional diagram of the switch 5 (see Fig. 4) contains: 2 ₁ -2 ₃ - a group of information inputs; 3 ₁ -3 ₃ - group of control outputs; 34 ₁ -34 ₃ - group of control inputs; 36, 37 - respectively, the first and second control inputs; 38 - RS - trigger; 39 ₁ -39 ₃ , 40 ₁ -40 ₃ - respectively, the first and second groups of elements And; 41 - element OR; 42 - element And; 43 - information output.

Functional diagram of the shaper 6 addresses (see Fig. 5) contains: 34 ₁ -34 ₃ , 44 ₁ -44 _2, respectively, the first and second groups of control inputs; 45 - binary code encoder; 46 ₁ -46 ₂ -group of elements And; 47 - element OR; 48 - information output.

The functional diagram of the encoder 8 polynomial (see Fig. 6) contains: 49 ₁ -49 ₄ - a group of control inputs; 50 ₁ -50 ₅ - group of elements OR; 51 ₁ -51 ₇ - group of control outputs.

Functional diagram of block 9 frequency generators (see Fig.7) contains: 49 ₁ -49 ₄ - group of control inputs; 52 ₁ -52 ₄ - a group of harmonic oscillation generators (carrier frequencies); 53 ₁ -53 ₄ -group of mounting elements And (keys); 54 - mounting OR element (assembly diagram); 55 - control output.

Functional diagram of the tunable distributor 10 of the transmitting device (see Fig. 8) contains: 27 - the first control output; 35 - control input; 36, 37 - respectively, the third and second control outputs; 44 ₁ -44 ₂ -group of control outputs; 49 ₁ -49 ₄ -group of control inputs; 56 - clock input; 57- RS-trigger; 58 - shift register; 59.60 - respectively, the fourth and fifth control outputs; 61 ₁ -61 ₄ - a group of elements And; 62 is an OR element.

 Functional diagram of the driver 11 clock (see Fig. 9) contains: 59.60 - respectively, the first and second control inputs; 63 - RS-trigger; 64 - information output.

The functional block diagram of the coding unit 12 (see Fig. 10) contains: 27.37, respectively, the first and second control inputs; 43, 48, respectively, the first and second information inputs; 51 ₁ -51 ₇ - group of control inputs; 56 - clock input; 65 ₁ -65 ₇ - a group of elements And; 66 ₁ -66 ₇ - a group of adders modulo two; 67 ₁ -67 ₉ - group of D-flip-flops; 69 ₁ , 69 ₂ - elements And; 70.71 - OR elements; 72 - information output.

The functional block diagram 13 of the channel state assessment (see 11) contains: 34 ₁ -34 ₃ - a group of control inputs; 49 ₁ -49 ₄ - group of control outputs; 73 ₁ -73 ₃ - a group of generators of a Poisson sequence of pulses; 74 ₁ -74 ₃ - a group of elements And; 75 ₁ -75 ₃ - a group of shift registers; 76 ₁₁ -76 ₁₄ , I = 1,3, - three group of OR elements; 77 ₁₁ -77 ₁₄ , I = 1.3 - three groups of elements And; 78 ₁ -78 ₄ -group of elements OR.

 The functional diagram of the block 14 coordination of the transmitting device (see Fig. 12) contains: 15 - channel output; 55 - control input; 64.72 - respectively, the second and first information inputs; 79 - element OR; 80 - modulator; 81 - bandpass filter.

 Functional diagram of the block 17 coordination of the receiving device (see Fig. 13) contains: 16 - channel input; 82 - band-pass filter; 83 - demodulator; 84 - information output.

Functional diagram of the decoder 18 frequencies (see Fig. 14) contains: 16 - channel input; 85 ₁ -85 ₄ - bandpass filter group; 85 ₁ -86 ₄ - group of Schmitt triggers (threshold devices); 87 ₁ -87 ₄ -group of RS-triggers; 88 ₁ -88 ₄ -group of control outputs; 89 - control input.

 Functional diagram of the selector 19 of the clock signal (see Fig. 15) contains: 84 - information input; 90 - single pulse generator (single vibrator), the duration of which is equal to the duration of the clock signal; 91, 92 - shaper signals of the leading edge of the pulses; 93 - element And; 94 - control output.

 Functional diagram of the block 20 of the clock generator (see Fig. 16) contains: 89, 94, respectively, the second and first control inputs; 95 - high-frequency pulse generator; 96 - RS-trigger; 97 is a binary counter that performs the functions of a frequency divider; 98 - clock output.

The functional diagram of the tunable distributor 21 of the receiving device (see Fig. 17) contains: 88 ₁ -88 ₄ -group of control inputs; 89 - control output; 94 - control input; 98 - clock input; 99 ₁ , 99 ₂ - RS-triggers; 100 - driver of the signal leading edge of the pulse; 101 - shift register; 102 ₁ -102 ₄ , 103 ₁ -103 ₄ - respectively, the first and second group of elements And; 104 ₁ -104 ₄ , 105 ₁ -105 ₄ - respectively, the first and second groups of control outputs; 106 is an OR element.

Functional diagram of the decoding unit 23 ₂ (see Fig. 18) contains: 89 - the third control input; 98 - clock input; 104 ₂ , 105 ₂ - respectively, the first and second control inputs; 107 ₂ - information input; 108 ₂ - element OR; 109 ₂ - shift register; 110 ₂ - RS-trigger; 111 _2- element And; 112 ₂ - adder modulo two; 113 ₁₂ -113 ₅₂ - a group of adders modulo two; 114 ₁₂ -114 ₅₂ - a group of D-triggers; 115 ₂ , 116 ₂ - elements of And; 117 ₁₂ -117 ₂₂ , 118 ₁₂ -118 ₄₂ - respectively, the second and first groups of information outputs; 119 ₂ - control output.

The functional diagram of the address decoder 24 (see Fig. 19) contains: 117 _1J -117 _2J , J = 1.4 - four groups of information inputs; 119 ₁ -119 ₄ - group of control inputs; 120 ₁ , 120 ₂ - two elements OR; 122 - binary code decoder; 121 - OR element, 123 ₁ -123 ₃ - a group of control outputs.

The functional diagram of the data output unit 25 (see Fig. 20) contains: 118 _1J -118 _4J , J = 1.4, - four groups of information inputs; 123 ₁ -123 ₃ - group of control inputs; 124 ₁ -124 ₄ -group of elements OR; 125 ₁ -125 ₃ - a group of memory registers; 126 _I1 -126 _I4 , I = 1,3, - three groups of information outputs.

Functional diagram of the start-up block 4, switch 5, address shaper 6, polynomial encoder 8, frequency generator block 9, tunable distributor 10 of the transmitting device, coding block 12, channel condition estimator 13, frequency decryptor 18, tunable distributor 21 of the receiving device, decoding block 23 ₂ , address decoder 24, data output unit 25 are given for an example implementation of a system for transmitting and receiving information with variable-length codes when the number of message sources is B = 3; the number of bits of the address code V = 2; the number of bits of the message W = 4; H = 4 cyclic codes are used with parameters (10, 6), (11, 6), (14, 6), (15, 6), where the first number in brackets indicates the length N _J , J = 1,4, of the code, and the second number is the number M = V + W of information symbols in the code combination; the elongation factor of the clock U = 2.

 Elements of a system for transmitting and receiving information by variable-length codes are interconnected as follows.

In the transmitting device (see Fig. 1), the group of control inputs 1 ₁ -1 _{B of the} start-up unit 4 is a group of control inputs of the system, the group of information inputs 2 ₁ -2 _{B of} switch 5 is a group of information inputs of the system, group of control outputs 3 ₁ -3 _B switch 5 is a group of control outputs of the system. The group of control outputs of the start-up unit 4 is connected to the groups of control inputs of the switch 5, the first group of control inputs of the address shaper 6 and the group of control inputs of the channel state estimation unit 13. The information output of the switch 5 is connected to the first information input of the coding unit 12. The information output of the address generator 6 is connected to the second information input of the encoding unit 12, the output of the clock generator 7 is connected to the clock inputs of the tunable distributor 10 and the encoding unit 12. The group of control outputs of the encoder 8 of the polynomial is connected to the group of control inputs of the coding unit 12, the output of the block 9 of the frequency generator is connected to the control input of the matching unit 14. The group of control outputs of the tunable distributor 10 is connected to the second group of control inputs of the address shaper 6, the first control output of the tunable distributor 10 is connected to the control input of the start-up block 4 and the first control input of the coding block 12. The second control output of the tunable distributor 10 is connected to the second control inputs of the switch 5 and the coding unit 12. The third control output of the tunable distributor 10 is connected to the first control input of the switch 5, the fourth and fifth control outputs of the tunable distributor 10 are connected respectively to the first and second control inputs of the clock generator 11, the information output of which is connected to the second information input of the matching unit 14, the information output of block 12 encoding is connected to the first information input of the matching unit 14, a group of control outputs of the soy channel state estimation unit 13 inena with groups of control inputs of the polynomial of the encoder 8, 9 Block frequency generators tunable distributor 10. The channel 15 output matching unit 14 is a channel output system.

In the receiving device (see Fig. 2), the channel input 16 of the system is connected to the channel inputs of the matching unit 17 and the frequency decoder 18. The information output of the matching unit 17 is connected to the information input of the clock selector 19 and the first inputs of the elements And 22 _J , J = 1, H. The group of control outputs of the frequency decoder 18 is connected to the group of control inputs of the tunable distributor 21 and Jth, J = 1, H, the group output is connected to the second input of the element And 22 _J , J = 1, H. The control output of the clock selector 19 is connected to the first control input of the clock generator unit 20 and the control input of the tunable distributor 21. The output of the clock generator block 20 is connected to the clock inputs of the tunable distributor 21 and decoding blocks 23 _J , J = 1, H. The control output of the tunable distributor 21 is connected to the control input of the frequency decoder 18, the second control input of the clock generator unit 20 and the third control inputs of the decoding units 23 _J , J = 1, H, J-e, J = 1, H, the outputs of the first and second groups of control outputs tunable distributor 21 are connected respectively to the first and second control inputs of the decoding unit 23 _J , J = 1, H. The output of the element And 22 _J , J = 1, H, is connected to the information input of the decoding unit 23 _J , J = 1, H. The first group of information outputs of the decoding unit 23 _J , J = 1, H, is connected to the Jth, J = 1, H, the group of information inputs of the data output unit 25, the second group of information outputs of the decoding unit 23 _J , J = 1, H, connected to the Jth, J = 1, H, group of information inputs of the address decoder 24, the control output of the decoding unit 23 _J , J = 1, H, connected to the Jth, J = 1, H, the input of the group of control inputs of the decoder 24 addresses, the group of control outputs of which is connected to the group of control inputs of the data output unit 25, B of the groups of information outputs 26 _I1 -26 _IW , I = 1, B, which Horn are groups of information outputs of the system.

In the start-up block 4 (see Fig. 3) for an example implementation, the inputs 1 ₁ -1 _{3 of the} group of control inputs are connected respectively to the inputs of the installation in the state "1" of RS-flip-flops 28 ₁ -28 ₃ . The control input 27 is connected to the first inputs of the elements And 31 ₁ -31 ₃ . The direct inputs of the RS-flip-flops 28 ₁ -28 _{3 are} connected respectively to the first inputs of the elements And 29 ₁ -29 ₃ , the inverse output of the RS-flip-flop 28 _{1 is} connected to the second inputs of the elements And 29 ₂ , 29 ₃ , the inverse output of the RS-flip-flop 28 ₂ with the third input of the element And 29 ₃ . The outputs of the elements And 29 ₁ -29 _{3 are} connected respectively to the inputs of the installation in the state "1" of RS-flip-flops 30 ₁ -30 ₃ , the direct outputs of which are connected respectively to the second inputs of the elements And 31 ₁ -31 ₃ , the inputs of the element OR 32, the outputs 34 ₁ -34 ₃ groups of control outputs. The inverse output of the RS-trigger 30 _{2 is} connected to the third input of the And 29 ₁ element, the inverse output of the RS-trigger 30 _{3 is} connected to the second input of the And 29 ₁ element and the third input of the And 29 ₂ element. The outputs of the elements 31 ₁ -31 _{3 are} connected respectively to the reset inputs of the RS-flip-flops 28 ₁ -28 ₃ , 30 ₁ -30 ₃ . The output of the OR element 32 is connected to the input of the signal shaper 33 of the leading edge of the pulses, the output of which is connected to the control output 35.

In switch 5 (see Fig. 4), for an example implementation, the inputs 2 ₁ -2 _{3 of the} group of information inputs are connected respectively to the first inputs of the elements AND 39 ₁ -39 ₃ , the inputs 34 ₁ -34 _{3 of the} group of control inputs are connected respectively to the second inputs of the elements And 39 ₁ - 39 ₃ and the first inputs of the elements And 40 ₁ - 40 ₃ . The first 36 and second 37 control inputs are connected respectively to the inputs of setting to "12" and resetting the RS flip-flop 38, the output of which is connected to the second input And 42 and the second inputs of the elements And 40 ₁ -40 ₃ . The outputs of the elements And 39 ₁ -39 ₃ connected to the inputs of the element OR 41. The outputs of the elements And 40 ₁ -40 ₃ connected to the outputs 3 ₁ -3 ₃ groups of control outputs. The output of the OR element 41 is connected to the first input of the And 42 element. The output of the And 42 element is connected to the control output 43.

In the address generator 6 (see Fig. 5), for an example implementation, the inputs 34 ₁ -34 _{3 of the} first group of control inputs are connected to the inputs of the encoder 45 of the binary code. The inputs 44 ₁ -44 _{2 of the} second group of control inputs are connected respectively to the second inputs of the elements And 46 ₁ -46 ₂ . The first output of the binary code encoder 45 is connected to the first input of the AND element 46 ₁ , the second output of the encoder 45 is connected to the first input of the AND element 46 ₂ . The outputs of the elements And 46 ₁ -46 ₂ connected to the inputs of the element OR 47, the output of which is connected to the information output 48.

In the encoder 8 of the polynomial (see Fig. 6) for an example implementation, the input 49 _{1 of the} group of control inputs is connected to the first inputs of the elements OR 50 ₃ , 50 ₄ , the input 49 _{2 of the} group of control inputs is connected to the first inputs of the elements OR 50 ₂ , 50 ₅ and the second input of the OR element 50 ₄ , the input 49 _{3 of the} group of control inputs is connected to the first input of the OR element 50 ₁ , the second inputs of the elements OR 50 ₃ , 50 ₅ and the output 51 _{6 of the} group of control outputs, the input 49 of the ₄ group of control inputs is connected to the second inputs of the elements OR 50 _1, 50 _2, third inputs of OR elements 50 _3, 50 ₄ and 51 output ₁ c ppy control outputs, outputs of OR elements 50 ₁ -50 ₅ are connected respectively to the outputs of 51 ₂ -51 _5, 51 ₇ groups of control outputs.

In block 9 of the frequency generators (see Fig. 7), for an example of implementation, the inputs 49 ₁ -49 _{4 of the} group of control inputs are connected respectively to the second inputs of the mounting elements AND 53 ₁ -53 ₄ , the outputs of the generators 52 ₁ -52 _{4 of} harmonic oscillations are connected to the first the inputs of the mounting elements AND 53 ₁ -53 ₄ , the outputs of which are connected to the inputs of the mounting element OR 54, the output of which is connected to the control output 55.

In the tunable distributor 10 (see Fig. 8), for an example implementation, the control input 35 is connected to the installation input in the state "1" of the RS-flip-flop 57. Inputs 49 ₁ -49 ₄ groups of control inputs are connected respectively to the second inputs of the elements And 61 ₁ - 61 ₄ . The clock input 56 is connected to the synchronization input of the shift register 58. The output of the RS flip-flop 57 is connected to the information input of the shift register 58. The output of the first cell of the shift register 58 is connected to the reset input of the RS flip-flop 57 and the fourth control output 59, the output of the third cell of the shift register 58 is connected to the fifth control output 60, the outputs of the fourth and fifth cells of the shift register 58 are connected respectively to the outputs 44 ₁ , 44 ₂ groups of control outputs, outputs of the sixth and tenth cells of shift register 58 are connected respectively to the third 36 and second 37 control outputs, outputs of the 24th, 26th, 32nd and 34th cells of shift register 58 are connected respectively to the first inputs of AND elements 61 ₁ -61 ₄ . The outputs of the elements AND 61 ₁ -61 _{4 are} connected to the inputs of the element OR 62, the output of which is connected to the first control output 27 and the reset input of the shift register 58.

 In the driver 11 clock (see Fig. 9), the first 59 and second 60 control inputs are connected respectively to the inputs of the installation in the state "1" and reset the RS-trigger 63, the output of which is connected to the information output 64.

In coding block 12 (see Fig. 10), for receiving an implementation, the first control input 27 is connected to the reset inputs of the D-flip-flops 67 ₁ -67 ₉ and the RS-flip-flop 68, the second control input 37 is connected to the input of the installation in the state "1" RS -trigger 68. The first 43 and second 48 information inputs are connected respectively to the inputs of the OR element 70. Inputs 51 ₁ -51 _{7 of the} group of control inputs are connected respectively to the second inputs of the elements AND 65 ₁ -65 ₇ . The clock input 56 is connected to the synchronization inputs of the D-flip-flops 67 ₁ -67 ₉ . The output of the element And 65 _{1 is} connected to the information input of the D-trigger 67 ₁ . The outputs of the elements And 65 ₂ -65 _{7 are} connected respectively with the first inputs of the adders 66 ₁ -66 ₆ modulo two. The output of the adder 66 ₁ modulo two is connected to the information input of the D-trigger 67 ₂ . The outputs of the adders 66 ₂ -66 ₆ modulo two are connected respectively to the information inputs of the D-flip-flops 67 ₅ -67 ₉ . The output of the adder 66 ₇ modulo two is connected to the first inputs of the elements And 69 ₁ , 69 ₂ . The output of the D-flip-flop 67 _{1 is} connected to the second input of the adder 66 ₁ modulo two. The output of the D-flip-flop 67 _{2 is} connected to the information input of the D-flip-flop 67 ₃ , the output of which is connected to the information input of the D-flip-flop 67 ₄ . The outputs of the D-flip-flops 67 ₄ -67 _{9 are} connected respectively to the second inputs of the adders 66 ₂ -66 ₇ modulo two. The direct and inverse outputs of the RS flip-flop 68 are connected respectively to the second inputs of the elements AND 69 ₁ -69 ₂ , the output of the element AND 69 _{1 is} connected to the first inputs of the elements AND 65 ₁ -65 ₇ , the output of the element AND 69 _{2 is} connected to the first input of the element OR 71 The output of the OR element 70 is connected to the first input of the adder 66 ₇ modulo two and the second input of the OR element 71, the output of which is connected to the information output 72.

In block 13 of the channel state assessment (see Fig. 11), for an example implementation, the inputs 34 ₁ -34 _{3 of the} group of control inputs are connected respectively to the inverse inputs of the elements AND 74 ₁ -74 ₃ and the first inputs of the elements AND 77 _1J -77 _3J , J = 1.4, the outputs of the generators 73 ₁ -73 _{3 of the} Poisson sequence of pulses are connected respectively to the direct inputs of the elements And 74 ₁ -74 ₃ , the outputs of which are connected respectively to the synchronization inputs of the registers 75 ₁ -75 ₃ shift, the outputs of the cells of the register 75 _I , I = 1.3, the shear elements are connected to inputs OR 76 _I1 -76 _I4, I = 1,3, in accordance with probability nostnymi channel characteristics of the mathematical model, the output of the last cell of register 75 _{I, I} = 1,3, the shift is connected with its data input, i.e. the register is closed in a ring, the outputs of the elements OR 76 _I1 -76 _I4 , I = 1,3, connected to the second inputs of the elements And 77 _I1 -77 _I4 , I = 1,3. The outputs of the elements And 77 _I1 -77 _I4 , I = 1.3 are connected respectively to the inputs of the elements OR 78 ₁ -78 ₄ , the outputs of which are connected respectively to the outputs 49 ₁ -49 ₄ groups of control outputs.

 In block 14 of the coordination of the transmitting device (see Fig. 12), the control input 55 is connected to the input of the carrier signal of the modulator 80. The second 64 and first 72 information inputs are connected to the inputs of the element OR 79, the output of which is connected to the input of the modulating signal of the modulator 80, output which is connected to the input of the bandpass filter 81, the output of which is connected to the channel output 15.

 In block 17 matching receiver (see Fig. 13), the channel input 16 is connected to the input of the bandpass filter 82, the output of which is connected to the input of the demodulator 83, the output of which is connected to the information output 84.

In a frequency decoder 18 (see Fig. 14), for an example implementation, channel input 16 is connected to the inputs of bandpass filters 85 ₁ -85 ₄ , the outputs of which are connected respectively to the inputs of Schmitt triggers 86 ₁ -86 ₄ (threshold devices), the outputs of which are connected respectively with the inputs of the installation in the state "1" RS-triggers 87 ₁ -87 ₄ , the outputs of which are connected respectively with the outputs 88 ₁ -88 ₄ groups of control outputs. The control input 89 is connected to the reset inputs of the RS-flip-flops 87 ₁ -87 ₄ .

 In the selector 19 of the clock signal (see Fig. 15), the information input 84 is connected to the inputs of the single vibrator 90 and the driver of the leading edge signals, the output of the single vibrator 90 is connected to the input of the driver 91 of the signal leading edge of the pulses, the output of which is connected to the first input of the element And 93 Output a signal former 92 is connected to a second input of AND element 93, the output of which is connected to a control output 94.

 In block 20 of the clock generator (see Fig. 16), the second 89 and first 94 control inputs are connected respectively to the reset inputs and set to state “1” of the RS flip-flop 96. The output of the high-frequency pulse generator 95 is connected to the synchronization input of the binary counter 97 The inverse output of the RS flip-flop 96 is connected to the reset input of the binary counter 97, the output of which is connected to the clock output 98.

In the tunable distributor 21 of the receiving device (see Fig. 17), for an example of implementation, the inputs 88 ₁ -88 _{4 of the} group of control inputs are connected respectively to the second inputs of the elements And 102 ₁ -104 ₄ , 103 ₁ -103 ₄ , the control input 94 is connected to the input settings in state “1” of the RS flip-flop 99 ₁ . The clock input 98 is connected to the synchronization input of the shift register 101. The output of the RS-flip-flop 99 ₁ with the input of the driver 100 of the leading edge of the pulses, the output of the RS-flip-flop 99 _{2 is} connected to the information input of the shift register 101. The output of the driver 100 signals of the leading edge of the pulses is connected to the input of the installation in the state "1" of the RS-trigger 99 ₂ . The output of the first cell of the shift register 101 is connected to the reset input of the RS flip-flop 99 ₂ , the outputs of the 11th, 12th, 15th, 16th cells of the shift register 101 are connected respectively to the first inputs of the elements And 102 ₁ -102 ₄ , the outputs The 21st, 23rd, 29th and 31st cells of the shift register 101 are connected respectively to the first inputs of the AND elements 103 ₁ -103 ₄ . The outputs of AND gates 102 _{1 to} 102 ₄ are connected respectively to the outputs 104 ₁ -104 ₄ of the first group of control outputs. The outputs of the elements 103 ₁ -103 _{4 are} connected respectively to the outputs 105 ₁ -105 _{4 of the} second group of control outputs and the inputs of the OR element 106, the output of which is connected to the reset inputs of the RS flip-flop 99 ₁ and the shift register 101 and the control output 89.

In the decoding unit 23 ₂ (see FIG. 18) for an example implementation, the third control input 89 is connected to the reset inputs _{of the} shift register 109 ₂ , RS-flip-flop 110 ₂ and D-flip-flops 114 ₁₂ -114 ₅₂ , the clock input 98 is connected to the synchronization inputs register 109 ₂ shift and D-flip-flops 114 ₁₂ -114 ₅₂ , the first control input 104 _{2 is} connected to the input of the installation in the state "1" of the RS-flip-flop 110 ₂ . The second control input 105 _{2 is} connected to the sixth input of the element And 115 ₂ . Information input 107 _{2 is} connected to the second inputs of the OR element 108 ₂ and adder 113 ₁₂ modulo two. The output of the OR element 108 _{2 is} connected to the information input _{of the} shift register 109 ₂ . The outputs of the 9th, 8th, 7th and 6th cells _{of the} shift register 109 are connected respectively to the outputs 118 ₁₂ -118 _{42 of the} first group of information outputs, the output of the 10th cell _{of the} shift register 109 is connected to the output of 117 _{22 the} second groups of information outputs, the output of the 11th cell _{of the} shift register 109 ₂ is connected to the first input of the adder 112 ₂ modulo two and the output 117 _{12 of the} second group of information outputs. The output of the RS-flip-flop 110 _{2 is} connected to the first input of the AND 111 ₂ element, the output of which is connected to the second input of the adder 112 ₂ modulo two, the output of which is connected to the first input of the OR element 108 ₂ . The outputs of the adders 113 ₁₂ -113 ₅₂ modulo two are connected respectively to the information inputs of the D-flip-flops 114 ₁₂ -114 ₅₂ , the inverse outputs of which are connected respectively with the first-fifth inputs of the element And 115 ₂ , as well as the first and second direct and third-fifth inverse the inputs of And 116 ₂ , the direct output of the D-flip-flops 114 ₁₂ -114 _{42 are} connected modulo two to the first inputs of the adders 113 ₂₂ -113 ₅₂ , the direct output of the D-flip-flop 114 _{52 is} connected to the first input of the adder 113 ₁₂ modulo two and second the inputs of the adders 113 ₃₂ , 113 ₅₂ modulo two. The output of the element And 115 _{2 is} connected to the control output 119 ₂ . The output of the element And 116 ₂ connected to the second inputs of the element And 111 ₂ , adders 113 ₂₂ , 113 ₄₂ modulo two and the third input of the adder 113 ₃₂ modulo two.

In the address decoder 24 (see FIG. 19), for an example implementation, the information inputs 117 ₁₁ -117 _{14 are} connected to the inputs of the OR element 120 ₁ , the information inputs 117 ₂₁ -117 _{24 are} connected to the inputs of the OR element 120 ₂ . The inputs 119 ₁ -119 ₄ groups of control inputs are connected to the inputs of the element OR 121. The outputs of the elements OR 120 ₁ , 120 _{2 are} connected to the inputs of the decoder 122 of the binary code. The output of the OR element 121 is connected to the input information permission input (V-input) of the binary code decoder 122, the outputs of which are connected to the outputs 123 ₁ - 123 _{3 of the} group of control outputs.

In block 25 of the data output (see Fig. 20) for an example of implementation, the information inputs 118 _L1 -118 _L4 , L = 1,4, are connected to the inputs of the OR element 124 _L , L = 1,4, inputs 123 ₁ -123 ₃ groups control inputs are connected respectively to the synchronization inputs of the registers 125 ₁ -125 ₃ memory. The output of the OR element 124 _{L is} connected to Ls, L = 1.4, the information inputs of the registers 125 ₁ -125 ₃ memory, the outputs of the register 125 _I , I = 1,3, the memory is connected to the outputs 26 _I1 -26 _I4 I I = 1.3, groups of information outputs.

 The system for transmitting and receiving information with variable-length codes works as follows.

First, consider a generalized algorithm. In the initial state, the clock pulse generator 7 is on the transmitting side, and the high frequency pulse generator 95 (see Fig. 16) in the clock pulse generator unit 20 is on the receiving side. When the I-th, I = 1, B, message information source appears on the corresponding input 1 of the _I group of control inputs of the start-up unit 4, a transmission request signal from the I-th source appears. This signal is stored in the start-up block 4, which implements the relative priority of the service in increasing numbers. According to the indicated type of priority, if messages from other sources occurred during the transmission of a message, they wait for the transmission of this message to end, and then the transmission of the source message with the lowest number begins. Suppose that at the time of the occurrence of a message at the I-th source, the system is not busy sending messages to another source, then at the I-th output of the control output group of the start-up unit 4, a signal for processing the message of the I-th source appears.

 Under the action of the specified signal in the address generator 6, a parallel code of the address of the I-th source is generated, and in block 13 of the channel state estimation, the number J, J = 1, H, of the correction code used at the moment in time to transmit the message of the I-th source is determined. The signal carrying information about the code number is fed to the Jth output of the group of control outputs of the channel state estimation unit 13.

 Under the action of the specified signal in the block 9 of the frequency generators, a carrier oscillation is selected with the frequency corresponding to this code, which is fed to the control input of the matching unit 14. In addition, the polynomial encoder 11, in accordance with the incoming control signal, provides signals to the group of control inputs of the encoding unit 12 that carry information about the generating polynomial of the selected code. Also, the signal from the Jth output of the group of control outputs of the channel status estimator 13 sets in the tunable distributor 10 the number of clock cycles for transmitting and processing (decoding) the message using the Jth code.

 On the leading edge of the message processing permission signal, at the control output of the start-up unit 4, the trigger signal of the tunable distributor 10 is formed, which starts switching under the action of clock pulses generated by the clock pulse generator 7. The signals from the 4th and 5th control outputs of the tunable distributor 10, generated at the 1st and (U + 1) -th clocks, are used to form a clock signal, which is fed to the second information input of the matching unit 14 after conversion (modulation and filtering) through channel output 15 to the communication channel.

 The signals from the group of control outputs of the tunable distributor 10, generated on clock cycles from the (U + 2) th to the (U + 1 + V) th, are used in the address generator 6 to convert the parallel address code to a serial code fed to the second information input block 12 coding.

At the (U + 2 + V) -th cycle, the tunable distributor 10 outputs a signal to enable reception of information bits of the source message to the 3rd control output. Under the action of said signal (in conjunction with the signal processing permission message I-th power supplied from puskonakachivayuschego unit 4) at the output _I 3 groups of control switch 5 outputs a signal appears transmission permission information I-th source. As a result, during the W cycles (from the (U + 2 + V) -th to (U + 1 + M) -th) information bits of the message in the serial code are fed to the input 2 _{I of the} group of information inputs of the switch 5, and from the information output of the switch 5 - to the first information input of coding unit 12.

The encoding procedure is implemented in accordance with the ratio
A (X) = C (X) • X ^K + R (X),
Where
A (X) is the code polynomial of the cyclic code;
C (X) is a polynomial of information symbols, which include address code symbols and source messages;
K is the degree of the generating polynomial G (X), equal to the number of control characters of the code;
R (X) is a polynomial of control characters equal to the remainder of the division of the polynomial C (X) • X ^K by the polynomial G (X).

 During M clock periods (from (U + 2) th to (U + 1 + M) th) in the coding block 12, control symbols are calculated; at the same time, the information symbols entering the coding block 12 from the second and first information inputs are issued through the information output of the coding block 12 to the first information input of the conversion block 14 and, after conversion (modulation and filtering), is transmitted after the clock signal through the channel output 15 to the communication channel.

At the (U + 2 + M) -th cycle, the tunable distributor 10 generates a control discharge signal to the second control output. Under the action of the specified signal, the output signal of permission to transmit information from the I-th source is removed from the output 3 of the _I group of control outputs of the switch 5, and the inputs 2 ₁ -2 _{B of the} group of information inputs of the switch 5 are disconnected from its information input. During K _J cycles (from the (U + 2 + M) -th to (U + 1 + M) -th) control characters, following the information, arrive at the first information input of the matching unit 14 and after conversion (modulation and filtering) through the channel output 15 to the communication channel.

At the (U + 2 + 2N _J ) -th cycle, the tunable distributor 10 provides a reset signal to the first control output. Under the action of this signal, the elements with memory of the coding unit 12 and the tunable distributor 10, as well as the RS-triggers 28 _I , 30 _I (see Fig. 3) of the start-up unit 4 are set to the state 0. At the same time, from the I-th output of the group the control outputs of the start-up unit 4, the signal for authorizing the processing of the message from the I-th source is removed and from the J-th output of the group of control outputs of the channel state evaluation unit 13 is a signal that determines the number of the code used for transmitting.

On the receiving side of the system, the signal from the channel input 16 enters the matching unit 17, where it is filtered and demodulated, and the frequency decoder unit 18, where the code number J used for transmission is determined. As a result, at the Jth output of the group of control outputs of the frequency decoder 18, a signal appears that carries information about the code number. The specified signal is supplied to the second input of the element And 22 _J , allowing the reception and decoding of the code combination received at the first inputs of the elements And 22 ₁ -22 _H from the information output of the matching unit 17, the decoding unit 23 _J.

On the trailing edge of the clock, the clock selector 19 generates a start signal for the clock generator unit 20 and the tunable distributor 21. Under the action of the clock pulses, the tunable distributor 21 starts and the decoding unit 23 _J starts working. Thus, the 1st cycle of the tunable distributor 21 of the receiving device corresponds to the (U + 2) -th cycle of the tunable distributor 10 of the transmitting device.

During the first N _J cycles in the decoding unit 23 _J , the received combination is recorded in the buffer register and the syndrome is calculated (the remainder of the division of the received polynomial into the generating polynomial). Starting from the (N _J +1) th clock, according to the signal output from the tunable distributor 21 to the first control input of the decoding unit 23 _J , the error correction is performed in the last for N _J clock cycles.

At the (2N _J +1) th step, the tunable distributor 21 provides a signal for completing the error correction step to the second control input of the decoding unit 23 _J. If the adopted combination does not contain errors or contains correctable or undetectable errors, then under the action of the indicated signal, the decoding unit 23 _J gives the address decoder 24 an enable signal for decoding the address code of the source of information coming to the address decoder 24 from the second group of information outputs of the decoding unit 23 _J. Otherwise (the received combination contains detectable but uncorrectable errors), the decoding unit 23 _J does not give the decoding enable signal to the decoder 24.

upon receipt of the decoding enable signal, the address decoder 24 in turn issues to the 1st input of the group of control inputs of the data output unit 25 a signal for issuing to the 1st recipient information of the message bits coming from the first group of information outputs of the decoding unit 23 _J.

At the (2N _J +1) -th clock cycle with a small delay in time, the control output of the tunable distributor 21 gives a reset signal to the control input of the frequency decoder 18, the second control input of the clock generator unit 20 and the third control input of the decoding unit 23 _J , in which (as well as in tunable distributor 21) the elements with memory are set to state "0". This stops the generation of clock pulses by the block 20 of the clock generator, and also removes the signal from the Jth output of the group of control outputs of the frequency decoder 18, which determines the number used for transmitting the code.

As an example of confirming the operability of the device, we consider the implementation of blocks 8, 12, 13, 23 ₂ and the operation of the device when the number of message sources is B = 3 (whence the number of bits of the address code V = 2); the number of bits of the message W = 4; used H = 4 cyclically or truncated cyclic codes with generating polynomials G ₁ (X) = X ⁴ + X + 1, G ₂ (X) = X ⁵ + X ⁴ + X ² +1, G ₃ (X) = X ⁸ + X ⁷ + X ⁶ X ⁴ +1, G ₄ (X) = X ⁹ + X ⁶ + X ⁵ X ⁴ + X + 1; the elongation factor of the clock U = 2.

Из матрицы следует, что выходные сигналы Y_L шифратора 8 полинома определяются через его входные сигналы X_J следующим образом:
Y₁=X₄; Y₂=X₃VX₄; Y₄=0; Y₅=X₂VX₄; Y₆=X₁VX₃VX₄; Y₇=X₁VX₂VX₄; Y₈= X₃; Y₉=X₂VX₃.We represent the generators of the polynomials G _J (X), J = 1,4, in normalized form, while the senior term of the polynomial has degree K = 9, and K ₄ -K _J = 9-K _{J of the} lower terms are zero: G ₁ (X ) • X ⁵ = X ⁹ + X ⁶ + X ⁵ , G ₂ (X) • X ⁴ = X ⁹ + X ⁸ + X ⁶ + X ⁴ , G ₃ (X) • X = X ⁹ + X ⁸ + X ⁷ + X ⁵ + X, G ₄ (X) = X ⁹ + X ⁶ + X ⁵ + X ⁴ + X + 1,
Based on the values of the coefficients of the polynomials in normalized form, we compose a matrix for the synthesis of the encoder 8 of the polynomial, in which the rows correspond to the input signals X _J , J = 1,4, and the columns correspond to the output signals Y _L , L = 1,9, the encoder

From the matrix it follows that the output signals Y _{L of the} encoder 8 of the polynomial are determined through its input signals X _J as follows:
Y ₁ = X ₄ ; Y ₂ = X ₃ VX ₄ ; Y ₄ = 0; Y ₅ = X ₂ VX ₄ ; Y ₆ = X ₁ VX ₃ VX ₄ ; Y ₇ = X ₁ VX ₂ VX ₄ ; Y ₈ = X ₃ ; Y ₉ = X ₂ VX ₃ .

In the encoder 8 of the polynomial (see Fig. 6), the logic of the connections of the inputs 49 with the inputs of the elements OR 50 and outputs 51 corresponds to the logical functions Y ₁ , Y ₂ and Y ₅ -Y ₉ .

 The signals coming from the encoder 8 of the polynomial to the inputs 51 of the coding block 12 (Fig. 10) provide, using the And 65 elements, a division scheme into the generating polynomial of the code used to transmit the code (the code whose number corresponds to the output number 49 of the channel state estimation block 13, by which signal will appear).

 The basis of the implementation of the block 13 assessment of the channel conditions (Fig. 11) is the following mathematical model.

When examining a real channel for each homogeneous message flow characterized by specified requirements for fidelity of transmission, H states are distinguished, characterized, for example, by a different level of interference in the channel. Then for each 1st, I = 1, B, source of homogeneous messages, the mathematical model of the channel is written in the form of a row matrix
P ^(I) = | P $\genfrac{}{}{0ex}{}{\text{I}}{\text{1}}$ , P $\genfrac{}{}{0ex}{}{\text{I}}{\text{2}}$ , ..., P $\genfrac{}{}{0ex}{}{\text{I}}{\text{H}}$ |,
Where
P $\genfrac{}{}{0ex}{}{\text{I}}{\text{J}}$ - - the probability of transmitting the message of the 1st source to the Jth, J = 1, H, code (code with the Jth correcting ability).

The elements of the stochastic matrices P ^{(I) are} normalized; therefore, the choice of channel states will correspond to the random event scheme.

 Due to the fact that the automaton models for each 1st source are homomorphic, the circuitry of the channel state estimation unit 13 consists of B identical nodes implemented on generators 73 of a Poisson pulse stream, AND elements 74, cyclically closed shift registers 75, groups of OR elements 76 and groups of elements AND 77.

В этом случае для реализации вероятностного (1-f)-полюсника выбираем f= 10. Тогда к элементу ИЛИ 76₁₁ следует подключить выходы первой и второй ячеек регистра 75₁, к элементу ИЛИ 76₁₂ - выходы третьей и четвертой ячеек регистра 75₁, к элементу ИЛИ 76₁₃ - выходы пятой и шестой ячеек регистра 75₁, к элементу ИЛИ 76₁₄ - выходы седьмой, восьмой, девятой и десятой ячеек регистра 75₁ и т.д.An equiprobable (1-f) -pole, where f is the number of cells (bits) of the register 75, is implemented on the And 74 element, the register 75 and the generator 73. The outputs of the cells of the register 75 _I , I = 1, B, shift are connected to the inputs of the group of elements OR 76 _IJ , J = 1, H, in accordance with the probabilities P $\genfrac{}{}{0ex}{}{\text{I}}{\text{J}}$ .
For the example implementation of FIG. 11 it is accepted that the matrix P has the form:

In this case, for the implementation of a probability (1-f) -polyusnika choose f = 10. Then the element 76 or ₁₁ to be connected first and second outputs of register cells 75 _1, the element 76 or ₁₂ - the third and fourth outputs of register cells 75 _1, to the element OR 76 ₁₃ - the outputs of the fifth and sixth cells of the register 75 ₁ , to the element OR 76 ₁₄ - the outputs of the seventh, eighth, ninth and tenth cells of the register 75 ₁ , etc.

 The frequencies of the generators 73 of the Poisson pulse stream are an order of magnitude or more higher than the sampling frequency of the inputs 34. One of the bits (randomly selected) of the registers 75 is pre-recorded (not shown in Fig. 11 to simplify the circuit of the preliminary recording circuit in the registers 75). The generators 73 supply pulses through the AND elements 74 to the clock inputs of the registers 75 and a unit in each of the registers between the moments of the polling repeatedly “circulates” the memory cells.

At the time of the survey on the input element 34 ₁ and 74 ₁ is closed and one of the outputs of register 75 ₁ kvaziravnoveroyatno fixed potential, which via respective OR elements 76, AND gate 77, OR gate 78 is supplied to one of the outputs of the block 49. Thus, the outputs 49 ₁ -49 ₄ provide the appearance of signals during the polling time at input 34 ₁ with probabilities P $\genfrac{}{}{0ex}{}{\text{I}}{\text{1}}$ -P $\genfrac{}{}{0ex}{}{\text{I}}{}$$\genfrac{}{}{0ex}{}{}{\text{4}}$ respectively.

The decoding unit 23 ₂ (Fig. 18) performs decoding according to the syndrome (sequential mode) of the code with the parameters:
N ₂ = 11, D ₂ = 4, G ₂ (X) = X ⁵ + X ⁴ + X ² +1.

 In this case, one-time errors are corrected and two-time errors and part of the errors of higher multiplicity are detected.

The scheme of the syndrome calculator, which is a division scheme by a polynomial, is implemented on D-flip-flops 114 and adders 113 modulo two. Nonzero coefficients of the generating polynomial G ₂ (X) = X ⁵ + X ⁴ + X ² +1 determine the presence of adders 113 ₅₂ , 113 ₃₂ , 113 ₁₂ modulo two, connected to the feedback circuit wound from the output of the D-trigger 114 ₅₂ .

When correcting single errors, many selectable syndromes consist of one syndrome S ^* (X), defined as the remainder of the division of X ^N-1 by G (X). In this case, S ^* (X) = X ² + X + 1. The selector of syndromes of correctable errors is implemented on the element And 116 ₂ . In accordance with the coefficients S ^* (X), the inverse outputs of the D-flip-flops 114 of the syndrome calculator are connected to the direct and inverse inputs of the AND element 116 ₂ .

The polynomial T (X), which sets the feedback for zeroing the D-flip-flops of the syndrome calculator after fixing the error, is defined as the remainder of dividing X ^N by G (X). In this case, T (X) = X ³ + X ² + X. Nonzero coefficients T (X) determine the presence of the adder 113 ₄₂ , 113 ₃₂ , 113 ₂₂ modulo two, connected to the feedback circuit wound up from the output of the syndrome selector.

The selector of the zero syndrome implemented on the AND 115 ₂ element is interrogated at the (2N + 1) -th cycle (in this case, at the 23rd) of the operation of the receiving device. If the syndrome is zero, then the output signal 119 ₂ receives address resolution code decoding; if the syndrome is non-zero, then the decoding enable signal of the address code is not output to output 119 ₂ .

Suppose that at some moment in time, the 1st source has a message 1010. At the same time, at the input 1 _{1 of the} start-up block 4 (Fig. 3), a transmission request signal from the 1st source appears, stored in trigger 28 ₁ . Assume that the system is not currently busy sending messages from other sources. Then the triggers 28 ₂ , 28 ₃ , 30 ₂ , 30 _{3 of the} start-up block 4 are in the zero state, as a result of which the element And 29 ₁ , the trigger 30 _{1 are} triggered, and the output signal 1 of the message of the 1st source appears at the output 34 _{1 of the} start-up block 4.

Under the action of the specified signal in the address shaper 6 (Fig. 5) using the binary code encoder 45, a parallel code 01 of the address of the 1st source is formed, and in the block 13 of the channel state estimation (Fig. 11) the And 74 ₁ element is closed and on one of the outputs of the register 75 ₁ shift fixed signal "1". Let this signal be fixed at the 3rd output of register 75 ₁ . This means that to transmit a message from the 1st source at the given moment, the 2nd code will be used - a code with parameters N ₂ = 11, D ₂ = 4 and the generatrix polynomial G ₂ (X) = X ⁵ + X ⁴ + X ² +1. The signal determining the code number is received from the 3rd output _{of the} shift register 75 ₁ through the elements OR 76 ₁₂ , AND 77 ₁₂ , OR 78 ₂ to the output 49 ₂ of the channel state estimation unit 13.

Under the action of the specified signal in the block 9 of the frequency generators (Fig. 7), the carrier frequency generator 52 ₂ corresponding to the 2nd code is selected and the harmonic oscillation with the corresponding frequency is fed to the input 55 of the block 14 matching the transmitting device of the system. In addition, at the outputs 51 ₁ -51 _{7 of the} encoder 8 of the polynomial (Fig. 6), a set of signals 0010101 is formed, which is used for switching the feedback circuit in the division circuit of the encoding unit 12. Also, the signal about the code number prepares the element And 61 ₂ tunable distributor 10 (Fig. 8), thereby determining the number of clock cycles (25 cycles) of the transmitting device.

 A signal is generated at the leading edge of the message processing permission signal of the 1st source at the output 35 of the start-up unit 4, which sets the trigger 57 of the tunable distributor 10 into a single state (Fig. 8), and one is written at the leading edge of the next clock pulse to the first cell of the shift register 58 . The signal from the output of the first cell sets the trigger 57 to zero, thereby ensuring that the shift register performs the distributor function (the appearance of the signal "1" at only one of the distributor outputs at any time). Clock pulses, ensuring the advancement of the unit in the register, are fed to the input 56 of the tunable distributor 10 from the generator 7 clock pulses.

 The signals from the outputs 59 and 60 of the tunable distributor 10, generated at the 1st and 3rd clocks, respectively, are used in the clock driver 11 (Fig. 9) to generate a pulse using a trigger 63, the duration of which is twice the duration of the elementary signal. The specified clock signal is fed to input 64 of the matching unit 14 (Fig. 12) and after the transformations performed by the modulator 80 and the bandpass filter 81, through the channel output 15 into the communication channel.

The signals from the outputs 44 ₁ , 44 _{2 of the} tunable distributor 10, generated at the 4th and 5th clocks, respectively, are used in the address shaper 6 (Fig. 5) for conversion using AND 46 ₁ , 46 ₂ elements and OR 47 parallel element code 01 of the address of the 1st source in the serial code received at the input 48 of the block 12 encoding.

At the 6th step, the tunable distributor 10 outputs to the output 36 a permission signal for receiving information bits of the source message, which sets the trigger 38 of switch 5 to a single state (Fig. 4). The signal from the direct output of the trigger 38, together with the permission signal for processing the message of the 1st source at the input 34 ₁ using the AND 40 ₁ element at the output 3 _{1 of the} switch 5, forms a signal for the permission to transmit information from the 1st source. As a result, over 4 clock cycles (from the 6th to the 9th), information bits 1010 of the message in a serial code are received at input 2 _{1 of} switch 5 and through elements AND 39 ₁ , OR 41, AND 42 to input 43 of encoding unit 12 .

Within 6 cycles (from the 4th to the 9th), information symbols 011010 are received, which enter the encoding block 12 (Fig. 10) from inputs 48 and 43, through OR elements 70, 71 to output 72; at the same time, in the coding block 12, control characters 10000 of the code combination are calculated, and the division scheme by the generatrix polynomial G ₂ (X) = X ⁵ + X ⁴ + X ² + 1 is implemented on triggers 67 ₅ -67 ₉ and adders 66 ₂ , 66 ₄ and 66 ₆ modulo two.

At the 10th step, the tunable distributor 10 outputs to the output 37 a signal for issuing control bits. The specified signal sets the trigger 38 of switch 5 to the zero state, as a result of which the information transmission enable signal from the 1st source is removed from the output 3 of the ₁ switch, after which the 1st source removes the transmission request signal from input 1 _{of the} start-up unit 4, and inputs 2 ₁ -2 _{3 of the} switch 5 are disconnected from its output 43. The signal for the issuance of control bits also switches the control key in the coding unit 12 (Fig. 10), assembled on the trigger 68 and the elements And 69 ₁ , 69 ₂ , and for 5 cycles (s 10th to 14th) 10000 control characters come from t riggers 67 ₅ -67 ₉ through the adder 66 ₇ , the elements AND 69 ₂ , OR 71 after the information output 72 of the block 12 encoding.

 Symbols 01101010000 of the code combination (information and control) from the output 72 of the coding unit 12 are sent to the matching unit 14 (Fig. 12) and after the transformations performed by the modulator 80 and the bandpass filter 81, through the channel output 15 - into the communication channel.

At the 25th step (on the leading edge), the tunable distributor 10 issues a reset signal through the AND 61 ₂ , OR 62 elements to the output 27. Under the influence of the indicated signal, the triggers 67 ₁ -67 ₉ , 68 of the coding unit 12, the shift register 58 of the tunable distributor 10, as well as the triggers 28 ₁ and 30 _{1 of the} starting unit 4 are set to zero (Fig. 3). At the same time, the signal processing permission signal from the first source is removed from the output 34 _{1 of the} start-up block, after which the signal determining the number of the code used for transmitting is removed from the output 49 ₂ of the channel state estimation block 13. The transmitter of the system is ready to receive messages from the I-th, I = 1, B, source, its encoding and transmission over the communication channel.

In the receiver of the system, the signal from the channel input 16 enters the matching unit 17 (Fig. 13), where it is filtered and demodulated, and to the frequency decoder unit 18 (Fig. 14), where using a band-pass filter 85 ₂ and Schmitt trigger 86 ₂ determines the frequency range in which the transmission is conducted. The range number in turn determines the number of the code used for transmission. A signal carrying information about the code number is generated using the RS-trigger 87 ₂ and goes to the output 88 _{2 of the} frequency decoder. The specified signal prepares the elements And 102 ₂ , 103 ₂ tunable distributor 21 (Fig. 17), thereby determining the cycle of the beginning of the error correction phase (12th cycle) and the number of cycles of operation (22 cycles) of the receiving device. In addition, the signal about the code number prepares the element And 22 ₂ , allowing the decoding unit 23 _{2 to} receive the code combination coming from the output 84 of the matching block 17.

The one-shot 90 of the selector 19 of the clock signal (Fig. 15) generates a pulse whose duration is equal to the duration of the clock signal, therefore, a trigger signal appears at the output of the selector 94 at the trailing edge of the clock signal. The indicated signal sets the RS-flip-flop 96 of the block 20 of the clock pulse generator into a single state (Fig. 16), thereby allowing the operation of the binary counter 97 of the subtracting type, which performs the function of a frequency divider. The length of the counter determines the value of the maximum phase mismatch of the clock pulses of the transmitting and receiving devices of the system. So, for the one shown in FIG. 16 of a four-digit counter, the maximum mismatch will be 6%, while the frequency of the pulses generated by the generator 95 should be 16 times the frequency of the clock pulses, i.e. f _HF = 16f _TI . In addition, under the action of the start signal in the tunable distributor 21 (Fig. 17) using a chain of elements consisting of an RS-trigger 99 ₁ , a shaper 100 of the leading edge signals and RS-trigger 99 ₂ , the unit is written to the shift register 101 by the clock pulse corresponding to the 4th clock pulse in the transmitting device. Thus, the 1st cycle of the tunable distributor 21 of the receiving device corresponds to the 4th cycle of the tunable distributor 10 of the transmitting device.

During the first 11 clock cycles of the tunable distributor 21, the received combination is recorded in the buffer register 109 _{2 of the} shift of the decoding unit 23 ₂ (Fig. 18) and the syndrome is calculated in the division scheme by the generator polynomial G ₂ (X) = X ⁵ + X ⁴ + X ² + 1, implemented on D-flip-flops 114 ₁₂ -114 ₅₂ and adders 113 ₁₂ -113 ₅₂ modulo two. Let distortions occur during transmission over the communication channel, as a result of which the code combination at the output of the matching unit 17 has the form 01101110000, i.e. contains a single error. Then the syndrome of the accepted combination is 10101.

At the 12th step, the tunable distributor 21 outputs to the output 104 _{2 a} signal at the beginning of the error correction stage, which sets the RS-trigger 110 _{2 of the} decoding unit 23 ₂ to a single state. As a result, the output of the selector of syndromes of correctable errors implemented on the element And 116 ₂ is connected to the second input of the adder 112 ₂ , in which, on the 17th clock cycle of the tunable distributor 21, the error is corrected. On the 18th step, the triggers 114 of the syndrome calculator are set to zero state by the feedback signal from the output of the And 116 ₂ element.

At the 23rd step, the tunable distributor 21 outputs 105 _{2 a} signal to complete the error correction step, interrogating the zero syndrome selector implemented on the And 115 ₂ element. As a result, at the output 119 _{2 of the} decoding unit 23 ₂ , a signal is generated allowing the operation of the binary code decoder 122 included in the address decoder 124 (Fig. 19). The information inputs 117 ₁₂ and 117 _{22 of the} address decoder 24 receive a parallel code 01 of the address of the first source from the corresponding outputs of the decoding unit 23 ₂ .

In turn, at the output 123 _{1 of the} address decoder 24, a write signal is generated in the register 125 ₁ of the data output unit 25 (Fig. 20) of the message bits 1010 received in parallel code to the inputs 118 ₁₂ -118 ₄₂ from the corresponding outputs of the decoding unit 23 ₂ . As a result, the message from the outputs 26 ₁₁ -26 ₁₄ of the data output unit 25 is sent to the 1st information recipient.

On the 23rd cycle with a small delay in time, the tunable distributor 21 outputs a reset signal to the output 89. The specified signal sets the trigger 96 to zero in block 20 of the clock generator (Fig. 16). The signal from the inverse output of the trigger 96 prohibits the operation of the binary counter 97, as a result of which the issuance of clock pulses to the circuit of the receiving device of the system stops. The reset signal also sets to zero the trigger 87 ₂ in the frequency decoder 18, the shift register 109 ₂ , and the trigger 110 ₂ in the decoding unit 23 ₂ , and the trigger 99 ₁ , and the shift register 101 in the tunable distributor 21. The receiver of the system is ready to receive messages from the communication channel, its decoding and delivery to the 1st recipient.

 The timing diagram of the system for this example is shown in FIG. 21.

 The technical and economic efficiency of the proposed system for transmitting and receiving information with a variable-length code in relation to a known system (see ed. Certificate of the USSR N 1109927, M. cl. H 04 L 5/22, published in officer. Bull. BI N 31 from 08.23.84) it is possible to estimate from a decrease in the utilization rate of the communication channel.

 The utilization coefficient R of the communication channel determines the fraction of the time during which the channel is busy transmitting messages. Obviously, for the known system R = 1.

где
A_I - интенсивность потока сообщений I-го источника (сооб./ед. врем);
T_I - время передачи сообщения I-го источника (ед. врем/сооб.).For the proposed system

Where
A _I - the intensity of the message flow of the I-th source (co. / Unit time);
T _I - the transmission time of the message of the I-th source (unit time / message).

Экономическая эффективность Э за время T при известной стоимости C использования канала в единицу времени составит

$For many information transfer systems (e.g. telemechanics systems)

Economic efficiency E for time T at a known cost C of channel use per unit time will be

$

Claims (1)

 A system for transmitting and receiving information with a variable-length code, comprising on the transmitting side a switch, a channel status estimator, a coding unit, a tunable distributor, a clock generator, a polynomial encoder, a frequency generator unit, a matching unit, while the group of information inputs of the switch is a group of information system inputs, the information output of the switch is connected to the first information input of the coding unit, the output of the clock generator is connected to the clock inputs tunable distributor and coding block, the group of control outputs of the channel state estimation block is connected to the groups of control inputs of the frequency generator block, tunable distributor and polynomial encoder, the group of control outputs of which is connected to the group of control inputs of the coding block, the first control output of the tunable distributor is connected to the first control input coding unit, the second control output - with the second control input of the coding unit, information output is connected to the first information input of the matching unit, the control output of the frequency generator unit is connected to the control input of the matching unit, the channel output of which is connected to the input of the communication channel, and on the receiving side, the matching unit, frequency decoder, I elements, data output unit, tunable distributor decoding blocks, while the output of the communication channel is connected to the channel inputs of the frequency decoder and the matching unit, the information output of which is connected to the first inputs of the AND elements, group the control outputs of the frequency decoder are connected to the group of control inputs of the tunable distributor and the second inputs of the I elements, the outputs of which are connected to the information inputs of the decoder blocks, the outputs of the first group of control outputs of the tunable distributor are connected respectively to the first control inputs of the decoder blocks, the outputs of the second group of control outputs, respectively, the second control inputs of the decoding blocks, the control output of the tunable distributor with a control input of a frequency decoder and third control inputs of decoding blocks, the first groups of information outputs of which are connected to the corresponding groups of information inputs of a data output unit, the groups of information outputs of which are groups of information outputs of the system, characterized in that a start-up block is introduced into it additionally on the transmitting side , an address former and a clock driver, wherein the group of control inputs of the start-up block is a control group the system inputs, and the group of control outputs of the switch by the group of control outputs of the system, the group of control outputs of the start-up unit is connected to the groups of control inputs of the channel status estimator, the switch, and the first group of control inputs of the address generator, the information output of which is connected to the second information input of the coding unit, the first and second control inputs of the switch are connected respectively to the third and second control outputs of the tunable distributor, control The main output and input of the start-up block are connected respectively to the control inputs and the first output of the tunable distributor, the group of control outputs of which is connected to the second group of control inputs of the address shaper, the fourth and fifth control outputs of the tunable distributor are connected to the first and second control inputs of the clock generator, information output which is connected to the second information input of the matching unit, and on the receiving side is a si selector signal, clock generator block, address decoder, while the information input of the clock selector is connected to the information output of the matching unit, the control output of the clock selector is connected to the control input of the tunable distributor and the first control input of the clock generator block, the second control input of which is connected to the control output tunable distributor, the output of the clock generator unit is connected to the clock inputs of the tunable clock predelitelya and decoding units, the second group of information outputs of decoding units connected to respective groups of information inputs of the address decoder, the control outputs of the decoding units are connected to corresponding inputs of the group of control inputs of the address decoder, a group of control outputs of which is connected with the group of control inputs data output unit.

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