RU2071635C1 - Digital regulator for multimotored electric drive - Google Patents

Abstract

FIELD: automated control systems with digital control over multimotor electric drives of paper-making machines. SUBSTANCE: each control channel for multimotor electric drive includes second microcomputer, unit of analog regulators, two storages, relay and logic signal input/output unit, two units for successive input/output of controlling information of data wire, of control, of addresses of external devices and wires of input communication channels of second microcomputer are connected to corresponding wires of second unit for input/output of controlling information, units of input/output of relay and logical signals. Second wires of data, control and address of second microcomputer are connected to proper wires of first and second storages. EFFECT: enhanced reliability of control over system of multimotor electric drive, possibility to build various systems of multimotor electric drives. 7 cl, 13 dwg

Description

 The invention relates to the field of automated control systems and can be used to control multi-motor electric drives of paper machines.

A digital controller for a multi-motor electric drive is known, comprising a first trigger, an OR element, a first pulse shaper connected by an input to the output of a speed controller, and by output through a series-connected first speed controller and a first counter with inputs of the first element AND a pulse generator connected by output through the first key to to the control input of the first counter, through the frequency divider to the control input of the reverse counter and to the input of the second counter, and through the first connected in series th switch, register, memory block and a reversible counter to the first inputs of the second and third triggers connected by the outputs to the first and second inputs of the switch connected by the outputs to the corresponding inputs of the asynchronous motor, the second switch, the fourth trigger, additionally installed the third and fourth pulse shapers, the second and a third key, a third AND element, a direction adjuster and serially connected a second speed adjuster, a third counter and a fourth And element [1]
The disadvantages are the inability to organize a local area network for a multi-motor drive; organization of drive control requires the installation of additional equipment, which greatly complicates the device; the inability to rebuild the system to the variety of requirements of electric drives.

Closest to the proposed digital control system for a multi-motor drive in technical essence is a digital control system containing n control channels by the number of electric motors, each of which contains a first microcomputer, a random access memory (RAM) unit, a first control information input / output unit with inputs for inputting a signal from a speed sensor, an input / output unit for analog signals, an input / output unit for relay and logic signals with inputs and outputs for input and output and control signals from external devices, the first inputs / outputs of the data of the first microcomputer being connected via the first bus of the same name, respectively, with the inputs / outputs of the sequential input / output block of control information and the input / output block of analog signals, the first outputs of the address and control of the first microcomputer through the first of the same name the buses are connected to the inputs of the input / output unit of analog signals, the second inputs / outputs of the data, the control outputs and addresses of the first microcomputer through the second buses of the same name are connected respectively but with the first inputs / outputs and the inputs of the RAM block, the first control channel comprises a nonvolatile memory unit, the first data and outputs the first address and control inputs of which are connected to the second buses of the same name of the first microcomputer [2]
The disadvantages are the exchange with other digital controllers of a multi-motor electric drive via a parallel MULTIBUS bus, which requires special communication cables; the use of a parallel MULTIBUS bus limits the bus length (maximum 30 m) when communicating with other multi-motor drive controllers; the modes of speed control and electric drive control are not divided, which complicates the functioning algorithm and reduces performance.

 The aim of the invention is to increase the reliability and unification of the digital control system for a multi-motor drive by decentralizing the control and regulation functions, improve control performance, simplify algorithms and write programs, use standard control algorithms and hardware for a multi-drive electric drive for the entire variety of sectional drives, better algorithm processing management, organization of non-volatile memory in a digital control system laziness, a significant reduction in ties, improving the manageability of the system.

 This goal is achieved by the fact that in a digital controller for a multi-motor drive containing n control channels for the number of electric motors, each of which contains a first microcomputer, a random access memory (RAM) unit, a first block of sequential input / output of control information with inputs for inputting a signal from speed sensor, input / output block of analog signals, input / output block of relay and logic signals with inputs and outputs for input and output of control signals from external devices c, the first inputs / outputs of the data of the first microcomputer connected via the first bus of the same name to the inputs / outputs of the serial input / output block of control information and the input / output block of analog signals, the first outputs of the address and control of the first microcomputer through the first bus of the same name are connected to the inputs of the block input / output of analog signals, second inputs / outputs of data, control outputs and addresses of the first microcomputer through the second bus of the same name connected respectively to the first inputs / outputs and inputs of the unit As for RAM, the first control channel contains a non-volatile memory block, the first data outputs and the first control inputs and addresses of which are connected to the second buses of the same name on the first microcomputer, the second microcomputer, the second block of serial input / output of control information, the first inputs and outputs are inserted into each control channel which is designed to connect to the communication line of the local computer network, a block of analog controllers with first inputs for inputting current and speed feedbacks and outputs for outputting signals electric drive control, with the first data inputs / outputs and control outputs and addresses of the second microcomputer via the bus of the same name respectively connected to the inputs / outputs and inputs of the relay and logic signal input / output block, data inputs / outputs and control inputs of the second control serial input / output block information is connected to the first bus of the same name with the second microcomputer, and the second inputs and outputs are used to organize communication channels with the second microcomputer, the second data inputs / outputs and control and address outputs and the second microcomputer via the second bus of the same name is connected respectively to the second inputs / outputs and inputs of the RAM block, and in the first control channel additionally to the corresponding second inputs / outputs and inputs of a non-volatile memory block, the second inputs and outputs of the block of analog controllers of each control channel are connected to the inputs and the outputs of the input / output unit of analog signals, and the data inputs / outputs and control inputs of this unit are connected to the first buses of the same name with the first microcomputer, the first block of the serial the input / output of control information is provided with inputs and outputs for connecting to the second communication line of the local computer network, and inputs and outputs for organizing communication channels of the first microcomputer, a non-volatile memory block is introduced into each of the (n-1) control channels, the first the data outputs and the first control inputs and addresses of which are connected to the second buses of the same name of the first microcomputer, and the second data inputs / outputs and control inputs and addresses of the same name of the second buses of the second microcomputer, while ervaya and the second microcomputer configured to implement algorithms given in the description in the figures 10, 11, 12, 13.

 In addition, in the digital controller, the RAM block can contain eight input signal conditioners, a static random access memory, two line decoders, two drive configuration settings, four output register buffers, the inputs of the first and fifth input signal conditioners being the first block address inputs, and the inputs of the third and sixth input signal conditioners are the first control inputs, the combined inputs and outputs of the first and third buffer registers ditch drivers are the first inputs / outputs of the unit data, the inputs of the second and seventh input signal conditioners are second address inputs, the inputs of the fourth and eighth input signal conditioners are second control inputs, the combined inputs and outputs of the second and fourth buffer registers of output signals are second inputs / outputs of the data block, the outputs of the first and second shapers of the input signals are connected to the address inputs of a static random access memory the state, the sampling inputs of which are connected to the outputs of the third and fourth shapers of input signals, the outputs of which are connected to the control inputs of the first and second buffer registers-shapers of output signals, the second inputs / outputs of which are connected to the input-outputs of data of a static random access memory, the fifth shaper the input signal outputs are connected through series-connected first line decoder, the first node of the configuration configuration of the drive with the inputs of the third buffer form output signal generator, the outputs of the sixth input driver are connected to the control inputs of the first line decoder and the third buffer register-driver of the output signals, the seventh input driver is connected to the outputs through the second line decoder connected in series, the second drive configuration setting unit with the inputs of the fourth buffer output driver , the outputs of the eighth input driver are connected to the control inputs of the second line decoder and tvertoy buffer register-shaper of output signals.

 In addition, in a digital controller, a non-volatile memory block can contain six input signal conditioners, two status decoders, two address decoders, a line decoder, a line sample signal former, a random-access memory device executed on polarized relays, a written word signal conditioner, four buffer registers -shaper of the output signal, the register of the recorded word, while the outputs of the first and second buffer registers-shapers of the output signal are combined and are the first data outputs, the second inputs of the first driver of the input signal and the first state decoder, as well as the combined control inputs of the first, second, third, fourth, fifth and sixth drivers of the input signals are the first inputs of the control unit, the inputs of the second and third drivers of the water signals are the first inputs addresses, inputs of the fourth and fifth input signal conditioners are second address inputs, second inputs of the sixth input signal conditioner and second decoder melting, as well as the combined third input of the second state decoder and the input of the signal generator of the recorded word are the second control inputs, the inputs and outputs of the third and fourth buffer registers of the output signal, as well as the register of the recorded word are combined and are the second data inputs / outputs, the output of the first shaper of the input signal is connected to the first inputs of the first state decoder, line decoder, second state decoder, the outputs associated with the control inputs of the tre the fifth and fourth buffer registers-shapers of the output signal; the outputs of the first state decoder with control inputs of the first and second buffer registers-shapers of the output signal; the outputs of the second shaper of the input signal are connected to the inputs of the first address decoder, the combined outputs of the third and fourth shapers of the input signals through series-connected line decoder, the shaper of the signal sample lines and random-access memory made on polarized relays are connected to the inputs of the second and third buffer registers shapers of the output signal, the outputs of the fifth shaper of the input signal through the second address decoder are connected to the fourth input of the second state encoder, the outputs of the signal generator of the recorded word are connected to the second inputs of the random access memory, the second outputs to the inputs of the first and fourth buffer registers-shapers of the output signal; the third output of the second state decoder is connected to the input of the recorded word register, the outputs of which are connected with the signal shaper of the recorded word.

 In addition, in a digital control system, the first block of sequential input-output of control information may contain buffer registers-shapers of input and output signals, a shaper of an input signal, three nodes of galvanic isolation, two shapers of an output signal, two commutators of communication channels, combined inputs and outputs of buffer registers-shapers of the input and output signal are inputs and outputs of the data block, and the outputs of the buffer register-shaper of the input signal are outputs of the parallel output of control information, the inputs of the buffer register-shaper of the output signal by the input of the parallel input of control information, the inputs of the shaper of the input signal are the control inputs of the unit, and its outputs are connected to the control inputs of the corresponding buffer registers-shapers of the input and output signal, the outputs of the first and second nodes of galvanic junctions are connected respectively to the inputs of the first and second shaper of the output signal, the outputs of the second shaper of the output signal are connected to the inputs of the first commutator of communication channels, the output of which is the output for organizing the communication channels of the first microcomputer, the outputs of the third galvanic isolation node are the outputs intended for connection to the second communication line of the local computer network, and the inputs are connected to the outputs of the second commutator of communication channels is an input for organizing communication channels of the first microcomputer.

 In addition, in the digital controller, the second block of sequential input / output of control information may contain buffer registers-shapers of input and output signals, two shapers of input signals, two nodes of galvanic isolation, two shapers of the output signal, two commutators of communication channels, while the outputs of the buffer register the output signal shaper is connected to the inputs of the buffer register-shaper of the input signal and are the inputs / outputs of the data block, and the outputs of the buffer register are If the input signal is the output of the parallel output, the input of the buffer register-shaper of the output signal is the input of the parallel input, the inputs of the first driver of the input signal are the control inputs of the first block, and the outputs are connected to the control inputs of the buffer registers of the input and output signals, the inputs of the first galvanic unit junctions are inputs / outputs for connecting to a communication line of a local area network, and outputs through a second output driver are connected inens with the inputs of the first commutator of communication channels, the outputs of which are outputs for organizing the communication channels of the second microcomputer, the outputs of the first driver of the output signal are outputs for connecting to the communication line of the local computer network, and the inputs through the second galvanic isolation node and the second commutator of communication channels are connected to the outputs the second driver of the input signal, the inputs of which form the inputs for the organization of communication channels with the second microcomputer.

 In addition, in a digital controller, the block of analog controllers may contain an input signal shaper, a buffer register of analog controller shapers, an input shaper, a first limiting unit, an analog speed controller, a unit of normalizing scale amplifiers, a control unit, a second limiting unit, and an analog current regulator, analog controller control unit, analog controller enable indicator block, analog controller initialization block, buffer reg outputs analog conditioner condition driver is connected to the inputs of the register of the input signal, which are inputs / outputs of the unit data, the outputs of the register-driver of the input signal are connected to the inputs of the control unit of the analog controllers, the first outputs of which are connected to the inputs of the display unit for turning on the analog controllers, the second outputs connected to the inputs of the buffer register-conditioner of the analog regulators, the third outputs to the inputs of the analog speed controller and analog of the current regulator, and the control inputs of the control unit of the analog controllers to the first output of the control unit and the output of the initialization unit of the analog controllers, the second output of the control unit is connected to the control input of the buffer register-conditioner of the analog regulators, and the third output to the control input of the buffer register-shaper of the input signal, the inputs of the driver of the input signal are the control inputs of the unit, and the outputs are connected to the inputs of the control unit, the inputs of the analog speed controller A bridge, an analog current controller, a block of normalizing scale amplifiers are the analog inputs of the block, and the outputs of an analog current controller and a block of normalizing scale amplifiers are the analog outputs of the block, the outputs of the first and second limiting nodes are connected respectively to the inputs of the analog speed controller and the analog current controller, interconnected sequentially.

 In addition, in the digital controller, the analog input / output block can contain three input signal shapers, a buffer output signal shaper, a control unit, two galvanic isolation nodes, an output signal shaper, an address decoder, an analog-to-digital converter, and digital-to-analog converters of static and dynamic output , three normalizing amplifiers, switches of inputs and outputs of analog signals, inputs of the first driver of the input signal are address inputs, and the outputs through therefore, the connected first node of the galvanic isolation, the driver of the output signal and the address decoder are connected to the inputs of the switches of the inputs and outputs of the analog signals, the control inputs and outputs of which are the inputs and outputs of the analog signals of the unit, the inputs of the second driver of the input signal are the control inputs of the unit, and the outputs are connected to the inputs of the control node, the first output of which is connected to the control inputs of the first and third shaper of the input signal and the buffer shaper the input signal, the control inputs of the analog-to-digital converter, the digital-to-analog converter of the dynamic output, the digital-to-analog converter of the static output are connected to the second, third, and fourth outputs of the control unit, the inputs of the third driver of the input signal and the outputs of the buffer driver of the output signal are data input / output, and the outputs of the third the shaper of the input signal and the inputs of the buffer shaper of the output signal through the second node of the galvanic isolation are connected with the corresponding the corresponding outputs and inputs of the analog-to-digital converter, digital-to-analog converters of dynamic and static output, the input of the analog-to-digital converter through the first normalizing amplifier is connected to the output of the analog input inputs switch, the inputs of which form the analog signal inputs of the unit, the output of the digital-to-analog dynamic output converter through the second normalizing amplifier connected to the control input of the switch of outputs of analog signals, the outputs of which form the outputs of analog block signals, the output of the digital-to-analog converter of the static output is connected to the input of the third normalizing amplifier, the output of which forms the output of the analog signal.

The advantages of the invention are
decentralization of control and regulation functions, the first microcomputer implements a speed control algorithm, and the second microcomputer implements an electric drive control algorithm. Decentralization of functions allows
a) increase the speed of regulation, since the first microcomputer "is not distracted" by the processing of the control algorithm;
b) to simplify the algorithm and writing programs, as it becomes possible to apply standard control algorithms that do not take into account drive control algorithms;
c) apply standard control algorithms and hardware for the whole variety of sectional drives for a multi-motor electric drive;
d) better work out the control algorithm through the use of a second microcomputer to implement the control of electric drives, since there is no need to "be distracted" by regulation;
e) organize non-volatile memory in a digital system due to the time reserve that the second microcomputer has, which allows you to transfer control commands from the remote control to a serial communication channel, which in turn sharply reduces and stabilizes the number of communications of the digital system console with any number of control commands from the remote ;
f) transfer the communication between digital systems of a multi-motor drive to a serial communication channel, which allows you to organize a local computer network for a multi-motor drive, dramatically reduces cable consumption and does not limit the length of the communication line;
increased reliability due to a sharp decrease in communications;
increase in the reliability of controllability of a multi-engine electric drive system;
the presence of analog controllers controlled by a digital system, if necessary, allows expanding the possibilities of constructing various multi-motor drive systems, as well as implementing various types of digital-to-analog controllers (for example, an external control loop - digital, an internal analog loop, etc.).

 In FIG. 1 shows a block diagram of a digital control system for a multi-motor drive; figure 2 structural diagram of the first memory block; figure 3 is a structural diagram of a second memory block; figure 4 is a structural diagram of a first block of serial input-output; figure 5 is a structural diagram of a block of analog controllers; in Fig.6 block diagram of the block analog input-output; Fig.7 is a structural diagram of a second block of serial input-output; on Fig structural block diagram of the output relay and logical signals; Fig.9 is a structural diagram of a block input relay and logical signals; on Fig.11 the algorithm of the first microcomputer; in FIG. 12.13 algorithm of the second microcomputer.

The following notation is accepted:
ША (МЭ1), ШД (МЭ1), ШУ (МЭ1) bus address, data and control of the first microcomputer;
ША (МЭ2), ШД (МЭ2), ШУ (МЭ2) bus address, data and control of the second microcomputer;
CMM (ME1), CMM (ME2) matrix bus of the first and second microcomputers.

 The digital control system for a multi-motor electric drive contains the first 1 and second 2 microcomputers, the first memory block 3, the second memory block 4, the first block 5 serial input-output, block 6 analog controllers, block 7 analog input-output, the second block 8 serial input output unit 9 output relay and logical signals, unit 10 input relay and logical signals, while the first inputs / outputs of data and control of the first microcomputer 1 are connected through the first bus of the same name, respectively, with inputs / outputs and inputs the first block 5 of the serial input-output and block 7 input-output analog signals, the first inputs of the address of the first microcomputer 1 via the bus of the same name are connected to the inputs of the block 7 of the input-output analog signals, second inputs / outputs of data, control outputs and addresses of the first microcomputer 1 through the second bus of the same name are connected respectively to the first inputs / outputs and inputs of the first 3 and second 4 memory blocks, the first inputs / outputs of data and control of the second microcomputer 2 are connected via the first bus of the same name with inputs / output, respectively and the inputs of the second block 8 of serial input-output, block 9 output of relay and logical signals, block 10 input relay and logic, the first outputs of the address of the second microcomputer 2 are connected to the inputs of block 9 output relay and logical signals, block 10 input relay and logical signals , the second inputs / outputs of data, control and addresses of the second microcomputer 2 through the second bus of the same name are connected respectively to the second inputs / outputs of the first 3 and second 4 memory blocks.

 The first memory block contains eight shapers 11-18 input signals, a static random access memory node 19, two decoders 20, 21 lines, two nodes 22, 23 setting the configuration of the drive, four buffer register-shaper 24-27 output signals, while the inputs of the shapers 11 and 15 input signals are the address inputs for connecting to the first microcomputer 1, the inputs of the drivers 13 and 16 input signals are control inputs for connecting to the first microcomputer 1, the combined inputs of the buffer registers-shapers 24 and 26 are are inputs / outputs of data for connecting to the first microcomputer 1, the inputs of the shapers 12 and 17 of the input signals are address inputs for connecting to the second microcomputer 2, the inputs of the shapers 14 and 18 of the input signals are control inputs for connecting to the second microcomputer 2, the combined outputs of the buffer registers -shapers 25 and 27 of the output signals are data outputs for connection to a second microcomputer 2, the output addresses of the shapers 11 and 12 of the input signals are connected to the inputs of a static random access memory (RAM) 19 associated with the output buses of the sample drivers 13 and 14 of the input signals, the control outputs of which are connected to the inputs of the buffer registers of the drivers 24 and 25 of the output signals, the input data buses of which are connected to the data bus of the RAM 18; the driver 15 of the input signals by the output address bus is connected via series-connected line decoder 20, the drive configuration setting unit 22 with the output signal buffer former 26; the control outputs of the shaper 16 input signals are connected to the inputs of the decoder 20 lines and the buffer shaper 26 of the output signal; the shaper 17 of the input signals by the output address bus is connected through series-connected decoder 21 lines, the node 23 for setting the configuration of the electric drive with the shaper 27 of the output signals, the control outputs of the shaper 18 input signals are connected to the inputs of the decoder 21 lines and the buffer shaper 27 of the output signals.

 The second memory block contains six shapers 28-33 of the input signals, the first state decoder 34, the second state decoder 35, the first address decoder 36, the second address decoder 37, the decoder 38 lines, the line shaper 39 signal samples, random access memory (RAM) 40 on polarized relays, the shaper of the recorded word signal 41, four buffer register-shaper 42-45, the register 46 of the recorded word, while the outputs of the buffer registers-shapers 42 and 43 of the output signal are combined and are inputs and outputs for data for connecting to the first microcomputer, the second inputs of the first driver 28 of the input signal and the first state decoder 34, as well as the combined first inputs of the first, second, third, fourth, fifth and sixth drivers 28-33 input signals are control inputs for connecting to the first microcomputer , the inputs of the second and third shapers 29, 30 of the input signals are address inputs for connecting to the first microcomputer, the inputs of the fourth and fifth shapers 31 and 32 of the input signal are address inputs for switching to the second microcomputer, the second inputs of the sixth input signal shaper 33 and the second state decoder 35, as well as the third input of the second state decoder 35 and the input of the recorded word signal shaper 41 are control inputs for connecting to the second microcomputer, the outputs of the third and fourth buffer register-shapers 44 and 45 of the output signal, as well as the register 46 of the recorded word are combined and are inputs / outputs of data for connection to a second microcomputer, the input of the first driver 28 input signal connected to the first inputs of the first decoder 34, a state decoder 38 rows, the second decoder 35 state outputs connected to the inputs of the third and fourth shaping buffer registers 44 and 45 output; the outputs of the first state decoder 34 are connected to the inputs of the first and second buffer registers-shapers 42 and 43 of the output signal; the output bus address of the second shaper 29 of the input signal is connected to the inputs of the first decoder 36 addresses; output address buses of the third and fourth shapers 30 and 31 of the input signals through series-connected line decoder 38, the line sampler 39 and RAM 40 are connected to the data bus of the second and third buffer register-shapers 43 and 44 of the output signal; the output address bus of the fifth input driver 32 through the second state decoder 35 is connected to the fourth input of the second address decoder 37; the output bus of the shaper 41 of the recorded word signal is connected to the inputs of the RAM 40, and the output bus of the status word to the inputs of the first and fourth buffer registers-shapers 42 and 45 of the output signal; the third output of the second state decoder 35 is connected to the input of the register 46 of the recorded word, the output bus associated with the shaper 46 of the signal of the recorded word.

 The first block of serial input / output of control information contains a buffer register-shaper 47 of the input signal, a buffer register-shaper 48 of the output signal, shaper 49 of the input signal, three nodes 50, 51, 52 of galvanic isolation, two shapers 53, 54 of the output signal, two switches 55, 56 communication channels, while the combined inputs and outputs of the buffer registers of the shapers 47, 48 of the input and output signals are inputs and outputs of data for connection to the first microcomputer, and the outputs of the buffer register are formed Filling 47 of the input signal are outputs of a parallel output of control information; the inputs of the buffer register-shaper 48 of the output signal are inputs of a parallel input of control information; the inputs of the shaper 49 of the input signal are control inputs for connecting to the first microcomputer, and its outputs are connected to the control inputs of the buffer registers shapers 47, 48 of the input and output signal, the outputs of the first and second nodes 50, 51 of galvanic isolation are connected respectively to the inputs of the first and second shaper 53, 54 of the output signal, the outputs of the second shaper 54 of the output signal are connected to the inputs of the first switch 55 of the communication channels, the output of which is the output of the serial communication channel ka, the outputs of the third galvanic isolation node 52 are the output communication channels of the unit, and the inputs are connected to the outputs of the second commutator 56 communication channels.

 The second block of serial input / output of control information contains buffer registers-shapers 57, 58 of the input and output signal, the first and second shapers 59, 60 of the input signal, the first and second node 61, 62 of galvanic isolation, the first and second shapers 63, 64 of the output signal , the first and second switch 65, 66 communication channels, while the outputs of the buffer register-shaper 58 of the output signal are connected to the inputs of the buffer register-shaper 57 of the input signal and are the address inputs of the block, and the output of the buffer register-shaper 57 of the input signal is a parallel output, the input of the buffer register-shaper 58 of the output signal is a parallel input, the inputs of the first shaper 59 of the input signal are inputs of the control unit, and the outputs are connected to the inputs of the buffer registers-shapers 59, 63 of the input and output signals, the inputs of the first node 61 galvanic isolation are input communication channels, and the outputs through the second driver 64 of the output signal are connected to the inputs of the first switch 65 communication channels, output dy which are the output channels of the serial communication, outputs the first output signal generator 63 are output communication channels, and inputs through the second node 62 and a second electrical isolation switch 66 communication channels are connected to the outputs of the said second input signal, the outputs of which are input serial communication channels.

 The block of analog controllers contains the register-driver 57 of the input signal, the buffer register-driver 68 of the status of the analog controllers, the driver 69 of the input signal, the first node 70 limits, the analog speed controller 71, the block 72 normalizing scale amplifiers, the node 73 controls, the second node 74 restrictions, analog current controller 75, analog controller control unit 76, analog controller enable indicator block 77, controller initialization unit 78, outputs of the state register-shaper 68 regulators taxes connected to the inputs of the input-signal generator 67 and the register are data inputs-outputs for connection to the first microcomputer outputs the register-generator 67 through the input control unit 76 controls the analog display unit associated with the inclusion of analog inputs 77 regulators; the outputs of the analog control unit 76 are connected to the inputs of the analog register regulator 68, the analog speed controller 71, the analog current controller 75, and the inputs of the analog control unit 76 are connected to the output of the control unit 73 and the output of the analog controller initialization unit 78, another input the control unit 73 is connected to the output of the buffer register-shaper 68 of the status of the analog controllers, the outputs of the shaper 69 of the input signal to the inputs of the control unit 73, the inputs are anal of a speed controller 71, an analog current controller 75, a block 72 of normalizing scaling amplifiers form the inputs of analog signals, and the outputs of an analog controller of 75 current and a block of 72 normalizing scale amplifiers are the outputs of the analog signals, the outputs of the first and second node 70, 74 of the limitation are connected respectively to the inputs of the analog a speed controller 71 and an analog current controller 75, connected in series.

 The input / output block of analog signals contains three shapers 79, 80, 81 input signals, a buffer shaper 82 of the output signal, a control unit 83, two nodes 84, 85 of galvanic isolation, a shaper 86 of the output signal, an address decoder 87, and an analog-to-digital converter ( ADC) 88, digital-to-analog converter (DAC) 89 dynamic output, digital-to-analog converter (DAC) 90 static output, three normalizing amplifiers 91, 92, 93, switches 94, 95 input and output analog signals, inputs of the first driver 79 input with Ignals are address inputs for connecting to the first microcomputer, and the outputs through series-connected first node 84 of galvanic isolation, driver of output signal 86 and decoder 87 of address are connected to inputs of switches 94, 95 of input and output analog signals, inputs and outputs of which form inputs / outputs analog signals of the block, the inputs of the second driver 80 of the input signal are control inputs for connecting to the first microcomputer, and the outputs through the control unit 83 are connected to the inputs of the first and third shapers 79, 81 of the input signal, the buffer shaper 82 of the output signal, the control inputs of the ADC 88, the DAC 89 of the dynamic output, the DAC 90 of the static output are connected to the outputs of the node 83 control, the inputs of the third shaper 81 of the input signal and the outputs of the buffer shaper 82 of the output signal are inputs / data outputs for connection to the first microcomputer, and the outputs of the third input driver 81 and the inputs of the output driver buffer 82 through the second galvanic isolation unit 85 are associated with the ADC 88, DAC 89 and 90, the ADC input 88 through the first normalizing amplifier 91 is connected to the output of the switch 94 of the input analog signals, the inputs of which are inputs of the analog signals of the unit, the output of the DAC 89 through the second normalizing amplifier 92 is connected to the input of the switch 95 analog output signals, the outputs of which are the outputs of the analog signals of the unit, the output of the DAC 90 is connected to the input of the third normalizing amplifier 93, the output of which is the output of the analog signal.

 The relay and logic signal output unit comprises an address input signal shaper 96, a control input signal shaper 97, a buffer register-shaper 98 of the input signal, a buffer register-shaper of the input signal 99, an address decoder 100, a sampling and control unit 101, and a buffer register-shaper 102 of the state the first relay output port, registers 103 and 104 of the first and second relay output ports, the buffer register-former 105 of the state of the second relay output port, the first output port 106 relay signals, the second port 107 output relay signals, node 108 galvanic isolation, two shapers 109 and 110 output signals, nodes 111, 112, 113 indicate the status of logical signals of the first output port relay signals, the second port output relay signals, node 114 initialization of the first and the second input ports of relay signals, while the input of the shaper 96 of the input signal of the address is the input of the address to connect to the second microcomputer, the input of the shaper 97 of the input signal of the control bus control to connect to W a swarm of microcomputers, the combined inputs of the buffer register-conditioner 98 of the state, the buffer register-shaper 99 of the input signal, the buffer register-shaper 102 of the state of the first output port of the relay signals, the register 103 of the first output port of the relay signals, the register 104 of the second port of the output of the relay signals, the buffer register -shaper 105 state of the second port output relay signals are inputs / outputs of data for connection to a second microcomputer, the outputs of the first driver 109 output signal outputs log of the natural signal, the outputs of the second port 107 of the output of the relay signals by the second output of the relay signals, the node 101 sampling and controlling inputs is connected to the output bus of the driver 96 of the input control signal and through the address decoder 100 with the output bus of the driver 96 of the input address signal; the outputs of the sampling and control unit 101 are connected to the inputs of the buffer register-shaper 98 of the state, the buffer register-shaper 99 of the input signal, the buffer register-shaper 102 the state of the first output port of the relay signals, registers 103 and 104 of the first and second ports of the output of relay signals, the buffer register -shaper 105 state of the second port output relay signals; the outputs of the buffer register-shaper 99 of the input signal are connected to the inputs of the node 108 galvanic isolation, the outputs connected to the inputs of the first and second shapers 109, 110 of the output signal, and the outputs of the second shaper 110 of the output signal are connected to the inputs of the node 111 indicating the status of logical signals, the outputs of the first port 106 outputs of relay signals are connected to the inputs of the buffer register-former 102 of the state of the first port for outputting relay signals, the inputs of the first port 106 of outputting relay signals are connected are connected to the outputs of the register 103 of the first relay output port and the node 114 for initializing the first and second relay output ports, the outputs of the second relay output port 107 are connected to the inputs of the buffer register-conditioner 105 of the second relay output port and the second port status indication 113 the output of relay signals, the inputs of the second port 107 of the output of the relay signals with the outputs of the register 104 of the second port of the output of the relay signals and the node 114 of the initialization of the first and second ports of the output of the relay signals fishing.

 The input unit of relay and logical signals contains a driver 115 of the input relay signals, a driver 116 of the input signal addresses, a driver 117 of the input control signals, a node 118 of galvanic isolation, an address decoder 119, a node 120 of a signal sample, a signal driver 121, a node 122 for indicating the status of logical signals, shaper 123 of the signal samples of rows, node 124 indicating the status of relay signals, random access memory (RAM) 125, read-only memory (ROM) 126, driver 127 output signal, the first and W swarm buffer registers-shapers 128, 129 of the output signal, the inputs of the shaper 115 of the input relay signals form the inputs of the relay signals, and the outputs are connected to the inputs of the node 124 indicating the status of the relay signals and the shaper 123 of the signal line selection, the inputs of the shaper 116 of the input address signals are address inputs connections to the second microcomputer, and the outputs through series-connected decoder 119 addresses and the shaper 123 of the signal sample lines are connected to RAM 125 and ROM 126, the outputs of which through the shaper 127 output one signal are connected to the first buffer register-shaper 128 of the output signal, the inputs of the shaper 117 of the input control signals are control inputs for connecting to the second microcomputer, and the outputs through the node 120 of the signal selection are connected to the inputs of the first and second buffer registers-shapers 128, 129 of the output signal the outputs of which are inputs / outputs of data for connection to a second microcomputer, the inputs of the galvanic isolation unit 118 form the inputs of logical signals, and the outputs through the signal driver 123 second buffer register, output shaper 129, input node 122 of the status display logic signals are connected to the outputs of the signal generator 121.

 In the first memory block, eight shapers of 11-18 input signals are made on K55LP10, K155LP11 microcircuits.

 The static random access memory 19 is made on chips KR537RU10 with a total capacity of 16K x 8 (2K x 8 bits in each crystal).

 The first and second buffer registers-shapers 24, 25 of the output signals are made on chips KR580VA86.

 The first and second decoders 20.21 rows of the matrix are made on chips K155ID3.

 The third and fourth buffer shapers 26, 27 of the output signals are made on chips KR580IR82.

 Shapers 28-33 of the input signal of the second memory block are made on chips K155LP10 and K155LP11.

 The first address decoder 36 is made on a K155ID4 chip.

 The first state decoder 34 is made on K155ID4, K155LL1 microcircuits.

 The decoder 38 lines is made on a chip K155ID4.

 Shaper 39 of the signal sample lines is made on chips K155LI5.

 The matrix of random access memory 40 is made on polarized relay type RPS-45 with a total capacity of 4 x 16 bits.

 The first and second buffer registers-shapers 42, 43 of the output signal are made on chips KR580IR82.

 The third and fourth buffer registers-shapers 44, 45 of the output signal are made on chips KR580IR82.

 Register 46 of the recorded word is made on K155TM8 microcircuits.

 Shaper of the recorded signal signal is assembled on K155ID4, K155LP11, K155LL1, K155AG3, K155TM8 microcircuits.

 Buffer registers-shapers 47, 48 of the first block of sequential input-output of control information are made on chips KR580IR82.

 The input signal shaper is made on K155TL2 and K155LL1 microcircuits.

 The first switch 55 of the communication channels (input signals) is made on the K155ID4 and K155LP8 microcircuits.

 The second switch 56 communication channels (output signals) is made on a chip K155ID4.

 Buffer registers-shapers 57, 58 of the input and output signal of the second input-output block are made on the KR580IR82 chip.

 The first and second shapers 59, 60 of the input signal are made on chips K155LP10.

 Switches 65, 66 communication channels are made on K155LP8 microcircuits.

 The register-driver 67 of the input signal of the block of analog controllers is made on the K155TM8 chip.

 The buffer register-shaper 68 of the status of the analog controllers is made on the chip KR580IR82.

 The analog controller control device 76 is made on polarized RPS45 relays and KT503E transistors.

 The control unit 73 is assembled on K155AG3, A155TM8, K155LL1 microcircuits.

 The initialization unit 78 is made on a K142EP1B chip and KT503E and KT817G transistors.

 The node 77 indicating the status of analog controllers is made on a single indicator LEDs AL307AM.

 On the K553UD2 microcircuits a double-circuit regulation system is made (current regulator 75 and speed regulator 71).

 Block 72 of normalizing large-scale amplifiers assembled on K553UD2 microcircuits.

 Shapers 79, 81 of the input signals of the input-output block of analog signals are made on the K155LP10, K155TM8 microcircuits.

 The buffer driver 82 of the output signal is made on a chip KR580IR82.

 The address decoder 87 is made on K155TM8, K155ID4 microcircuits.

 The digital-to-analog converter 89 of the dynamic output is made on the chip K572PA2A.

 The digital-to-analog converter 90 of the static output is made on the chip K572PA2A.

 The analog-to-digital Converter 88 is made on a chip K1113PV1A.

 The first, second and third standardizing amplifiers 91-93 are made on chips KR544UD2A.

 The switch 94 of the input analog signals is made on a chip KR590KN6.

 The switch 95 of the output analog signals is made on the KR590KN6 chip.

 The shaper of the input signal of the address and the input control signal is made on the chip K155LP10.

 The address decoder 100 is made on a K155ID4 chip.

 The node 101 of the selection and control is made on microcircuits K155LL1, K155AG3, K155LN1, K155TM2, K155IE5.

 The buffer register-driver 99 of the input signal is made on the chip KR580IR82.

 The node 111 indicating the status of logical signals is made on a seven-segment indicator.

 The buffer register-shaper 98 state is made on the chip KR580IR82.

 The first and second registers 103, 104 of the output port of the relay signals are made on chips K155TM8.

 The first and second ports 106, 107 output relay signals are made on polarized relay type RPS-45.

 The node 114 of the initialization of the first and second ports for outputting relay signals is assembled on a K142EP1B chip and KT503E transistors.

 Buffer registers-shapers 102, 105 of the first and second ports for outputting relay signals are made on chips KR580IR82.

 Shaper 115 of the input relay signals of the input unit of the relay and logical signals is made on the relay RES47.

 Shaper 116 of the input signals of the address is made on the chip K155LP10.

 Shaper 117 of the input control signals is made on chips K155LP10 and K155LL3.

 The node 120 of the signal sampling is made on microcircuits K155LP3 and K155LL1.

 The address decoder 119 is made on the K155ID3 chip.

 Shaper 123 of the signal samples of the rows is made on chips K155LP4.

 RAM 125 relay signals are assembled in the form of a matrix consisting of NO contacts of relay RES47 with a total capacity of 3 x 8 bits.

 Permanent storage device 126 is made in the form of a matrix with a total capacity of 13 x 8 bits. By setting jumpers in each row of the matrix, you can get the configuration of external devices that the user needs.

 Shaper 127 of the output signal is made on transistors KT315G.

 The first and second buffer registers-shapers 128, 129 of the output signal are made on chips KR580IR82.

 The digital system is used as the main device in the control and regulation system of the electric drive of the paper machine section and is intended for receiving and generating feedback signals, tasks, digital speed control, issuing control actions on power units, as well as for receiving, processing relay and logic control signals and issuing control actions on power control elements.

 The digital system includes two microcomputers. The first microcomputer is used to receive tasks and feedbacks in digital form, to process digital control programs, and to issue a regulatory effect in digital or analog form.

 The second microcomputer serves to receive information on the local area network, receive, process and issue control actions of the logical control of the section, output information to the local area network, and also communicate with the technology control panel.

 The exchange of information between the first and second microcomputers is carried out using two blocks of 3.4 memory.

 The microprocessor system, implemented in a digital system, operates under the control of a work program that is stored in permanent storage devices of the first and second microcomputers and is not accessible to the user. The work programs are designed specifically for electric paper machine in accordance with the algorithm of the section shown in the drawings of figure 10 13.

 The signals from the speed sensor are fed to the first control information input / output block 5, where they are formed, presented in a form convenient for processing, and transmitted to the first microcomputer.

 The organization of the input and output channels of serial communication with the first microcomputer is carried out using the first block 5 input-output control information. Using the same block, parallel output and parallel input of information from standard external devices (display, printing device, etc.) is carried out via the data bus of external devices of the first microcomputer. Input and input of analog signals is organized through block 6 analog controllers and block 7 analog input-output via the data bus of external devices of the first microcomputer.

 The organization of the input and output channels of serial communication with the second microcomputer is carried out using the second block 8 input-output control information. Using the same block, parallel output and parallel input of information from standard external devices via the data bus of external devices of the second microcomputer is carried out. The output of logical and relay signals is organized via the data bus of external devices of the second microcomputer. The output of logical and relay signals is organized via the data bus of external devices of the second microcomputer using block 9 output relay and logic signals. On the same bus with the help of block 10 input relay and logical signals, the input into the microprocessor system of logical and relay signals.

 The first memory block serves to exchange information between the processors of the first and second microcomputers, as well as to set the configuration of the electric drive for the first and second microcomputers, for which it contains 16 eight-bit words of read-only memory for the processor of the first microcomputer and the processor of the second microcomputer.

 Eight input signal conditioners 11-18 serve to form address buses and sample buses of the random access memory of the first and second microcomputers.

 The TA signal allows the processors of the first and second microcomputers to access the second memory block.

 Static random access memory 19 is used to store and read information.

 The first and second buffer registers 24, 25 are used to generate data bus signals of the first and second microcomputers.

 The first and second decoders 20, 21 lines are used to decrypt the address of the lines of the first and second matrix nodes 22, 23 setting the configuration of the drive.

 The second node 23 to configure the drive with a capacity of 16 x 8 bits is used to set the user configuration of the second microcomputer.

 The third buffer driver 26 of the output signals is used to generate output signals from the first matrix of the node 22 setting the configuration of the electric drive for the first microcomputer.

 The fourth driver 14 of the output signals is used to generate output signals from the second matrix of the node 23 setting the configuration of the electric drive for the second microcomputer, which are received on the data bus of the second microcomputer.

 The second block of memory allows you to organize read and write cycles of the first and second microcomputers.

 The reading cycle of the first microcomputer is as follows: when signals are received via the address bus and the control bus of the first microcomputer, a certain chip of random access memory 19 is sampled, the output of which appears in accordance with the address received by the chip of the random access memory. Further, this information is supplied to the first buffer register-shaper 24 of the output signals.

 Upon receipt of the buffer control signal from the third shaper 13 of the input signals, the first buffer register-shaper 24 opens and signals are generated at its output, which are fed to the data bus of the first microcomputer.

 The reading cycle of the second microcomputer occurs similarly to the above.

 The recording cycle of the first microcomputer is as follows: when signals are received via the address bus of the first microcomputer, a specific chip of the RAM is sampled 19. Information from the data bus of the first microcomputer via the first buffer register-shaper 24 of the output signals is transmitted to the selected RAM. Then, the information received is recorded in accordance with the address from the first microcomputer.

 The recording cycle of the second microcomputer is similar.

 Reading the signals of setting the configuration of the electric drive of the first microcomputer is as follows: when signals are received via the address bus and the control bus of the first microcomputer, the row address of the first matrix of the unit 22 of setting the configuration of the electric drive is sampled. Next, the address of the matrix row is decrypted and a current for reading information is generated. The signals of setting the configuration of the electric drive are read by the first microcomputer from the columns of the matrix and through the third buffer driver 26 of the output signals is fed to the data bus of the first microcomputer.

 The second memory block is made on polarized relays and serves to exchange information between the second and first microcomputers, as well as to store reference information on a task in all modes.

 The first, second, and third input signal conditioners 28, 29, 30 serve to form the address bus and control signals of the first microcomputer.

 The fourth, fifth, and sixth input signal conditioners 31, 32, 33 serve to form the address bus and control signals of the second microcomputer.

 The TA signal calls the first and second microcomputers to the first memory block.

 The first address decoder 36 is used to decrypt the address received on the address bus of the first microcomputer.

 The second state decoder 35 serves to generate data output signals, output the status word of the second microcomputer and the input signal of the recorded word from the second microcomputer.

 A line decoder 38 is used to select a matrix row of a random access memory 40 on polarized relays.

 Shaper 39 of the signal samples of the rows is used to generate a current for reading information from the selected row of the matrix of random access memory 40.

 The random access memory 40 serves to store information.

 The first and second buffer registers-shapers 42, 43 of the output signal are used to generate data bus signals of the first microcomputer.

 The third and fourth buffer registers-shapers 44, 45 of the output signal are used to generate data bus signals of the second microcomputer.

 The register 46 of the recorded word is used to enter the recorded word from the second microcomputer.

 Shaper of the signal of the recorded word is used to generate a signal of the recorded word.

 The second memory block allows you to organize the read and write cycles of the second microcomputer and the reading cycle of the first microcomputer.

 The reading cycle of the first microcomputer occurs as follows: when reading signals, samples, and signals are received via the address bus of the first microcomputer, the matrix row of the random access memory 40 is sampled on the polarized relays and an information read current is generated from the selected matrix row of the random access memory 40 and the read information fed to the second buffer register-shaper 43 of the output signal.

 When a data output signal arrives, register 43 opens and signals are generated at the output, which are fed to the data bus of the first microcomputer. Before the reading cycle, it is necessary to read the block status word, which indicates the possibility of the first microcomputer accessing the first memory block. The block status word is supplied to the first buffer register-shaper 42 of the output signal. When a status word output signal arrives, register 42 opens and a block status word signal is generated at its output, which is fed to the data bus of the first microcomputer.

 The reading cycle of the second microcomputer occurs similarly to the above.

 The recording cycle of the second microcomputer is as follows: the signals from the second microcomputer are fed from the data bus to the register 46 of the recorded word for recording in the matrix of the random access memory 40. When the recording signals, samples and signals are received via the address bus of the second microcomputer, the row of the matrix of the operative memory device 40 and information received in the register 46 of the recorded word is recorded in the selected row of the matrix of random access memory 40 on polarized relays.

 Before the recording cycle, it is necessary to read the block status word, which indicates the possibility of the second microcomputer accessing the first memory block. The block status word is supplied to the fourth buffer register-shaper 45 of the output signal. When a signal is received, the output of the status word of the register 45 is opened and at its output a signal is generated from the status word of the block, which is fed to the data bus of the second microcomputer.

 The first block of serial input / output of control information is intended for organizing input and output channels of serial communication of a local computer network, for distributing currents between electric motors, for inputting a signal from a speed sensor with galvanic separation of circuits, and also for connecting the unit to standard external devices (display, printing device, etc.).

 The buffer register-shaper 47 of the input signal is used to generate input signals of the data bus.

 The buffer register-shaper 48 of the output signal is used to generate the output signals of the data bus.

 Shaper 49 of the input signal is used to generate signals of the control bus.

 The first driver 53 of the output signal is used to generate a speed signal from the speed sensor.

 The first switch 55 communication channels (input signals) is used to select one of three consecutive communication channels.

 The second switch 56 communication channels (output channels) is used to select one serial communication channel using control signals of communication channels.

 To connect the unit with standard external devices, a bus (eight bits) of parallel output and a bus (eight bits) of parallel input are provided.

 The organization of channels of parallel input and output is carried out using buffer registers-shapers 47, 48 of the input and output signal.

 When signals are received via the data bus and control signal of the parallel output, the buffer register-shaper 47 of the input signal is opened and signals are generated at its output and supplied to an external device. When signals are received from external devices via the parallel input bus and the parallel input control signal, the buffer register-shaper 48 of the output signal is opened and signals are output at its output, which are fed to the data bus.

 The signals from the speed sensor enter through the first node 50 galvanic isolation and are supplied to the first driver 53 of the output signal, the output of which is generated signals proportional to the speed, which are displayed on the first microcomputer.

 The input signals from the local area network via communication channels are fed through the second node 51 galvanic isolation to the second driver 54 of the output signal. The signals from the output of this shaper are fed to the input of the first switch 55 communication channels. Using the control signals of the communication channels arriving at the inputs of the first switch 55 of the communication channels, one serial communication channel is selected and the signal is fed to the programmable serial interface of the first microcomputer.

 The output serial communication channel from the programmable serial interface of the first microcomputer is fed to the second commutator 56 communication channels.

 Using the control signals of the communication channels arriving at the inputs of the second commutator 56 of the communication channels, a serial communication channel is switched and, through the third galvanic isolation unit 52, are output to the communication line of the local computer network.

 The second block of serial input / output of control information is intended for organizing input and output channels of serial communication of a local computer network with galvanic separation of circuits, as well as for connecting the processor of the second microcomputer with standard external devices (display, printing device, etc.).

 The buffer register-driver 57 of the input signal is used to form the input signals of the data bus of the second microcomputer.

 The buffer register-shaper 58 of the output signal is used to generate the output signals of the data bus of the second microcomputer.

 The first driver 59 of the input signal is used to generate signals of the control bus of the second microcomputer.

 The second input signal conditioners 60 are used to form input serial communication channels.

 The first and second switches 65, 66 of the communication channels are used to select the main or standby serial communication channels for supplying a second microcomputer to the programmable serial interface.

 To connect the processor of the second microcomputer with standard external devices, the unit provides buses (eight bits) of parallel output and a bus (eight bits) of parallel input. The organization of channels of parallel input and output is carried out using buffer registers-shapers 58, 58 of the input and output signal. When signals are received via the data bus of the second microcomputer and the control signal of the parallel output, the buffer register-shaper 57 of the input signal opens and signals are output at its output that are supplied to external devices. When signals are received from external devices via the parallel input bus and the parallel input control signal, the buffer register-shaper 58 of the output signal is opened and signals are outputted to the data bus of the second microcomputer.

 The input communication channels enter through the first node 61 galvanic isolation to the second driver 64 of the output signal. The signals from the output of this shaper are fed to the input of the first switch 65 communication channels. Using the control signals of the communication channels supplied to the inputs of the first switch 65 communication channels, the main or standby serial communication channels are selected, which are fed to the programmable serial interfaces of the second microcomputer.

 The input channels of serial communication from the programmable serial interfaces of the second microcomputer are fed to the second driver 60 of the input signal, and then to the second switch 66 of the communication channels. Using the control signals of the communication channels arriving at the inputs of the second switch 66 of the communication channels, the main or backup serial communication channels are switched. The formed communication channels through the second node 62 galvanic isolation and the first driver of the output signal are output in line for the organization of serial communication channels.

 The block of analog controllers is designed to organize analog control loops, as well as to normalize analog signals input to the microprocessor system.

 Register-shaper 67 of the input signal is used to generate input signals of the data bus.

 The buffer register-shaper 68 of the status of the analog controllers is used to generate the status word of the analog controllers, which is displayed on the data bus.

 The status word of the analog controllers indicates the status of the analog controllers: on or off. In the off state, the analog controllers 71, 75 are shorted by the closing contacts of the polarized relays, which, together with the amplifier, form a control device 76 of the analog controllers.

 The control unit 73 is used to generate control signals of the control unit 76 of the analog controllers, the register-driver 67 of the input signal and the buffer register-driver 68 of the status of the analog controllers.

 The initialization unit 78 serves to turn off the analog controllers when a power supply is applied or in the event of a power failure, while the make contacts of the polarized relays close.

 For monitoring the status of analog controllers, a node 77 for indicating the status of analog controllers is also provided.

 The two-contact control system consists of a current regulator 75 and a speed regulator 71. The configuration of the analog control system is selected depending on the desired operation algorithm and is set by the corresponding jumper connection in the block of analog controllers.

 The drive control signals are removed from the output of the current regulator. On the speed controller 71 and current controller 75, restriction nodes 70, 74 are provided.

 Block 72 normalizing scale amplifiers is used to normalize the level of analog signals that are fed to the analog-to-digital Converter 87 of the input-output block of analog signals.

 The input / output unit of analog signals is designed to input analog signals, convert signals to digital form with galvanic separation of circuits, as well as to convert digital signals to analog and output analog signals with galvanic separation of circuits.

 The first, second, third input signal conditioners 79, 80, 81 serve to form the address bus, control bus, and data bus input signals.

 The buffer driver 82 of the output signal is used to generate the output signals of the data bus.

 The address decoder 87 is used to select the address of one of the analog inputs or analog outputs.

 The digital-to-analog converter 89 of the dynamic output and the digital-to-analog converter 90 of the static output are used to convert digital signals to analog.

 Switch 94 inputs of analog signals is used to select one of the analog signals in accordance with the address coming from the address decoder.

 The control unit 83 serves to generate control signals of the first and third input signal shapers 79, 81, an output signal buffer shaper 82, an analog-to-digital converter 88, and digital-to-analog converters 89, 90 of dynamic and static output.

 The input of analog signals and their conversion to the digital phase is carried out as follows: input analog signals are fed to the switch 94 of the inputs of analog signals, which, in accordance with the received address, selects one of eight analog signals. The selected analog signal through the first normalizing amplifier 91 is fed to the input of the analog-to-digital converter 88. When the control signal of the analog-to-digital converter 88 is received, the analog signal is converted into a digital signal, which is fed to the input of the output signal buffer shaper 82 through the second galvanic isolation unit 85.

 The control unit 83 opens the buffer driver 82 and at its output a digital equivalent of the analog signal is generated, which is fed to the data bus.

 The conversion of digital signals to analog and their output with galvanic separation of the circuits is as follows: a digital signal from the data bus through the third driver 81 of the input signal and the second node 85 of the galvanic isolation is fed to the digital-to-analog converter 89 of the dynamic output. Upon receipt of the control signal of the digital-to-analog converter 89 of the dynamic output, the digital signal is converted into an analog signal, which, through the second normalizing amplifier 92, is fed to the input of the switch 95 of the output analog signals. The switch 95 in accordance with the received address selects one of eight outputs of the analog signals, to which the converted analog signal is supplied and through the terminal connectors are output from the block.

 Block 9 output relay and logic signals is designed to output control signals with galvanic separation of the output circuits, as well as to indicate the status of relay and logic signals.

 Shapers 96, 97 of the input address signal and the input control signal are used to generate address buses and control the second microcomputer.

 The address decoder 100 is used to decode the signals arriving on the address bus of the second microcomputer.

 The node 101 sampling and control is used to generate control signals registers 103, 104 of the first and second ports for outputting relay signals, buffer registers-shapers 102, 105 state of the first and second ports for outputting relay signals, buffer registers-shapers 98, 99 status and input signal, as well as a control signal for the node 114 of the initialization of the first and second output ports of the relay signals.

 The buffer register-driver 99 of the input signal is used to generate signals from the data bus of the second microcomputer, which are fed to the node 108 galvanic isolation, which is used to obtain galvanically isolated output logic signals.

 The first and second shapers 109, 110 of the output signal are used to generate signals from the node 108 galvanic isolation.

 The node 111 indicating the status of logical signals is used to monitor the status of logical signals.

 The buffer register-shaper 98 status is used to generate a word status block output relay and logical signals. Four bits of the status word are used to determine the state of four logical signals, the other four bits indicate the possibility of the processor of the second microcomputer accessing the block 9 for outputting relay and logical signals.

 The registers 103, 104 of the first and second relay output ports serve to generate the enable signals of the corresponding polarized relay windings of the first and second relay output ports 106, 107.

 The node 114 of the initialization of the first and second output ports of the relay signals serves to reset the ports 106, 107 output relay signals after turning on the power or in the event of a power failure.

 The buffer registers-shapers 102, 105 of the state of the first and second relay output ports serve to generate the status signals of the polarized relays of the first and second relay output ports 106, 107, which are received on the data bus of the second microcomputer.

 The process of outputting logical signals is as follows: when signals are received via the data, address, and control buses of the second microcomputer, the sampling and control unit 101 generates a signal that opens the buffer register-driver 99 of the input signal, and the signals from its output through the galvanic isolation unit 108 are sent to the first and a second output driver 109, 110. At the output of the first shaper 109 we obtain galvanically isolated logical signals. The state of these logical signals is monitored using the node 111 indicating the status of the logical signals.

 The process of outputting relay signals is carried out as follows: when signals are received via the data, address and control buses of the second microcomputer, the sampling and control unit 101 opens a register 103 or 104 of the first or second ports 106, 107 for outputting relay signals, the output of which is formed by signals that control the switching on of the corresponding windings of polarized relays of the first or second ports 106, 107 output relay signals. The state of the relay is monitored by the initialization unit 114 of the first and second relay output ports and the state indication unit 113 of the second relay output port.

 The state signals of the first and second ports 106, 107 output relay signals are output through the buffer registers-shapers 102, 105 status of the output ports of the relay signals to the data bus of the second microcomputer.

 After the power is turned on or in the event of a power failure, the first and second ports 106, 107 of the output of the relay signals are forced to initialize to set them to the zero position.

 The input unit of 10 relay and logic signals is intended for input into the system of control relay and logic signals with galvanic separation of input circuits.

 Shaper 115 input relay signals is used to generate input relay signals.

 Shaper 116 of the input address signals is used to generate address bus signals of the second microcomputer.

 Shaper 117 input control signals is used to generate signals of the control bus of the second microcomputer.

 The signal sampling unit 120 serves to control the first and second buffer registers-shapers 128, 129 of the output signal, as well as to generate a sample signal received at the address decoder 119.

 The address decoder 119 is used to sample the matrix row of the random access memory 125 of the relay signals or the matrix of the read-only memory 126.

 Shaper 123 of the signal samples of the rows is used to generate a signal of the selection of rows of matrices random access memory device 125 of the relay signals and read-only memory device 126.

 Shaper 127 of the output signal is used to generate a signal from a selected row of matrices of random access memory device 125 of the relay signals or read-only memory device 126.

 The first and second buffer registers-shapers 128, 129 of the output signal are used to form the data bus signals of the second microcomputer.

 The signals from external devices control the inclusion of the relay shaper 115 input relay signals. The status of the relay is monitored using seven-segment indicators of the node 124 indicating the status of the relay signals.

 Block 10 input relay and logical signals allows you to organize a cycle of reading the state of the relay of the second microcomputer. When signals are received via the address and control buses of the second microcomputer, the matrix row of the RAM memory 125 of the relay signals is selected and the relay status information from the selected matrix row is supplied through the output signal shaper 127 to the first buffer register-shaper 128 of the output signal. When a control signal is received by the first buffer register-shaper 128 of the output signal from the signal sampling unit 120, this register opens and a relay status signal is generated at its output, which is transmitted to the data bus of the second microcomputer.

 In the matrix of the read-only memory 126, information is set by the user by setting appropriate jumpers. This information is output to the data bus of the second microcomputer similarly to the relay status reading cycle described above.

 The input block of relay and logical signals allows you to organize the input of four galvanically isolated logical signals. Logical signals from the output of the signal shaper 121 from the galvanic isolation unit 118 are supplied to the second buffer register-shaper 129 of the output signal. When a control signal is received by the second buffer register-shaper 129 of the output signal from the signal sampler 120, this register opens and logical signals are generated at its output, which are fed to the data bus of the second microcomputer. The state of the logical signals is monitored using the node 128 indicating the status of the logical signals.

 Thus, the proposed technical solution allows you to: increase the reliability of controllability of the multi-motor drive system, build various multi-motor drive systems, implement various types of digital-to-analog controllers.

Claims (7)

 1. A digital controller for a multi-motor drive, containing n control channels according to the number of electric motors, each of which contains a first microcomputer, a random access memory (RAM) unit, a first block of sequential input / output of control information with inputs for inputting a signal from a speed sensor, an input unit / output of analog signals, an input / output unit for relay and logic signals with inputs and outputs for input and output of control signals from external devices, the first inputs / outputs of data being the first microcomputers are connected via the first bus of the same name, respectively, to the inputs / outputs of the sequential input / output unit of control information and the input / output unit of analog signals, the first outputs of the address and control of the first microcomputer via the first bus of the same name are connected to the inputs of the input / output unit of analog signals, the second inputs / data outputs, control outputs and addresses of the first microcomputer through the second bus of the same name are connected respectively to the first inputs / outputs and inputs of the RAM block, the first control channel contains a non-independent memory block, the first data outputs and the first control inputs and addresses of which are connected to the second buses of the same name on the first microcomputer, characterized in that a second microcomputer, a second block of sequential input / output of control information, the first inputs and outputs of which are intended for connections to the communication line of the local computer network, a block of analog controllers with first inputs for inputting current and speed feedbacks and outputs for outputting electric control signals house, and the first inputs / outputs of the data and the control outputs and addresses of the second microcomputer via the bus of the same name are respectively connected to the inputs / outputs and inputs of the input / output unit of the relay and logic signals, data inputs / outputs and control inputs of the second unit of sequential input / output of control information connected to the first buses of the same name with the second microcomputer, and the second inputs and outputs are used to organize communication channels with the second microcomputer, the second data inputs / outputs and control outputs and addresses of the second microcomputer through the same bus of the same name are connected respectively to the second inputs / outputs and inputs of the RAM block, and in the first control channel additionally to the corresponding second inputs / outputs and inputs of a non-volatile memory block, the second inputs and outputs of the analog controller block of each control channel are connected to the inputs and outputs of the input block / output of analog signals, and the data inputs / outputs and control inputs of this unit are connected to the first buses of the same name of the first microcomputer, the first block of serial input / output of the control The information is equipped with inputs and outputs intended for connecting to the second communication line of the local computer network, and inputs and outputs intended for organizing communication channels of the first microcomputer, a non-volatile memory unit, first data outputs and first control inputs are introduced into each of the n-1 control channels and the addresses of which are connected to the second buses of the same name of the first microcomputer, and the second data inputs / outputs and control inputs and addresses to the second buses of the same name of the second microcomputer, while the first and second microcomputers Nena capable of implementing the algorithms given in the description of FIG. 10 13.  2. The controller according to claim 1, characterized in that the RAM unit contains eight input signal conditioners, a static random access memory, two line decoders, two drive configuration settings, four output recorder buffers, the inputs of the first and fifth shapers of the input signals are the first inputs of the block address, and the inputs of the third and sixth shapers of the input signals are the first control inputs, the combined inputs and outputs of the first and third buffer registers drivers are the first inputs / outputs of the unit data, inputs of the second and seventh drivers of the input signals are second inputs of the address, inputs of the fourth and eighth drivers of the input signals are the second control inputs, the combined inputs and outputs of the second and fourth buffer registers are the output signals are the second inputs / outputs of the data block, the outputs of the first and second shapers of input signals are connected to the address inputs of a static random access memory device, the sampling inputs of which are dined with the outputs of the third and fourth input signal conditioners, the outputs of which are connected to the control inputs of the first and second buffer registers, output signal shapers, the second inputs / outputs of which are connected to the data input / outputs of a static random access memory device, the fifth input signal shaper outputs are connected through the first line decoder connected in series, the first drive configuration setting node with the inputs of the third output driver shaper, outputs the sixth input signal shaper is connected to the control inputs of the first line decoder and the third buffer register-shaper of the output signals, the seventh input signal shaper is connected to the outputs through the second line decoder sequentially connected, the second drive configuration setting unit with the inputs of the fourth buffer register-shaper of the output signals, the outputs of the eighth shaper input signals are connected to the control inputs of the second line decoder and the fourth buffer register a-shaper output signals.  3. The controller according to claim 1, characterized in that the non-volatile memory block contains six input signal conditioners, two status decoders, two address decoders, a line decoder, a line sample signal former, a random access memory device based on polarized relays, a signal conditioner words, four buffer register-shapers of the output signal, the register of the recorded word, while the outputs of the first and second buffer registers-shapers of the output signal are combined and are not First data outputs, the second inputs of the first driver of the input signal and the first state decoder, as well as the combined control inputs of the first sixth driver of the input signal are the first control inputs of the unit, the inputs of the second and third drivers of the input signal with the first inputs of the address, the inputs of the fourth and fifth drivers of the input signal with the second address inputs, second inputs of the sixth input driver and second state decoder, as well as the combined third input of the second decoder The state parameters and the input of the signal generator of the recorded word are the second control inputs, the inputs / outputs of the third and fourth buffer registers of the output signal, as well as the register of the recorded word are combined and are the second inputs / outputs of the data, the output of the first driver of the input signal is connected to the first inputs of the first state decoder, line decoder, second state decoder, outputs associated with the control inputs of the third and fourth buffer registers-shapers output of the first signal, the outputs of the first state decoder are connected to the control inputs of the first and second buffer registers-shapers of the output signal, the outputs of the second shaper of the input signal are connected to the inputs of the first address decoder, the combined outputs of the third and fourth shapers of the input signal through series-connected line decoder, sampling signal shaper lines and random-access memory made on polarized relays are connected to the inputs of the second and third buffer reg strov-shapers of the output signal, the outputs of the fifth shaper of the input signal through the second address decoder are connected to the fourth input of the second state decoder, the first outputs of the shaper of the recorded word are connected to the second inputs of the RAM, the second outputs to the inputs of the first and fourth buffer registers of the output signal, the third output of the second state decoder is connected to the input of the register of the recorded word, the outputs of which are connected to the signal shaper for the written word.  4. The controller according to claim 1, characterized in that the first block of sequential input / output of control information contains buffer registers-shapers of the input and output signal, a shaper of the input signal, three nodes of galvanic isolation, two shapers of the output signal, two commutators of communication channels, combined the inputs / outputs of the buffer registers-shapers of the input and output signals are inputs / outputs of the block data, and the outputs of the buffer register-shaper of the input signal are outputs of the parallel output of the control information, inputs of the buffer register-shaper of the output signal by the input of the parallel input of control information, inputs of the shaper of the input signal by the inputs of the control unit, and its outputs are connected to the control inputs of the corresponding buffer registers-shapers of the input and output signals, the outputs of the first and second nodes of galvanic isolation are connected respectively with the inputs of the first and second shapers of the output signal, the outputs of the second shaper of the output signal are connected to the inputs of the first the communication channel switch, the output of which is the output for organizing the communication channels of the first microcomputer, the outputs of the third galvanic isolation node are the outputs intended for connection to the second communication line of the local computer network, and the inputs are connected to the outputs of the second communication channel switch, the input of which is the input to the organization communication channels of the first microcomputer.  5. The controller according to claim 1, characterized in that the second block of sequential input / output of control information contains buffer registers-shapers of input and output signals, two shapers of the input signal, two nodes of galvanic isolation, two shapers of the output signal, two commutators of communication channels, the outputs of the buffer register-driver of the output signal are connected to the inputs of the buffer register-driver of the input signal and are the inputs / outputs of the data block, and the outputs of the buffer register-driver I of the input signal are the output of the parallel output, the input of the buffer register-shaper of the output signal is the input of the parallel input, the inputs of the first driver of the input signal are the control inputs of the unit, and the outputs are connected to the control inputs of the buffer registers of the input and output signals, the inputs of the first galvanic isolation node are the inputs for connecting to the communication line of the local computer network, and the outputs through the second output driver are connected to the inputs of the first switch to communication channels, the outputs of which are outputs for organizing communication channels with a second microcomputer, the outputs of the first driver of the output signal are outputs for connecting to the communication line of the local computer network, and the inputs through the second node of the galvanic isolation and the second switch of communication channels are connected to the outputs of the second driver of the input signal , the inputs of which form the inputs for the organization of communication channels with the second microcomputer.  6. The controller according to claim 1, characterized in that the block of analog controllers contains a register-shaper of the input signal, a buffer register-shaper of the status of analog controllers, a shaper of the input signal, the first limiting unit, an analog speed controller, a unit of normalizing scale amplifiers, a control unit, second restriction node, analog current controller, analog controller control unit, analog controller enable indication unit, analog controller initialization unit, buffer reg outputs the condition shaper of the analog controllers is connected to the inputs of the register of the input signal shaper, which are the inputs / outputs of the unit data, the outputs of the register-shaper of the input signal are connected to the inputs of the control unit of the analog controllers, the first outputs of which are connected to the inputs of the display unit for turning on the analog controllers, the second outputs connected to the inputs of the buffer register-conditioner of the analog controllers, the third outputs to the inputs of the analog speed controller and analog p current regulator, and the control inputs of the control unit of the analog controllers to the first output of the control unit and the output of the initialization unit of the analog controllers, the second output of the control unit is connected to the control input of the buffer register-conditioner of the analog controllers, and the third output to the control input of the buffer register-shaper of the input signal , the outputs of the driver of the input signal to the inputs of the control unit, and the inputs are the control inputs of the unit, the inputs of the analog speed controller, analog the current regulator, the block of normalizing scale amplifiers are the analog inputs of the block, and the outputs of the analog current regulator and the block of normalizing scale amplifiers are the analog outputs of the block, the outputs of the first and second nodes of the limitation are connected respectively to the inputs of the analog speed controller and the analog current regulator, connected in series.  7. The controller according to claim 1, characterized in that the input / output block of analog signals contains three input signal conditioners, a buffer output signal conditioner, a control unit, two galvanic isolation units, an output signal conditioner, an address decoder, an analog-to-digital converter, and digital-to-analog static and dynamic output converters, three normalizing amplifiers, switches of input and output analog signals, inputs of the first driver of the input signal are address inputs, and outputs through p subsequently connected to the first galvanic isolation unit, the output driver and the address decoder are connected to the inputs of the input and output analog signal switches, the control inputs and outputs of which are the analog inputs and outputs of the unit, the inputs of the second input driver are the control inputs of the unit, and the outputs are connected to the inputs control unit, the first output of which is connected to the control inputs of the first and third shapers of the input signal and the buffer shaper output about the signal, the control inputs of the analog-to-digital converter, digital-to-analog converter of dynamic output, digital-to-analog converter of static output are connected to the second, third and fourth outputs of the control unit, the inputs of the third driver of the input signal and the outputs of the buffer driver of the output signal are data input / output, and the outputs of the third the shaper of the input signal and the inputs of the buffer shaper of the output signal through the second node of the galvanic isolation are connected with the corresponding outputs and inputs of an analog-to-digital converter, digital-to-analog converters of dynamic and static output, the input of an analog-to-digital converter through the first normalizing amplifier is connected to the output of the switch of input analog signals, the inputs of which form the unit inputs, the output of the digital-to-analog converter of dynamic output through the second normalizing amplifier is connected with the control input of the switch of the output analog signals, the outputs of which form the outputs of the block, the output of the digital-to-analog conversion The static output generator is connected to the input of the third normalizing amplifier, the output of which forms the output of the unit.

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