RU2037197C1 - Device for solving systems of linear algebraic equations - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has l computing units, P parallel registers, where to P = (n+1)*(n+m) - l*(n+3) and m is number of columns in right-hand part of the system of linear algebraic equations. In addition device has two shift registers having P-bit length, unit of OR gates and two OR gates. Each computing unit has three registers, gate for n-pulse delay, two flip-flops, two groups of flip-flops, multiplier, unit for computing inverse fraction value, subtracter, nine groups of AND gates, four groups of OR gates, five AND gates and two NOT gates. Proposed device solves system having n algebraic equations by means of fixed number of L computing units when l<n. EFFECT: decreased hardware. 2 dwg

Description

 The invention relates to computer technology and can be used in high-performance specialized computers and signal processing devices for solving systems of linear algebraic equations.

 The purpose of the invention is the reduction of hardware costs.

 In FIG. 1 shows a block diagram of a device for solving systems of linear algebraic equations; in FIG. 2 functional diagram of the computing module.

), узел сдвигающих регистров 6_i (i

), первый 7 и второй 8 сдвигающие регистры, блок 9 элементов ИЛИ, первый 10 и второй 11 элементы ИЛИ, информационный выход 12.A device for solving systems of linear algebraic equations (Fig. 1) contains information input 1, first 2 and second 3 mode inputs, sync input 4, computing modules 5 _i (i

), the node of the shift registers 6 _i (i

), the first 7 and second 8 shift registers, block 9 elements OR, the first 10 and second 11 elements OR, information output 12.

), узел 22 вычисления обратной величины числа, умножитель 23, вычитатель 24, первый 25 и второй 26 триггеры, первый 27 и второй 28 блоки триггеров, триггеры 29_i первого блока (i

), триггеры 30_iвторого блока (i

), блоки 31-39 элементов И, блоки 40-43 элементов ИЛИ, элементы И 44-48, элементы НЕ 49, 50, первый 51, второй 52 и третий 53 выходы.Computing module 5 (Fig. 2) contains information input 13, first 14 and second 15 mode inputs, clock input 16, first 17, second 18 and third 19 registers, delay node 20 for n clock cycles, registers 21 _i (i

), node 22 for calculating the reciprocal of the number, multiplier 23, subtractor 24, first 25 and second 26 triggers, first 27 and second 28 trigger blocks, triggers 29 _{i of the} first block (i

), triggers 30 _{i of the} second block (i

), blocks 31-39 of AND elements, blocks 40-43 of OR elements, AND 44-48 elements, elements NOT 49, 50, first 51, second 52 and third 53 outputs.

, j

k

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ⁾= a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ^-1)
a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾= a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ^-1)/a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ⁾, j

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ⁾= a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ^-1), i

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ij}}$ ⁾= a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ij}}$ ^-1)- a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ⁾· a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾ _, i

, j

a $\genfrac{}{}{0ex}{}{\text{(k)}}{\text{n+k}}$ _,j= a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾, j

x_ij= a $\genfrac{}{}{0ex}{}{\text{(n)}}{\text{n+i}}$ _,n+j, i

, j

При описании работы устройства в обозначении а^(k) индекс k в скобках указывает номер рекуррентного шага.The device is based on the Gauss-Jordan method for solving SLAE, which is represented by the following recurrence relations:
a $\genfrac{}{}{0ex}{}{\text{(o}}{\text{ij}}$ ⁾ a _ij , i

, j

k

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ⁾ = a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ^-1)
a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾ = a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ^-1) / a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kk}}$ ⁾ , j

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ⁾ = a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ^-1) , i

a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ij}}$ ⁾ = a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ij}}$ ^-1) - a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{ik}}$ ⁾ · A $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾ _, i

, j

a $\genfrac{}{}{0ex}{}{\text{(k)}}{\text{n + k}}$ _{, j} = a $\genfrac{}{}{0ex}{}{\text{(k}}{\text{kj}}$ ⁾ , j

x _ij = a $\genfrac{}{}{0ex}{}{\text{(n)}}{\text{n + i}}$ _{, n + j} , i

, j

When describing the operation of the device in the notation a ^{(k), the} index k in parentheses indicates the number of the recurrence step.

Computing module 5 performs the following functions:
U ^{j + n + 3} α ^j ;
V ^{j + n + 3} β ^j , where α ^j β ^{j are the} values on the first 14 and second 15 inputs of the computing module mode on the j-th clock;
U ^j , V ^j values on the second 52 and third 53 outputs of the computing module on the j-th clock.

где а^j значение на информационном входе вычислительного модуля на j-м такте;
bj a^j/a^j-m(n+1) при ( α^j β^j ) (1,0)
c^j a^j при ( α^j β^j ) (1,1),
р, m некоторые числа, определяемые алгоритмом;
W^j значение на первом выходе 51 вычислительного модуля на j-м такте.W ^{j + 1}

where a ^{j is the} value at the information input of the computing module on the j-th clock;
bj a ^j / a ^{jm (n + 1)} at (α ^j β ^j ) (1,0)
c ^j a ^j for (α ^j β ^j ) (1,1),
p, m are some numbers determined by the algorithm;
W ^j value at the first output 51 of the computing module on the j-th clock.

 The device operates as follows.

, j

) в моменты времени
t

= i + (n+1)j n-2.At input 1, elements a _ij (i

, j

) at times
t

= i + (n + 1) j n-2.

 The control signals (α β) are fed to the inputs 2 and 3 of the mode as follows: starting from the zero point in time, they are fed sequentially n + 1 times (α β) (1,1), then a group of n + 1 is sent sequentially in the order of listing control signals (α β) (1,0), (0,0), (0,0), (0,1), which is repeated n + m-2 times.

, j

) для случая n/l целое число формируются на выходе 12 устройства в моменты времени
t

= (n/l-1)(n+1)(n+m) + (l-1)(n+3) + i + (n+1)j + 1.The calculation results x _ij (i

, j

) for the case n / l, an integer is formed at the output of the device 12 at time instants
t

= (n / l-1) (n + 1) (n + m) + (l-1) (n + 3) + i + (n + 1) j + 1.

, где

,

и

и матрицы размеров соответственно n' x n', n' x m и n' x m, а n' наименьшее целое из всех чисел, кратных l и больших n, причем матрица

получена добавлением к A₂(n'-n) нулевых строк, а матрица

добавлением к A₁(n'-n) новых строк и столбцов, все элементы которых равны нулю, за исключением лежащих на диагонали, равных единице. При таком расширении первые n строк матрицы

определяют решение Х, а остальные строки нулевые.If n / l is an integer, then we should consider a system of equations of the form

where

,

and

and size matrices, respectively, n 'x n', n 'xm and n' xm, and n 'is the smallest integer of all numbers that are multiples of l and large n, and the matrix

obtained by adding zero rows to A ₂ (n'-n), and the matrix

adding to A ₁ (n'-n) new rows and columns, all elements of which are equal to zero, with the exception of those lying on the diagonal, equal to one. With this extension, the first n rows of the matrix

determine the solution X, and the remaining lines are zero.

Claims (1)

 DEVICE FOR SOLVING SYSTEMS OF LINEAR ALGEBRAIC EQUATIONS, containing l computational modules, where l is an integer, l <n, n is the order of a system of linear algebraic equations, and the first output of the ith computational module, where i 1, l 1, is connected to the information input ( i + 1) th computing module, the first output of the l-th computing module is connected to the output of the device result, the second and third outputs of the i-th computing module are connected respectively to the first and second inputs of the mode of the (i + 1) -th computing module, sync input device The property is connected to the sync inputs of all the computing modules, characterized in that, in order to reduce hardware costs, it contains a node of the shift registers, the first and second shift registers, the block of OR elements, the first and second OR elements, the first information input of the device connected to the first input block of OR elements, the output of which is connected to the information input of the first computing module, the information output of the l-th computing module is connected to the information input of the node of the shift registers, the output the transfer of which is connected to the second input of the block of OR elements, the first and second inputs of the device mode are connected respectively to the first inputs of the first and second OR elements, the outputs of which are connected to the first and second inputs of the mode of the first computing module, the second and third outputs of the l-th computing module are connected respectively, to the information inputs of the first and second shift registers, the outputs of which are connected respectively to the second inputs of the first and second elements OR, the device sync input is connected to odes shift of all shift registers and the node shift registers.