RU2033640C1 - Time signal transmitting and receiving device - Google Patents

Abstract

FIELD: communication engineering. SUBSTANCE: device has in its central part time signal sensor, K time-signal transmitters built around output-signal shaper, signal time advance correction unit, and transceiving unit, time code converter, data signal source, data code converter, three switches, pseudorandom sequence phase keyer, pseudorandom signal generator, counter, signal time advance correction control unit, ambiguity elimination unit, two timers, carrier filtering unit, phased pseudorandom sequence generator, pseudorandom sequence filtering unit, frame synchronizer, two registers, enable signal shaper, synchronism analyzer, and comparison unit; in peripheral part it has in each of K signal receiving and transmitting channels time signal receiver built around transceiver unit, standard generator, two timers, ambiguity elimination unit, carrier filtering unit, phased pseudorandom sequence generator, pseudorandom sequence filtering unit, frame synchronizer, two registers, enable signal shaper, decoder, output signal shaper, time code converter, data signal source, data code converter, switch, pseudorandom sequence phase keyer, pseudorandom sequence generator, carrier phase keyer, synchronism analyzer, and key. EFFECT: enlarged functional capabilities due to transmission of both time signals and service information signals. 15 dwg

Description

 The invention relates to communication technology and can be used to transmit and receive accurate time signals on channels and communication lines with variable parameters.

 The disadvantage of the device selected as a prototype is the lack of the ability to transmit information (for example, service) on the allotted for synchronization communication lines without interrupting the synchronizing stream of information. When transferring service information, it is necessary to interrupt synchronization.

 The purpose of the invention is the expansion of the scope of the device by transmitting both accurate time signals and overhead signals.

 To achieve the goal, a device for transmitting and receiving accurate time signals, containing a time signal sensor on the central part, K time signal transmitters, executed on the output signal shaper, a signal prediction correction unit and a transceiver block, a time code converter, a pseudo-random sequence phase manipulator ( PSP), counter, first and second switches, a control unit for correcting the time anticipation of signals, the first and second chronizers, an ambiguity elimination unit, carrier filtering unit, phased PSP generator, PSP filtering unit, loop synchronizer, register, synchronism analyzer, comparison unit, on the peripheral part of each of the K channels for transmitting and receiving signals, the transceiver unit, the first and second synchronizers, the ambiguity elimination unit, the carrier filtering unit , reference generator, phased PSP generator, PSP filtering unit, cycle synchronizer, key, synchronism analyzer, register, decoder, output driver, carrier phase manipulator, PSP phase manipulator, PSP generator and a time code converter, an information signal source, an information code converter, a resolution signal driver, a second register and a third switch are introduced on the central part, an information signal source, an information code converter, a register on a peripheral part in each of the K transmission and reception channels , resolution driver and switch.

 The essence of the invention lies in the fact that using the blocks introduced into the central and peripheral parts of the device, the structure, volume and purpose of the signals transmitted in both directions along the communication lines are changed. In this case, the frequency of the selected and appropriately anticipated carrier frequency (1 kHz, as in the prototype) is preserved in the new structure of transmitted signals, the duration of the PSP block (1 kHz, as in the prototype), which performs the first phase shift of the carrier frequency and expands the resolution ambiguity, is preserved synchronization to 1 Hz, the speed of the second phase manipulation of the anticipated carrier frequency (already manipulated by the SRP) by the digitization signals of the current time (from 20 to 10 ms / symbol) doubles, expanding ambiguously st synchronization with the 1 Hz to tens of years. This allows you to reduce the time required to transfer the entire block of information about digitization (from 1 s to tens of years 4 bits x 12 decades + 2 bits of "empty" 50 bits) to 0.5 s (relative to 1 s in the prototype). In addition, in the remaining half of the second interval, phase manipulation of the same (already manipulated by the PSP signals and pre-emitted) carrier frequency by overhead signals is carried out. This allows not only transmitting 0.5 s 10 ms of 50 bits of service information on the same line, but not interrupting the flow of time synchronizing information, and not changing the phase position of the edges of the carrier frequency, since each bit of service information is superimposed on the carrier frequency by the second phase manipulation whose leading edge does not change with respect to the half-second interval in which information on the digitization of the current time was transmitted (which is also unchanged throughout the entire second interval). The introduced features in the known devices with the indicated purpose were not found, which indicates the ratio of the proposed technical solution to the criterion of "significant differences".

 In FIG. 1 is a functional diagram of a device for transmitting and receiving accurate time signals; figure 2 diagram of the information-time line-up of signals transmitted in the communication line; figure 3 diagram of the operation of the device; figure 4 diagram of the control unit correction of the lead time of the signals; in Fig.5 block diagram correction of the lead time of the signal; Fig.6 diagram of the driver of the output signals of the transmitter of the time signals; in FIG. 7 block diagram of the transceiver; on Fig a synchronizer circuit; Fig.9 block diagram of the disambiguation; 10 and 11 are diagrams of the operation of the disambiguation unit; on Fig shows a diagram of a phased generator SRP; 13 and 14 show diagrams of the first and second registers; on Fig presents a diagram of the analyzer synchronism channel transmission and reception of signals.

A device for transmitting and receiving accurate time signals (Fig. 1) comprises a time signal sensor 1, transmitters 2 ₁ .2 _K time signals on the central part, performed on the output signal shaper 3, the signal anticipatory correction unit 4, the transceiver unit 5, a converter 6 time codes, a source 7 of information signals, an information code converter 8, a third switch 9, a PSP phase manipulator 10, a PSP generator 11, a counter 12, first 13 and second 14 switches, a signal anticipation correction control unit 15, the first 16 and second 17 chroniclers, block 18 disambiguation, block 19 filtering carrier, phased generator 20 SRP, block 21 filtering SRP, clock synchronizer 22, the first register 23, the driver 24 of the enable signal, the second register 25, the output of which is the bus 26 code information, synchronism analyzer 27, comparison unit 28, lines 29 ₁ .29 _{K of} communication, on the peripheral part in each signal transmission and reception channel, receiver 30 ₁ .30 _{K of} time signals made on transceiver unit 31, reference generator 32, first 33 and second 34 chronizer x, ambiguity block 35, carrier filtering unit 36, phased OSS generator 37, OSS filtering unit 38, clock synchronizer 39, first 40 and second 41 registers, enable signal driver 42, decoder 43, output signal generator 44, time code converter 45 , information signal source 46, information code converter 47, switch 48, PSP phase manipulator 49, SRP generator 50, carrier phase manipulator 51, synchronism analyzer 52, key 53, control signal and frequency bus 54 (information outputs group), bus 55 of the current time code (information outputs of the second group) and information bus 56 (information outputs of the third group).

Block 15 control correction of the lead time of the signals (figure 4) contains information channels 57 ₁ .57 _K , each of which is made on the first 58 and second 59 elements And, phase discriminator 60, element OR 61, decoder 62 and analyzer 63 mismatch.

 Block 4 correction of the lead time of the signals (figure 5) contains two dynamic RS-flip-flops 64 and 65, two D-flip-flops 66 and 67, an element OR 68, elements And 69 and 70, as well as series-connected counter 71 with a variable division ratio and counter 72 with a constant division factor.

 Shaper 3 output signals (Fig.6) contains a D-trigger 73 and the adder 74 modulo two.

Blocks 5 ₁ .5 _K , 31 transceivers contain (Fig. 7) an amplifier 75, a resistor 76, a balanced transformer 77 and an amplifier-limiter 78.

 The chronizers 16, 17, 33, 34 (Fig. 8) contain a phase shifter 79, a frequency divider 80, a mismatch analyzer 81, a counter 82, a phase discriminator 83, a detector 84, a threshold device 85, and an And 86 element.

 The disambiguation blocks 18, 35 (Fig. 9) comprise a delay element 87, a D-trigger 88, and an adder 89 modulo two.

 Phased oscillators 20, 37 SRP (Fig) contain a driver 90 of the switching pulse, the first element OR 91, dynamic RS-trigger 92, switch 93, generator 94 SRP, the second element OR 95, counter 96, decoder 97, delay element 98, a second delay element 99, a first AND element 100, a second AND element 101, a multivibrator 102, a reversible counter 103, a threshold element 104, and a D-trigger 105.

 The first registers 23, 40 (FIG. 13) comprise a counter 106, a decoder 107, a delay element 108, first 109 and second 110 registers.

 The second registers 25, 41 (FIG. 14) comprise a register 111 and a key 112.

 The synchronism analyzer 52 (Fig. 15) comprises a counter 113, a decoder 114, and a D-trigger 115.

 The device operates as follows.

Based on the source of 7 information signals and the sensor 1 of the time signals, K transmitters 2 ₁ .2 _K time signals carry out continuous transmission of signals along K lines 29 ₁ .29 _{K of} communication with the corresponding K receivers 30 ₁ .30 _{K of} time signals. The information signals and time signals transmitted on each communication line represent the carrier frequency with double phase shift keying: signals of the SRP (selected constant length) and signals of a serial code of the information of the source 7 information signals or digitization of the current time of the sensor 1 of the time signals. Moreover, each period of the transmitted carrier frequency (both subjected to phase manipulation, and not subjected) is transmitted to each communication line with a temporary lead relative to the signals of the sensor 1, equal to the propagation time on the corresponding communication line. In this case, the signals arriving at the input of each receiver 30 are in phase with the signals of the sensor 1 and are suitable, after appropriate processing for removing phase manipulation, to directly synchronize the receivers 30 with an ambiguity resolution up to the period of the carrier frequency. Isolation of the received bandwidth from the received signal makes it possible to expand the resolved ambiguity of synchronization of the receivers 30 from the period of the carrier frequency by the duration of the block of the memory bandwidth (for example, 1 s). Isolation from the received signal of a serial digitization code of the current time of sensor 1 makes it possible to expand the resolvable ambiguity of synchronization of receivers due to the duration of the memory block to the lowest frequency part of the transmitted digitization of the current time (for example, up to tens of years).

Correction of temporary lead by appropriate transmitters 2 ₁ . 2 _K signals transmitted over the 29 ₁ .29 _K lines of communication are carried out according to the results of their comparison with the measured ones (based on the reverse transmission from the corresponding receivers 30 ₁ .30 _K along the same lines 29 ₁ .29 _{K of the} connection to the transmitters 2 _1. 2 _K ) at times of distribution along the corresponding lines 29 ₁ .29 _{K of} communication. Moreover, such correction of the introduced lead-time lead is carried out sequentially in each transmitter 2 ₁ .2 _K and is cyclically repeated, for example, the lead-time correction introduced into the signal of the first transmitter, then the second, third, etc. is corrected. then K-th, again the first, second, etc.

The time interval allotted for the correction of the time lead introduced into the signal transmitted by each transmitter 2, i.e. for input into synchronism of one of the receivers 30, it is set by the counter 12. This counter, using the signals of the sensor 1 (for example, 1 Hz), generates a control address code for the control unit 15 of the correction of the time-ahead signals, the first 13 and second 14 switches, taken, for example , from the last (highest) bits of counter 12. The signal of this code appears after a time interval exceeding the time required to enter into synchronism any (one) receiver 30 ₁ .30 _K time signals connected to transmitters 2 ₁ .2 _K time signals with p corresponding power line ₂₉ January .29 _K communications. Such a time interval may be, for example, five minutes.

As a result of the impact on the control unit 15 of the correction of the lead time of the signals and the switches 13, 14 of the control code from the counter 12 during each specified time interval in the Central part of the synchronization device, the following connections are organized. The control signals generated by the signal prediction correction control unit 15 for correcting the time anticipation introduced by one of the transmitters 2 ₁ .2 _K into the transmitted signal are supplied through one of the K pairs of inputs of the signal anticipatory correction control unit to the signal anticipatory correction unit 4 only this transmitter, the inputs of the other blocks of the correction of the lead of the signals are grounded by the control unit correction of the lead of the signals. The first information input of the signal prediction correction control unit 15 by means of the first switch 13 is connected to the output of that signal anticipation correction unit 4, the operation of which is controlled by the signal anticipatory correction control unit for a given period of time. Hronizatora input of the first filter 16 and the first carrier unit 19 input via the second switch 14 is connected to the output of May ₁ .5 _{To a} transceiver, which is conducted through the pass line January ₂₉ .29 _K communication signals developed temporary correction unit 4 feedforward signals, controlled in this period of time, the block 15 controls the correction of the lead time of the signals.

Next, we consider the operation of the system for one of the specified time intervals for the case when the block 15 controls the correction of the lead of the signals controls the last, K-m, the block 4 of the correction of the lead of the signals, which corresponds to the synchronization (correction introduced time lead) of the last, the Kth , a 30 _K receiver connected to a 2 _K transmitter of time signals via a 29 _K communication line.

The SRP generator 11, relying on the clock, for example 5 MHz, and low-frequency setting, for example 1 Hz, sensor signals 1, generates the SRP, for example, with a period of 1 s and the number of elements 1000, which corresponds to a clock frequency of output of the SRP elements of 1 kHz. Such a SRP with the number of elements 1000 can be obtained, for example, by forcing the SRP generator 11 to its initial state with a 1 Hz signal, which allows shortening the duration of the total SRP (the number of elements is described by the ratio of 2 ^P -1 and at P = 10 is 1023).

 The clock frequency of the output of the elements of the SRP, equal to 1 kHz, is selected as the average frequency of the amplitude-frequency characteristic (AFC) of the lowest frequency communication channel used for transmitting time signals, for example, based on a cable of the TZB type. The SRP period of 1 s is chosen to coincide with the rate of change of the current time code (for example, from seconds to hundreds of years).

 Thus formed PSP (Fig.3b) is fed to the first input of the manipulator 10 of the PSP phase, the second input of which in the form of a serial code is supplied through the switch 9, for example, in the first 0.5 s (Fig.2) information from the information code converter 8 , and, for example, in the second 0.5 s, digitization of the current time from the converter 6 of the time code (figa). Since the principles of signal transmission in the first and second 0.5 s are identical, then consider the operation of the device in the second 0.5 s.

 The converter 6 of the time code, according to the 1 Hz signal, reads out the digitization of the current time from the sensor 1 of the time signals (and the information code from the converter 8 of the information code), for example, in a parallel-binary code of twelve digits of units and tens of seconds, minutes, hours, days, months, years, as well as the sequential issuance of this code with a discharge frequency of bits of 100 Hz. Therefore, at the output of the manipulator 10 of the phase of the memory bandwidth (Fig.3c), which is, for example, an adder modulo two, forty-eight (since the digitization is represented by twelve digits, characterized by a four-digit binary decimal code), segments of the memory bandwidth of 10 ms are manipulated by phase depending on the content of digitization bits. The last two ten-millisecond segments of the PSP (the 99th and 100th in each second interval) are not manipulated (all other segments from the 1st to the 98th are manipulated).

It should be noted that all of these preliminary transformations are carried out synchronously with the signals of the sensor 1 and are intended to compose the structure of the signals transmitted via lines 29 ₁ .29 _To communicate signals with the aim of laying in them only those elements of the signal structure that are in the receivers 30 ₁ . 30 _K time signals can be used to expand the limits of the allowed synchronization of their output signal shapers. Such elements are the memory bandwidth, which, when processed in receivers 30 ₁ .30 _{K, is} used to synchronize the mid-frequency part of the shapers of 44 output signals (phasing of signals extracted from the frequency bandwidth 1 Hz), a serial code for digitizing the current time, which when received in receivers 30 ₁ .30 _K It is used to synchronize the low-frequency part of the output signal conditioners (phasing by recording the digitization information received from the communication line in case of difference from the existing one). This arrangement of the signal structure of the manipulator 10 is carried out simultaneously to prepare for transmission on all communication lines 29 ₁ .29 _K , on receivers 30 ₁ .30 _K, and, in particular, K-th, the synchronization process of which is described for the agreed time interval specified by the counter 12.

The signal anticipatory correction unit 4 carries out (FIG. 3d) in conjunction with FIG. 3a. the formation by commands from the block 15 controls the correction of the lead time signals of the necessary lead time relative to the sensor signals, selected accordingly, the carrier frequency. This carrier should be no higher than the upper frequency frequency response of the lines 29 ₁ .29 _K communication, as well as a multiple and not lower than the frequency of the output of the elements of the SRP generator 11 (1 kHz). The latter is conditionally superimposed because in the driver 3 of the signals from the manipulator 10, phase manipulation (second) is carried out by the carrier control unit 4 prepared, and during phase manipulation in direct or manipulated (inverse) form, only every whole period can be transmitted, and not part of it. For simplicity, in Fig. 3, the carrier frequency is selected (as an acceptable limiting case) equal to the clock frequency (1 kHz) of the output of the SRP elements (compare Figs. 3b and 3d).

 The functional composition and operation of the signal pre-correction correction unit 4 and the signal pre-correction correction control unit 15 interacting with it are described in detail later after the signal transmission through the corresponding communication lines 29 is completed both from the transmitter 2 to the receiver 30 and back to the transmitter 2, as soon as in this case, in the control unit of the correction of the time anticipation of signals, it is possible to determine the propagation time of the signals along the communication line and, accordingly, the development ravlyaetsya correction signals pledged delay time.

 Therefore, it is believed that the carrier (Fig. 3d) formed in block 4 for temporarily anticipating the signals so far has an arbitrary temporal anticipation relative to the signals of sensor 1 (Fig. 3a, c), which is quite consistent with the situation when the real synchronization system is put into synchronism. This carrier is fed to the first input of the shaper 3 of the output signals, to the second input of which the output signal of the PSP phase manipulator is received (Fig.3c).

 In the shaper 3 of the output signals with the help of the D-flip-flop 73 (Fig.6), the output signal of the manipulator (Fig.3c) is temporarily linked to the clocks (with a positive edge arriving at the clock input of the trigger 73) of the anticipated carrier (Fig.3g). The output signal of the flip-flops 73 is used as a manipulation of the carrier signal, which is anticipated relative to the signals of the sensor 1. Phase manipulation of the anticipated carrier is carried out using an adder 74 modulo two, the output signal of which (FIG. 3h) is the output signal for driver 3. This signal without additional transformations is suitable for direct (after necessary amplification) transmission to the communication line, since it is practically not affected spurious distortion at the reception of its own constant component, depending on the transmitted information about digitizing the current time of the sensor 1. The absence of such spurious distortion when receiving a signal about the constant component is explained by the fact that after passing through the communication line (usually connected to the source and consumer using matching balanced transformers), the received signal (as a set of whole periods of direct and inverse carrier frequencies of the meander shape) is almost symmetrical with respect to the zero potential. The symmetry caused by the chaotic alternation of direct and inverse periods of the carrier in the signal is random in nature and is easily compiled by averaging the phase of the received signal. The signal from the output of the shaper 3 enters through the block 5 of the transceiver only in the communication line 29.

 To clarify the last statement, the operation of the transceiver unit is considered (Fig. 7), since this is necessary to illustrate the possibility of organizing simultaneous continuous bidirectional transmission of time signals along the communication line 29 from both transmitter 2 to receiver 30 and in the opposite direction with unambiguous separation of signal flows .

Transmitter-transmitter unit 5 of transmitter 2 (as well as receiver-transceiver unit 31 of receiver 30) operates so that the signals supplied to its input can only get through its bi-directional input-output to communication line 29, and the signals coming from communication line 29 to bi-directional input-output can only go to the output of transceiver unit 5 (31). This happens because the current of the signal passing through the amplifier 75 and supplied to the middle tap of the primary winding of the transformer 77 branches out equally (if the ballast resistance rating is equal to 76 to the wave impedance of the communication line ρBar _hp ) into the communication line 29 and the resistor 76, without getting to the input of the amplifier-limiter 78 and, accordingly, to the output of the transceiver unit 5, and the signal that came from the communication line to the bidirectional input-output of unit 5 passes through the following circuit: the first (in Fig. 7) half of the primary winding of transformer 77, low in Khodnev resistance 76, and therefore only transformed to the input of the amplifier-limiter 78, and hence only the output unit 5.

Thus, the signal generated in the shaper 3 output through transceiver unit 5 enters the communication line 29 via the _camshaft propagation time T (at the end of input in synchronism feedforward equal time) comes to the transceiving unit 31 of the receiver 30. The output unit 31 received transceiving from the communication line, the signal (Fig. 3f) is supplied to the first chroniser 33 and the filtering block of the carrier of the receiver 30 for use for synchronization. When the receiver 30 is synchronized, several stages of conversion of the signal arriving at its input are carried out in it. The first stage, implemented using the first 33, second 34 chronizers, block 35 disambiguation and block 36 filtering the carrier, allows you to prepare the necessary signals for synchronization of the shaper 44 of the output signals with an ambiguity resolution to the period of the carrier frequency. Consistently consider the purpose, composition and operation of blocks 33.36.

раз меньшей фазовой дрожью, чем принимаемый из линии связи сигнал, где п число используемых при подстройке фазы фронтов принятых из линии 29 связи импульсов. Указанное уменьшение фазовой дрожи происходит потому, что обязательным элементом при выработке управляющих сигналов в цепях фазовой автоподстройки является интегратор (например, реверсивный счетчик 82), который и позволяет достичь такого усредняющего действия по отношению к фазе принимаемого сигнала.The first 33 and second 34 chronizers carry out the formation (based on the signal of the local generator 32) of a frequency equal to the carrier frequency (equal, in turn, to the repetition rate of the SRP elements), as well as its phase synchronization with phase-shifted signals supplied to their inputs. This operation is aimed at averaging the phases of the signal received from the communication line 29 and is necessary because when the pulses constituting the signal (in the described case, a phase-shifted meander) pass along the communication line, their fronts are "delayed" due to the limited bandwidth and the length of the communication line, and also receive distortion under the influence of noise. The information extracted (for example, by the limiter amplifier 78 in block 5 (or 31) from the received signal (the temporary position of the edges) therefore contains the so-called phase jitter, which is unacceptable for temporary systems. To eliminate it, pulses are generated from the signals of local generators 32, which follow with the frequency received (or a multiple of it) and carry out their phase self-tuning to the center of the phase jitter zone. The classical scheme of such a phase-locked loop (blocks 79.83, Fig. 8) constitutes the main functional content of the first 33 and second 34 chroniclers. The frequency they selected (divider output 80) has approximately

times less phase jitter than the signal received from the communication line, where n is the number of fronts used in phase adjustment of the pulses received from the communication line 29. The indicated decrease in phase jitter occurs because an obligatory element in the development of control signals in the phase locked loops is an integrator (for example, a counter 82), which makes it possible to achieve such an averaging action with respect to the phase of the received signal.

 The achievement of the desired synchronism during phase-locked loop is controlled by the mismatch analyzer 81, counting the number of control signals for the phase shifter 79 for a selected, for example, second time interval. If the number of control signals per second does not exceed a certain value, which indicates the end of the adjustment, the output of the analyzer 81 is allocated a signal that allows the use of the signal from the output of the frequency divider 80. It is important that this signal of the mismatch analyzer can reach the inhibitor inhibit output 33, 34 only through the And 86 element. The signal from the threshold device 85 is supplied to the second input of this And element, which, together with the peak detector 84, monitors the presence of the input signal of the corresponding chronicizer 33, 34 .

 However, due to the presence of phase manipulation in the input signal of the chronometers 33, 34 (namely, this case is considered), the phase adjustment of the generated signal that they carry out can be carried out with ambiguity (erroneous phase shift) to half the period of the highest frequency in the phase-shifted input signal. In relation to the first chroniser 33 (as a phase-locked loop system, with the aim of phasing, for example, the positive front of the signal it generates, for example, with the positive front of the input signal) this means that it can find this front (Fig.3e) as at the beginning of every one-millisecond interval (Fig.3k), and in its middle (Fig. 3g). Therefore, both stable states (Fig.3k or 3g) of the chroniser 33 are equally probable, and to which of them (hereinafter tightly held) the chroniser 33 depends on which periods of the carrier frequency in the received signal for the second averaging interval contained more: direct or manipulated (inverse).

 It is assumed that the carrier frequency signal generated by the chroniser 33 occupies a stable position (Fig. 3g), in which the positive front of the carrier formed by it falls in the middle of each one millisecond interval. This position allows us to illustrate the impossibility of filtering from the received carrier frequency signal using block 36 (as the first stage of processing the received signal), as well as ways to eliminate the specified ambiguity using blocks 34, 35. It is also believed that the output signal (Fig. 3g) of the first chroniser 33 through the disambiguation unit 35 is transmitted to the second input of the carrier filtering unit 36, to the other input of which a received signal is supplied (Fig. 3f) from the output of the transceiver unit 31.

 Block 36, which is an adder modulo two, is designed to filter from the received signal of the carrier frequency. The signal generated by him in this case (shown in FIG. 3h) should be a memory bandwidth, ten-millisecond segments, which are manipulated by the source information code 7 or the current time digitization code of sensor 1 (as in FIG. 3c). However, from the comparison (Figs. 3c and 3c), it is obvious that due to the presence in the output of the first chroniser 33 of unresolved ambiguity equal to half the period of the carrier frequency, the output signal of block 36 is the inverse of the signal (in Fig. 3c). Further use of the received signal (Fig.3z) for synchronization of the receivers 30 is not acceptable until the phase ambiguity of the signal at the output of the first chroniser 33 is eliminated.

 Block 36 is intended for its elimination, the implementation of which uses those of previously agreed circumstances that, when generating a signal transmitted to the corresponding communication line in direct or manipulated form, only a whole period of the carrier frequency can be transmitted. This means that at the moments of a possible phase manipulation of the corresponding whole periods of the carrier frequency by the PSP signals (Fig. 3b, c, d), for example, positive fronts that have not undergone the manipulation of the carrier frequency necessarily occur. The same property (compare fig.3b, c and fig.3z with fig.3d) has the signal of the carrier filtering unit 36, if the carrier frequency in the first chroniser 33 is restored with the specified ambiguity (fig.3zh).

 The output signal of the carrier filtering unit 36 is supplied to the second chroniser 34, which generates (Fig. 3i) a frequency equal to the frequency of the SRP elements (in this case, it is equal to the carrier frequency). The property of the output signal of the second chroniser 34 (Fig. 3i) is its binding, for example, of a positive front to the moments of changing the elements of the memory bandwidth (compare Fig. 3i in the "binding" to any front, Fig. 3b, c, h, i.e. phase the ambiguity of the processing of the second chronicler does not matter). Therefore, the temporary position of the positive edges in the output signal of the second chroniser 34 can be used as a pointer to the desired desired temporary position of the positive edges in the carrier frequency signal generated by the first chroniser 33 and supplied to the second input of the carrier filtering block 36 through the ambiguity block 35.

 This implies the implementation (Fig. 9) and the algorithm of the disambiguation block, which direct (Fig. 10) transfers the output signal of the first chroniser 33 to the input of the carrier filtering block 36 if there are positive edges in the signals generated by both the first 33 and the second 34 chroniclers, coincide in time; inverse, i.e. with a shift of 0.5 periods, (11) transmitting the output signal of the first 33 chronizer to the input of the carrier filtering unit 36 if the positive edges in the signals generated by both the first 33 and the second 34 chronometers do not coincide in time.

 Therefore, the input of the carrier filtering unit 36 using the block 35 is fed the restored carrier frequency with the disambiguation removed (the transition from fig.3zh to fig.3k); the carrier filtering unit carries out the correct selection from the received signal of the SRP with ten-millisecond segments manipulated by the information code of the sensor 7 or the code for digitizing the current time of the sensor 1 (Fig.3l as an addition product modulo two, Fig.3e and 3k in comparison with Fig.3c); the second chroniser 34 generates a signal of the frequency of changing the elements of the SRP (1 kHz), which does not change the operating mode of the ambiguity block 35 (coincidence of the edges in Figs. 3k and 3m), and also enters the first input of the output signal shaper 44 for use in the latter with the aim of its synchronization with an ambiguity resolution of up to 1 ns.

 The output signals of the carrier filtering unit 36 (extracted from the received PSP signal with phase-manipulated source information code 7 or 10-second digit code for digitizing the current time of the sensor 1, Fig. 3l) and the second chroniser 34 (clock frequency of the SRP elements equal to the carrier frequency 1 kHz , fig.3n) are supplied to the corresponding inputs of the PSP generator 37 (Fig. 12), which performs the formation of the SRP, which is a copy of the SRP generated by the SRP generator 11 and used in the receiver 30 of the time signals for allocation of the received clock signal of frequency 1 Hz signal, information about the information source code 7 and digitizing time of the current sensor 1; the phasing of the generated PSP with the PSP generated by the generator 11, without which the indicated extraction of a frequency signal of 1 Hz, a code of information of the source 7, and digitization of the current time of the sensor 1 is impossible; issuing the generated memory bandwidth in the form of both parallel and serial codes; the issuance of a ban signal to the shaper 44 of the output signal and the shaper 42 to enable the readout of information of the receiver 30 until the phasing of the generated PSP with the PSP generated by the generator 11.

 Consider the operation of a phased generator PSP 37 in cooperation with a cyclic synchronizer 39 and a filtering block 38 SRP (figure 1, 12), since it is with these blocks that the second stage of conversion of the signals received by the receiver 30 is carried out.

 After power is turned on, the pulse front from the shaper 9 is set to a single state through the OR element 91, the trigger 92 and through the OR element 95 to the initial state, for example, as in the transmitter 2 of the time signals, 100.00 (from left to right in Fig. 12) generator register 94 PSP. Under the influence of a single potential, the output of trigger 92 closes the feedback of the PSP generator 94 to its information D input through the X channel of the switch 93. As pulses (1 kHz) receive pulses from the second chroniser 34 at the clock input of the generated generator 37, the generator 37 ( using the register of the generator 94 and closed feedback) generates the SRP, the law of formation of which is similar to the law of the formation of the SRP in the generator 11. The difference between the generator 37 SRP in the receiver 30 consists only in the fact that in addition to the main ten digits its register RA (for the formation of the SRP with a length of 1023, and in our case 1000, pulses, their number is ten with feedback from the seventh and tenth digits modulo two) one additional (eleventh) is provided. The appearance of single characters of the generated memory bandwidth at the output of this additional discharge does not lead to switching of the switch 93, since the single state of the trigger 92 does not change.

 The PSP formed by the phased generator 37 in sequential form (from the main output) is fed to the input of the PSP filtering unit 38, the other input of which from the output of the carrier filtering unit 36 is allocated from the received from the communication line 29 PSP with ten millisecond segments and phase-manipulated source information code 7 and digitizing the current time of sensor 1.

 If the PSP generated by the generator 37 is in phase with the PSP generated by the generator 11, then at the output of the PSP filtering unit 38, which, like the carrier filtering unit 36, is an adder modulo two, a sequential code of source 7 information and digitization of the current time of sensor 1 should be allocated (the frequency of the change of characters of this code is 100 Hz). If the indicated memory bandwidths are not phased, then the signal at the output of the memory bandwidth block is random and is not suitable for further processing. To determine whether or not the desired phase matching of the local PSP and the PSP formed in the generator 11 is achieved, the output signal of the PSP filtering unit 38 is again fed to the phased PSP generator 37, in which the corresponding analysis is performed.

 A sign for making a conclusion on the achievement of the necessary synchronism is the following circumstance. If synchronism is achieved (Fig.3p in comparison with Fig.3b), then during each of the ten-millisecond intervals at the output of the PSP filtering block, the generated signal (Fig.3p as a result of modulo two addition, Fig.3l and 3p) is unchanged (or logical “0”, or logical “1”), since the frequency of changing the digits of the digitization code of the current time is 100 Hz. If during the specified ten-millisecond interval a signal change is registered at the output of the PSP filtering unit (Fig.3o as a result of modulo two additions, Fig.3l and 3n), then there is no necessary synchronism (Fig.3n in comparison with Fig.3b) and the corresponding impact on the generator 37 PSP.

 Phased generator PSP 37 checks the phasing of the generated PSP according to the specified algorithm using elements 96.105. Among them, the main ones are two counters: a counter 96 with a division factor of 10 to form a ten-millisecond time interval (the necessary time position of the beginning and end of the time intervals formed by it can be set either randomly or by a signal from the cyclic synchronizer 39, which determines the end of the signal 1 Hz 1000 an elementary generated memory bandwidth synchronous with the generated memory bandwidth generator 11; a reversible counter 103 for counting the number of millisecond intervals per unit and zero state digitization of the selected signal in each desyatimillisekundnom range specified by the counter 96, i.e., counting mode: the summation or subtraction of the counter varies depending on the content (logic "1" or logical "0") of the signal output from the filtering unit 38 SRP.

 Therefore, if the reverse counter 103 within a certain time interval 96 manages to reach the state "+10" or "-10", then a command must be formed for the rephasing of the generator 37 SRP.

 The state of the reversible counter 103 is analyzed by a threshold element 104 and recorded by a D-flip-flop 105, to the clock input of which at the end of a ten-millisecond interval a recording pulse is generated, formed by the decoder 97 and the delay element 98, as well as the I 100 element, which was opened by the signal from the inverted output of the multivibrator 102. If at the output of trigger 105, a logical “0” signal appears, this means that synchronism is achieved and the ban on further use of the selected digitization signal is removed (this signal is fed to ovatelyu output signal 44). If the logic 1 signal appears at the output of the trigger 105, then this is recognized as a command for further phasing of the PSP generator 37, which is performed as follows.

 If the result of the analysis of phasing of the memory bandwidth is unsatisfactory, then simultaneously with the appearance of a logical "1" signal, a pulse is generated at the output of the trigger 105 at the output of the element And 101, which starts the multivibrator 102, which generates a pulse lasting 25-30 ns and thereby prohibiting the removal of the protection signal from the output a trigger 105 in the next ten millisecond interval by closing the AND element 100 with a multivibrator 102; resetting the trigger 92, disconnecting the feedback from the generator 37 PSP and connecting the D-input of its register through the Y-channel of the switch 93 to the output of the block 36 filtering the carrier; installation in the initial state (10.00) of the register of the generator 94 PSP. The implementation of the agreed switching circuits and the provisions of the initial conditions allow you to go to the phasing generated by the generator 37 SRP with SRP formed by the generator 11.

 Phasing of the generated PSP is realized by using one of the properties of the PSP, which consists in the fact that the sequence of occurrence of elements (units and zeros) of the PSP at each bit of the register of the generator of the PSP generator is strictly constant and depends only on the architecture of the PSP generator and the initial state of this generator. Therefore, if we take two n-bit identical, working from different and in-phase clock frequencies of the PSP generator and equalize the states of all n bits of the registers that form these generators (at least in one cycle of their operation), then in the future these generators independently form the same and common-mode PSP.

 It should be noted that (due to the presence in the output of the filtering block 36 of the phase-shift keying carrier of a ten-millisecond segment received from the SRP communication line) the listed actions for synchronization are sufficient only when (randomly) the symbols of the received SRP are sequentially introduced into the generator 37, belonging to the segment (10 ms). If the SRP elements are introduced into the generator 37 from a segment with phase manipulation or for the junction of segments with or without manipulation, then the phasing of the SRP generator does not occur.

 Verification of the achievement of synchronization with the generation (if necessary) of the rephasing command is carried out using the elements 96.105 in the next twenty-millisecond interval (see operation of the multivibrator 102). If there is no synchronism, then a new forced record of the received SRP is made in the register of the generator 94, generator 37, then check, etc. trial and error to achieve synchronism. Synchronism can be achieved at any time, although its most likely achievement is at the end of each second interval, since the ten-millisecond segment of the SRP received from the communication line 29 does not contain phase manipulation (see the operation of the phase shifter of the SRP transmitter 2 time signals for the layout of the transmitted signal).

 This ends the second stage of converting the received signal receivers 30, as a result of which the phasing process of the phased generator PSP 37 ends (FIG. 3p), at the output of the SRP filtering unit 38, a sequential code of source information 7 and digitization of the current time of sensor 1 are allocated (FIG. 3p) and, at the output of the cyclic synchronizer 39, a frequency signal of 1 Hz is synchronized with a similar signal of sensor 1.

 At the third stage of signal conversion in the receiver 30, the serial code is converted from the output of the PSP filtering unit 38 to parallel using the first 40 and second 41 registers (Figs. 13 and 14), which operate as follows.

 The signal from the cyclic synchronizer 39 (Figs. 1, 13), which selects a frequency signal of 1 Hz (the length of the PSP cycle) from the PSP generated by the generator 37, sets the counter 106 to its initial state. Pulses with the repetition rate of the PSP elements arrive at the clock input of this counter (1 kHz) from block 36, the division of which generates clock pulses for receiving into the register 109 a sequential code of source information 7 and digitizing the current time of sensor 1 (frequency of changing bits 100 Hz, the number of bits for receiving 50 bits of information and 48 bits of digitization using a four-digit binary decimal code), an impulse (using the decoder 107 based on the code output of the counter 106 and the race eliminating element 108), the temporary position of which corresponds to the end of reception by the register 109, the end of reception by the register 108 of the last 98th digit of the serial information code source 7 and digitizing the current time of sensor 1. Therefore, the information and digitization code of register 110 is converted to parallel.

 The signals from the first register 40 from the element 108 (FIG. 13) and from the information read permission 42 (FIG. 1), which upon the arrival of the inhibit signals from the chronizers 33, 34, from the phasing generator 37 of the SRP generates a signal, are sent to the second register 41 , on the key 112 (Fig.14). The key 112 begins to give signals for recording information in the register 111. If this signal is generated, information is recorded in the register 111, in which the information D-inputs are connected to the first 50 outputs of the first register 40.

 At the end of all the stages of the conversion of the signals received in the receiver 30, the process of tuning the output driver 44, which is a controlled channel for dividing the frequency, to the signal received on the communication line 29, begins. From the former 44 are removed the prohibition signals generated by the first 33 and second 34 chronizers and generated by the PSP generator. If all prohibition signals are removed, then this means the resolution of the synchronization of the driver 44, which occurs as follows.

 Exact adjustment with an ambiguity resolution within 1 ms is realized by phase-locked loop of the high-frequency part of the frequency division in the driver 44 to the output signal of the second chroniser 34 (Fig. 3 m), synchronous with the sensor signal 1. An extension of the resolved ambiguity of adjustment from 1 ms to 1 s is realized the synchronization of the mid-frequency part (from 1 kHz to 1 Hz) of the frequency divider in the driver 44 by installing it with a 1 Hz signal from the output of the cyclic synchronizer 39. Further expansion of the resolved ambiguity under from 1 s to tens of years of construction is implemented due to the forced recording in the low-frequency part (below 1 Hz) of the frequency divider of the driver 44 of the adopted digitization of the current time of sensor 1 (register output 40 from the 51st to 98th discharge) if it differs from the generated shaper 44. Comparison of the digitization of the current time at the end of every second (after receiving from the communication line 29 all digits of the digitization code of the sensor 1 by register 40 according to the signal from the delay element 108 entering it, it is carried out by the decoder 43.

 Upon completion of the adjustment of the output signals of the driver 44 to the signal received from the communication line 29 (with arbitrary lead so far) using the receiver synchronism analyzer 52, a permission is generated for the reverse transmission of signals from the receiver 30 to the transmitter in the synchronization center, which is necessary for the corresponding correction of the transmitter introduced into the signal 2 time lead before alignment with the temporary propagation of signals over the communication line. The analyzer 52 (Fig. 15) produces this resolution as follows.

 Using the counter 113, set by the signal from the cyclic synchronizer 39, and the decoder 114, a time strobe is formed characterizing the phase position of the 1 Hz signal extracted from the signal received from the communication line 29. If the 1 Hz signal from the output of the driver 44, applied to the clock input of the D-trigger 115, does not "fall" into this time strobe, then the output of the D-trigger 115 receives a logical "0" signal, which indicates the incomplete tuning of the driver 44. Otherwise In this case, the adjustment of the shaper 44 is already completed. Therefore, the logic signal “1” from the analyzer 52 is fed to the control input of the key 53 (Fig. 1), allowing reverse transmission from the receiver 30 to the transmitter 2 of the synchronization center prepared by the blocks 45.51 of the signal.

 An analysis of the quality of the acceptance of information on the digitization of the current time by the driver 44 for issuing permission for the reverse transmission is not performed, since this operation is most simply carried out only in the synchronization center.

 The signal to be transmitted back over the communication line 29 is arranged using the time code converter 45, the information signal source 46, the information code converter 47, the switch 48, the PSP phase manipulator 49, and the PSP generator 50 (identical to blocks 6, 7, 8, 9 10 and 11 of the synchronization center, respectively), as well as a carrier phase manipulator 51, which (unlike the synchronization center former 3) is an adder modulo two. Therefore, the signal sent to the communication line 29 through the key 53 and the transceiver unit 31 (Fig. 3d) is a carrier (Fig. 3d) without a time shift relative to the clock cycles of the driver 44, the segments of which are manipulated as a signal of the PSP (Fig. 3b), and the information code from the information sensor or the code for digitizing the current time (Fig. 3a) from the driver 44. Therefore, the structure of the signal transmitted via the communication line 29 in the opposite direction to the transmitter 2 is completely identical to the structure of the direct signal transmitted along the same line relation, but all the necessary signals for its formation are used directly from the generator 44 of the receiver 30.

This signal via the propagation time T _camshaft (after passage unit 31 and communication line 29, unit 5) is supplied to the corresponding input switch 14 made of, for example, the multiplexer 133 KP7. From the output of the switch 14, this signal is sent for processing to blocks 16.25 of the synchronization center, the operation and purpose of which (Fig. 3p) are completely identical to the operation and purpose of blocks 33.42 of the receiver 30.

 Therefore, using the second chroniser 17, a signal is generated with a frequency of changing the elements of the SRP (1 kHz) of the SRP generator 50 (Fig. 3m); using the first chroniser 16 and the disambiguation unit 18, the carrier frequency of the signal received from the receiver 30 of the signal (Fig.3k) is correctly extracted without a 1/2 period shift; using the carrier filtering unit 19, the SRP with ten-millisecond segments correctly manipulated by digitizing the current time of the former 44 (Fig.3l) is correctly selected from the received signal; using the generated generator 20 SRP, block 21 filtering SRP and the cycle synchronizer 22 correctly restored (fig.3p) SRP (generator 50 SRP, as well as highlighted a serial code of information and digitization of the current time (figr), a signal of frequency 1 Hz of the shaper 44 and an information source 46; using the first register 23, the driver 24 of the enable signal and the second register 25, the serial code of information and digitization of the current time of the source 46 of information and the driver 44 is converted to parallel; as blocks 16, 17, 20 are processed from below The prohibition signals from their respective outputs are switched in. The signals thus prepared in the central part of the synchronization device are used as follows.

 As soon as the prohibition signals from the first 16 and second 17 clocks are removed from the control unit 15 of the signal timing correction (FIG. 4), the signal from the OR element 61 allows the phase discriminator 60 to generate control signals for the corresponding Kth block 4 of the signal timing correction. The generation of these control signals is carried out based on the following information (temporary position of the positive edges of the next pulses): lead-in relative to the signals of the pulse-time sensor 1 (frequency 1 kHz), drop from the corresponding K-th block 4 of correction of the time-ahead of signals through the first switch 13 to the first the input of the control unit 15 of the correction of the lead time of the signals; reference time marks from the sensor 1 time signals (also 1 kHz), filed to the second input of the control unit correction of the timing of the signals; delayed pulses (also 1 kHz, Fig. 3m), delayed relative to the signals propagated by a double time on the corresponding communication line 29 and applied to the third input of the control unit for correcting the time-ahead of signals from the output of the second chronicler 17.

Using these signals allows a block 15 correction control delay time signals to measure two time intervals:? T _exercise of preemption to reference pulses? T _z from the reference to the delayed pulses, as well as to generate, if necessary, on the two respective outputs (defined decryptor 62 and aND elements 58, 59 information channels 57 ₁ .57 _K), the control unit temporarily feedforward correction signal control signals for the respective correction unit 4 temporarily preempting I signals.

The generation of control signals is carried out so long as the lead time signal introduced by the corresponding block 4 of the signal pre-emptive correction into the signal transmitted via the communication line 29 does not lead to the control of the two signals measured by the signal pre-emptive correction control unit 15, two time intervals ΔТ _control = ΔT _s . In this case, the insertion loss in the transmitted signal delay time? T becomes equal _simp propagation time T _camshaft signals corresponding communication line 29, and the signals coming via input receiver 30 may be used for synchronization.

Upon reaching equality _simp? T =? T _s, t. C.ΔT _simp? T = _camshaft, the formation of temporary block feedforward correction control signal is terminated, corresponding memory value contributed as signal delay time in the synchronized channel. In other channels in which the lead-in adjustment is not currently performed, the lead-time memory mode is provided by the forced grounding of the control inputs of the signal-feed-forward correction unit 4 using the elements And 58, 59 of the control unit 15 of the feed-through-signal correction control closed by the decoder 62. Moreover, in this case, using the mismatch analyzer 63, counting the number of control pulses from the discriminator 60 for the selected, for example, second interval, a signal is generated that indicates the end of the correction ΔТ _exercise .

 Consider the operation of the information management unit 15 of the signal lead time (Fig. 4) for generating and sending control signals and the unit 4 interacting with it, correcting the signal lead time (Fig. 5).

The decoder 62 converts the control code, for example, binary decimal, coming from the counter 12 (figure 1), in a positional code, for example, using IC 564ID1. Therefore, the logic signal “1” appears only on one of the K outputs of the decoder 62, and the logic 0 signal is present on its other outputs. When changing the lead code from counter 12 (for example, after 5 min), the logical 1 signal moves to the adjacent output of the decoder, etc. Therefore, the control signals generated as a result of measurement? T _simp and? T _of the phase discriminator 60 (after removal bans from hronizatorov 16, 17 at the inputs OR 61) through one of the K pairs of AND gates 58, 59 are fed to corresponding K th block 4 correction of the lead time of the signals. At all other outputs of the block 15 control correction of the lead time of the signals is the potential of the logical "0", since all other pairs of its elements And 58, 59 are closed by the decoder 62.

 Blocks 4 correction of the lead time of the signals (figure 5) work as follows.

 The carrier frequency is formed by dividing the clock signals of the time sensor 1, for example 5 MHz, to the required frequency (for the case of using TZB cable as communication lines). This frequency, as well as the bandwidth frequency, is chosen equal to 1 kHz, and when using a block of broadband communication lines it can be higher, for example, 100 kHz (using sequentially connected counters 71 with a variable division ratio and 72 with a constant division coefficient). In the described case (for communication over a TZB cable), the total division ratio (in the absence of commands for its correction from the control unit for correcting the signal time lead) is equal to 5000.

 It is assumed that after the next measurement, block 15 provides one of two control signals, which requires an increase in the lead time introduced into the transmitted signal, which is input to the unit in the single state of the dynamic (front-mounted) RS-trigger 64. The potential is logical "1" from the trigger output 64 enters the D-input of the trigger 66, the input of which through the open element And 69 receives a pulse from the output of the counter 71 with a variable division ratio. Upon receipt of the next, for example, a positive edge from the output of the counter 71, the potential of the logical "1" appears at the output of the trigger 66, decreasing the division ratio of the counter 71 by one. Therefore, the next positive edge at the output of the counter 71 appears earlier by a time equal to the period of the input for the frequency counter 71, increasing the lead time of the signals generated by the correction unit for temporal lead time by the specified time (if necessary, the lead of the change in lead time can be reduced by entering the input multiplier before the input of the counter 71 frequency). The same front of the signal from the counter 71 through the open element And 70 returns to the initial state triggers 64.67. Therefore, according to one control command, the lead time correction is performed for a time equal to only one input period for the frequency counter 71.

 If, after the next measurement in the control unit 15 of the correction of the signal lead time requires a reduction of the lead time to the transmitted signal, the corresponding command from the control block correction of the signal lead time is issued to the input of the unit to the single state of the trigger 65. Next, the block 4 correction of the signal lead time works similarly with the only difference that the control signal to the second control input of the counter 71 is supplied through the triggers 65 and 67 and leads to an increase in the coefficient that dividing counter 71. As a result of this command from the control unit temporarily feedforward correction signal corrected feedforward insertion into the transmitted signal, in the absence of control signals previously stored look-ahead time of administration.

 At the end of these processes, a final operation is performed to synchronize the synchronization center of one of the K (in this case, the last) receivers 30, which consists in reliably determining the synchronization input of this receiver 30, forcing the synchronization of another (in this case, the first) receiver 30, if the achievement of synchronism is reliably determined in the K-m receiver 30, without waiting for the end of the K-th five-minute interval allocated for synchronization of the K-th receiver 30 and set by the counter 12. For its real signals to the synchronism analyzer 27, which is, for example, a coincidence element, a signal is collected from the time anticipation correction control unit 15 of the signals about the end of the anticipation time correction signals, prohibition signals from the first 16 and second 17 clocks, as well as from the phased generator 20 SRP, the signal from block 28 comparison.

 The signal from the control unit of the correction of the temporal lead of the signals indicates the equality of the lead in the transmitted signal to the K-th receiver 30, the time of its propagation through the communication line 29, and therefore about the possibility of using the received signal 30 for synchronization.

 The removal of prohibition signals from blocks 16, 17, 20 indicates the correct processing of all blocks of the receiver 30, the synchronism of the shaper 44 of the receiver 30 from the high-frequency input to the output with a frequency of 1 Hz with signals from the sensor 1 of the synchronization center, about the organization of the transmission of the return signal from the receiver 30 to the synchronization center and its correct processing in the center with 16.25 blocks.

 The presence of a signal from block 28 comparison indicates the coincidence of the digitization of the current time (from 1 s to hundreds of years) in the shaper 44 of the receiver 30 and the sensor 1 of the time signals of the synchronization center.

 Thus, the appearance of the signal at the output of the analyzer 27 indicates the reliable achievement of the synchronization of the K-th receiver 30 along the K-th communication line 29. Therefore, even before the end of the K-th five-minute interval allocated for synchronization of the K-th receiver 30, the output signal of the analyzer 27 acts on the counter 12, which changes the control code of the control unit 15 of the correction of the timing of the signals, the first 13 and second 14 switches, providing a transition to synchronization of the next (now the first in FIG. 1) receiver 30. The achieved synchronization of the previous (K-th) receiver is not disturbed, since the inputs of the K-th block of the signal anticipation correction unit 4 are grounded correspondingly th pair of AND gates 58, 59 the block 15, which leads to forced insertion mode memory in the signal delay time. Further, the process is repeated alternately for each time signal receiver 30.

 Therefore, after a time shorter than the mentioned five-minute intervals (set by the counter 12), a certain with high reliability synchronization of all K receivers 30 of information and time signals is carried out.

 As indicated, in the prototype device there is no possibility of transmitting overhead information without interrupting the flow of synchronizing time information on the corresponding communication line due to the fact that only temporal synchronizing information, namely, the timestamp of the correspondingly anticipated carrier frequency, is embedded in the transmitted signal structure (in prototype equal to 1 kHz and allowing to obtain synchronization ambiguity resolution up to 1 ms), SRP information adjusted to the carrier frequency by the first phase new manipulation (in the prototype, the length of the PSP block is 1 Hz), which allows removing the synchronization ambiguity limits up to 1 s after removing this type of phase manipulation, information about the digitization of the current time, adjusted to the carrier frequency (already manipulated by PSP) by the second phase manipulation (in the prototype after removing this type of phase manipulation, the ambiguity of synchronization expands to tens of years).

 In the proposed device, using the blocks introduced into the center and peripheral receivers, the structure, volume and purpose of the signals transmitted in both directions along the communication lines are changed. Moreover, in the new structure of the transmitted signal, the frequency of the selected and appropriately anticipated carrier frequency is stored (1 kHz, as in the prototype); the duration of the PSP block is preserved (1 Hz, as in the prototype), which performs the first phase shift of the carrier frequency and extends the synchronization ambiguity to 1 Hz; the speed of the second phase manipulation of the anticipated carrier frequency (already manipulated by the SRP) by the current time digitization signals (from 20 to 10 ms / symbol) is doubled, expanding the synchronization ambiguity from 1 Hz to tens of years, which reduces the time required to transmit the entire block of information about digitization (from 1 s to tens of years 4 bits x 12 decades + 2 bits "empty" = 50 bits) to 0.5 s (relative to 1 s in the prototype); in the remaining half of the second interval, phase manipulation of the same (already manipulated by the PSP signals and anticipated) carrier frequency is performed by the service information signals, which allows not only transmit 0.5 s: 10 ms = 50 bits of service information on the same line, but also not interrupt a stream of temporary synchronizing information (do not change the phase position of the edges of the carrier frequency). Therefore, the device can transmit service information, unlike the prototype, without disrupting synchronization.

Claims (1)

 A DEVICE FOR TRANSMITTING AND RECEIVING TIME SIGNALS, containing on the central part an exact time signal sensor, the first output of which is connected to the first clock input of the first clock, the first clock input of the second clock, clock inputs of a time code converter, a pseudorandom sequence of pulses, a control unit for correcting timing signals and a correction unit for temporal anticipation of signals of each channel for transmitting and receiving signals, the second output of the sensor signals of exact time The volume is connected to the installation inputs of the time code converter, pseudo-random sequence of pulses, the first and second clocks and the first counting input of the counter, the outputs of which are connected to the address inputs of the first and second switches and the control unit for correcting the time anticipation of signals, the first and second outputs of each group of outputs of which connected to the first and second inputs of the correction block of the temporary lead of the signals of each channel of transmission and reception of signals, respectively, the output is A correction of the signal lead time is connected to the control input of the output signal shaper in each signal transmission and reception channel and the corresponding information input of the first switch, the output of which is connected to the first information input of the signal lead time correction control unit, the output signal shaper output is connected to the information input of the transmission block and receiving signals in each channel of transmitting and receiving signals, the output of which of each channel of transmitting and receiving signals connected to the corresponding information input of the second switch, the output of which is connected to the second clock input of the first chronizer and the first clock input of the carrier frequency filtering unit, the input-output of the signal transmission and reception unit of each signal transmission and reception channel is the input-output of the corresponding communication line, the first and second outputs of the first chronizer are connected to the first input of the prohibition block of the control of correction of time anticipation of signals and the first clock input of the block for disambiguation of signals accordingly, the output of the latter is connected to the second sync input of the carrier frequency filtering unit, the output of which is connected to the second sync input of the second chroniser, the first output of which is connected to the second information input of the signal anticipation correction control unit and the second sync input of the signal ambiguity elimination unit, the second output of the second chronizer the second input of the prohibition of the control unit correction time anticipation of the signals, the outputs of the group of outputs of the sensor signals of time under are connected to the information inputs of the time code converter, the output of which is connected to the information input of the phase manipulator of the pseudorandom sequence of pulses, the output of the generator of the pseudorandom sequence of pulses is connected to the control input of the phase manipulator of the pseudorandom sequence of pulses, the output of which is connected to the information input of the generator of output signals of each signal transmission and reception channel , the second output of the time signal sensor is connected to the control input of the unit control the correction of the temporal lead of the signals, the outputs of the group of outputs of the sensor of the time signals are connected to the inputs of the first group of inputs of the comparison unit, the first output of the first chronizer is connected to the first input of the inhibitor of the synchronism analyzer, the first output of the second chronizer is connected to the clock inputs of the phased generator of a pseudo-random pulse sequence and register, outputs which are connected to the inputs of the second group of inputs of the comparison unit, the output of which is connected to the first information input of the analyzer synchronization, the second output of the second chronizer is connected to the second input of the inhibit analyzer of synchronism, the output of the filtering unit of the carrier frequency is connected to the first sync input of the filtering unit of the pseudo-random pulse sequence and to the first information input of the phased generator of the pseudo-random pulse sequence, the first and second outputs of the last are connected to the third input of the analyzer inhibit synchronism and the second clock input of the filtering unit of the pseudo-random sequence of pulses, the output of which the second is connected to the information input and the second information input of the phased generator of the pseudo-random pulse sequence, the outputs of the group of outputs of which are connected to the inputs of the cyclic synchronizer, the output of which is connected to the installation inputs of the register and the phased generator of the pseudorandom sequence of pulses, the output of the control unit of the correction of the time anticipation of signals is connected to the second information the input of the synchronism analyzer, the output of which is connected to the second counting input of the counter On the peripheral part in each signal transmission and reception channel, a signal transmission and reception unit, the input-output of which is the input-output of the corresponding communication line, the output of the signal transmission and reception unit is connected to the first clock inputs of the first chroniser and the carrier frequency filtering unit, the first output the first chronizer is connected to the first input of the output driver inhibition, the corresponding output of the first group of outputs of which is connected to the installation inputs of the first and second chronizers, the outputs of the first group The outputs of the output driver are the outputs of the first group of outputs of the device, the reference frequency generator, the output of which is connected to the second clock input of the first clock, to the first clock input of the second clock and the first clock input of the output signal, the second output of the first clock is connected to the first clock input of the signal disambiguation unit the output of which is connected to the second clock input of the carrier frequency filtering unit, the output of which is connected to the first information input a phased generator of a pseudorandom sequence of pulses and a second clock input of the second chroniser, the first output of which is connected to the second clock input of the signal disambiguation block, the clock inputs of the phased generator of a pseudorandom sequence of pulses, a register and the second clock input of the output driver, the second output of the second chronizer and the first output of the phased generator pseudo-random pulse sequences are connected to the second and third inputs of the prohibition of of the output signal, respectively, the second output of the phased generator of the pseudorandom sequence of pulses is connected to the second clock input of the filtering unit of the pseudo-random sequence of pulses, the output of which is connected to the information input of the register and the second information input of the phased generator of the pseudorandom sequence of pulses, the outputs of the group of outputs of which are connected to the cycle synchronizer, the output of which connected to the installation inputs of the phased pseudo-oscillator learning sequence of pulses of the shaper of the output signals and the register, the outputs of the latter are connected to the inputs of the first group of information inputs of the decoder, the outputs of which are connected to the information inputs of the shaper of output signals, the outputs of the second group of outputs connected to the inputs of the second group of information inputs of the decoder and are the outputs of the second group of outputs of the device , the corresponding output of the first group of outputs of the output driver is connected to the control input of the analyzer ism and the installation inputs of the time code converter and the pseudo-random pulse train generator, the other two corresponding outputs of the first group of outputs of the output signal shaper are connected to the control input of the carrier phase phase manipulator and the clock inputs of the pseudo-random pulse train generator and the time code converter, respectively, the outputs of the second group of outputs of the output shaper signals are connected to the information inputs of the time code converter, the output of which connected to the information input of the phase manipulator of the pseudorandom sequence of pulses, the output of the generator of the pseudorandom sequence of pulses is connected to the control input of the phase manipulator of the pseudorandom sequence of pulses, the output of which is connected to the information input of the phase manipulator of the carrier frequency, the output of which is connected to the first input of the key, the output of the reference frequency generator and the output cyclic synchronizer connected to the first and second clock inputs of the synchronism analyzer, output which is connected to the second key input, the output of which is connected to the input of the signal transmission and reception unit, characterized in that, in order to expand the scope by transmitting both accurate time signals and service information signals, an information signal source is introduced into it on the central part , information code converter, enable signal generator, second register and third switch connected between the output of the time code converter and the information input of the pseudo-random phase by their first information input and output, respectively, the first output of the time signal sensor is connected to the clock inputs of the third switch and the information code converter, the second output of the time signal sensor is connected to the installation outputs of the third switch, the information code converter and the input of the information signal source, the outputs of the latter are connected to information inputs of the information code converter, the output of which is connected to the second information input of the third switch, the output of the chronizer, the first output of the second chronizer and the output of the phased generator of the pseudo-random sequence are connected through the driver of the enable signal to the enable input of the second register, the outputs of the first register are connected to the information inputs of the second register, the outputs of which are information outputs, on the peripheral part in each transmission and reception channel signal source of information signals, information code converter, register, enable signal driver and switch connected Between the output of the time code converter and the information output of the pseudo-random sequence phase manipulator with its first information input and output, respectively, the third corresponding output of the first group of outputs of the output driver is connected to the clock inputs of the switch and the code converter of information, the first and corresponding output of the first group of outputs of the output signal generator is connected to the installation inputs of the switch and the code information converter and the input of the signal source information, the outputs of which are connected to the information inputs of the information code converter, the output of which is connected to the second information input of the switch, the first output of the first chronizer, the second output of the second chronizer, the first output of the phased pseudorandom sequence generator through the driver of permission signals connected to the resolution input of the second register, the outputs of the first of the register are connected to the information inputs of the second register, the outputs of which are the information outputs of the third group s.

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