RU2029359C1 - Data processing device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: data processing device has processor unit, input/output unit, data retrieval unit, command storage unit, command package shaping unit, and command loading switch. Processor unit has input register unit, arithmetic and logic unit, and microprogrammed control unit. Input/output unit has data switch and code number switch. Data retrieval unit has data storage assembly and associative address retrieval assembly. EFFECT: improved speed due to introduction of command package shaping unit and command loading switch affording concurrent shaping of functional components of command packages. 3 cl, 8 dwg

Description

 The invention relates to computer technology, namely to computing devices that use the control of the computing process from the data stream, and can be used in digital computing systems with high performance.

 A device for processing data comprising a processor, a command memory, a data memory, an interface unit, an instruction selection unit, an instruction printout unit and a register number assignment processor [1] is known.

 However, this device does not differ in high performance, since when performing scalar operations it is determined by the total time of sequential operation of the main functional units: processor, memory commands and data.

 By technical nature, the closest to the proposed device is a data processing device comprising a processor, an input-output unit, a data sampling unit, an instruction memory unit, the first information input of the input-output unit being connected to the first information output of the processor, an information input for inputting a half-packet device data is connected to the second information input of the input-output unit, the control input of which is connected to the input of the device mode code, the second information output of the processor is connected to the fifth information input of the input-output unit, the first output of which is connected to the first information input of the data selection unit and the output of the device result, the output of the address of the next command of which is connected to the input of the search argument of the data selection unit and to the second output of the bits of the code of the number of the command of the input-output unit, the first information output of the data sampling unit is connected to the first information input of the processor, the write permission output of the next data half packet is the device output of the same name, the output the interrupt code of which is connected to the processor output of the same name, the write enable output of the next data packet of which is the device output of the same name, the first control output of the processor is connected to the write enable output of the data sampling unit, processor synchronization inputs, I / O unit, data sample unit and memory block commands are connected to the input of the synchronization device [2].

 However, this device also does not differ in high performance, since it is determined in it by the period of execution of the instruction packages for execution and is limited by the total time of sequential operation of the functional units of the arithmetic logic unit (ALU), data sampling units and instruction memory.

 The aim of the invention is to increase performance by ensuring the parallel formation of the functional components of the command packages.

 This is achieved by the fact that in the information retrieval device comprising a data processing device comprising a processor, an input / output unit, a data sample unit, a command memory unit, the first information input of the input / output unit being connected to the first information output of the processor, an information input for inputting a half-packet of data, the device is connected to the second information input of the input-output block, the control input of which is connected to the input of the device mode code, the second information output of the processor is connected to the third inf the input of the input / output unit, the first output of which is connected to the first information input of the data sample unit and the output of the device, the output of the next command address is connected to the input of the search argument of the data sample unit and with the second output of the bits of the code of the number of the command of the input / output unit, first the information output of the data sampling unit is connected to the information input of the processor, the write permission output of the next data half-packet is the device output of the same name, the interrupt code output which is connected to the processor output of the same name, the write enable output of the next data packet of which is the device output of the same name, the first control output of the processor is connected to the write enable output of the data sampling unit, processor synchronization inputs, I / O unit, data sample unit and command memory unit are connected with the synchronization input of the device, a command packet generation unit and a command loading switch are introduced, the input of a sign of readiness of a data packet being connected to the output of the block the formation of command packets, the group of information inputs of which is connected to the inputs of the bits of the packet of the command of the processor, the input of the permission to download the data packet of which is connected to the device input of the same name, connected to the ready input of the external packet of the command packet forming block, the input for entering the data packet of which is the device input of the same name, the control input of the operating mode of which is connected to the input of the boot control of the command loading switch, the input of the control of the operating mode of the unit, you data orcs to the processor input of the same name, the output of the data retrieval control signal which is connected to the first information input of the data sampling unit, the memory reset control input of which is connected to the device input of the same name, whose address input is connected to the same input of the command loading switch, the output of which is connected to the input discharges of the command word and the output of the sign of readiness of the command word which is connected to the corresponding inputs of the unit for forming command packets, the input of the first operand of which о is connected to the output of the bits of the code for the number of the input-output block, the inputs of the first and second bits of the code for the search result of the processor are connected respectively to the outputs of the data sampling block of the same name, the data output and the output of the sign of data readiness of which are connected respectively to the inputs of the second operand and the write permission of the second operand a unit for generating command packets, an input sign of a single operand and a write permission input of the first operand of which are connected respectively to the output of the same name and the control output transmitting the result of the processor, the start control output of which is connected to the input of the initial installation of the command packet forming unit and to the control input of the command word reading of the command memory block, the control word record control input and the output of the end word record of the command word are the device input and output, respectively, the control word information input and the control word recording permission input of which are connected respectively to the input of the bits of the control word and the control input reception of the control word combined with the input of the sign of transmission of the command word of the command memory block, the input of the bits of the sample code of the command word of the command loading switch is connected to the output of the input-output block of the same name, the output of the memory overflow signal of the data sample block is the output of the device memory overflow sign, and the synchronization inputs of the command packet generation unit and the command loading switch are connected to the device synchronization input.

 The command packet generation unit contains the first, second and third switches, the first, second and third packet generation registers, the first, second and third triggers, the AND element and the OR element, the first information input of the first switch being connected to the outputs of the first, second and third formation registers of the packet, the first control input is connected to the output of the AND element and the output of the sign of readiness of the packet of the unit for forming command packets, the output of the bits of the command word of which is connected to the outputs of the first and second switch in, the first, second information and control inputs of the last of which are connected to the output of the first, the input of the initial installation of the command packet generation unit is connected to the control inputs of the first, second and third triggers, the outputs of which are connected to the inputs of the element And, the second information and second control inputs of the first the switches are respectively an input for inputting a data packet and an input of a sign of readiness of an external packet of a block for generating command packets, the write enable input of the second operand of which is is dined with the first input of the OR element and the first control input of the third switch, the output of which is connected to the information input of the second register, the read-write input of which is connected to the output of the OR element, which is connected to the installation input in "1" of the second trigger, the write enable input of the first operand of the command packet forming unit is connected to the installation input in "1" of the third trigger and the read-write input of the third register, the information input of which is connected to the input of the first operand of the command packet forming unit, input the sign of a single operand of which is connected to the second input of the OR element and the second control input of the third switch, the first and second information inputs of which are connected respectively to the input of the logical "0" block of the formation of command packets and to the input of the second operand of the block of command packet formation, the gate input of which is connected to the installation input to "1" of the first trigger and to the read-write input of the first register, and the information input of the first register is connected to the command input of the command packet generation unit.

 The data selection block contains a data memory node and an associative address selection node, wherein the associative address selection node contains a group of associative storage elements, first, second, third and fourth OR elements, a group of OR elements, a switch, first and second priority encoders, a decoder, an AND element and the element is NOT, while the information input of the first category and the reset input of each storage element are connected respectively to the inputs of the operation mode control and memory reset of the associative access node ow, write and read permission inputs are connected respectively to the inputs for controlling the recording of the argument and data search of the associative address selection node, the information inputs of the second category of associative storage elements are connected to the corresponding outputs of the decoder, the information inputs of the third and fourth bits of associative memory elements are connected respectively to the input of the search argument node associative sample addresses and to the output of the element NOT, the first and second information outputs of associative of the omitting elements are connected respectively to the inputs of the first and second OR elements, the outputs of which are respectively the write control output and the reading control output of the associative address selection node, the third and fourth information outputs of the associative storage elements are connected respectively to the inputs of the third and fourth OR elements and the first and second inputs corresponding elements OR groups whose outputs are connected to the corresponding inputs of the first priority encoder and control inputs by the switches of the switch, the inputs of the address bits of which are connected respectively to the fifth information outputs of the corresponding associative storage elements, the sixth information outputs of which are connected to the inputs of the second priority encoder and the corresponding inputs of the AND element, the output of which is the memory overflow output of the associative address selection node, the output of the second priority encoder is connected with the input of the decoder, the input of the element is NOT connected to the output of the third element OR, which is the first output the search ultat of the associative address selection node, the second output of the search result of which is connected to the output of the fourth OR element, the outputs of the switch and the first priority encoder are connected to the output of the data address of the associative address selection node, the first information input of the data selection block is connected to the initial setup input of the data memory node and with the data search control input node of the associative address sample, the second information input of the data sample block is connected to the data input of the data memory node, the input times The solution for recording the result of the data sampling unit is connected to the input control input of the data memory node and to the input of the recording control of the argument of the associative address selection node, the operation mode control input of which is the input of the data selection block of the same name, the inputs of the search and reset arguments of which are connected to the node inputs of the same name associative address selection, memory overflow output, the first and second outputs of the search result for a pair of associative address selection nodes are the outputs of the same name data sampling, write control output, read control output and data address output of the associative address selection node are connected to the inputs of the data memory node of the same name, the output of the memory overflow sign, the data output and the output of the data readiness sign of which are the outputs of the data sample block of the same name.

 The essence of the invention lies in the fact that the introduction of a unit for generating command packets and a switch for loading commands allows for simultaneous execution of operations in the main functional units: a processor, a memory block of commands, and a block of data sampling.

 In FIG. 1 is a functional block diagram of a device for processing information; figure 2 is a functional electrical diagram of a block of input registers; figure 3 - block firmware control; figure 4 - node data memory; figure 5 - node associative sample addresses; figure 6 - associative storage element; figure 7 - block formation of command packets; Fig. 8 shows an example of bit fields of a command packet.

 The device comprises a processor 1, an input / output unit 2, a data sampling unit 3, an instruction memory unit 4, an instruction packet generation unit 5, and an instruction loading switch 6. The processor 1 contains a block 7 input registers, ALU 8 and block 9 firmware control. The input / output unit 2 comprises a data switch 10 and a command number switch 11. The data sampling unit 3 comprises a data memory unit 12 and an associative address sampling unit 13.

 The device contains inputs 14 ... 23 respectively address, control recording command word, write command word permission, information command word, for entering a half-packet of data, device mode code, memory reset, control of device operation mode, permission to load data packet and for entering packet data and outputs 24 ... 30, respectively, the sign of the end of the recording of the control word, the sign of memory overflow, write permission for the next half-packet of data, write permission for the next data packet, address next to Mandi, interrupt code, the result of the device. The processor 1 contains inputs 31 ... 38, respectively, of the sign of readiness of the data packet, command, permission to load the data packet, the first and second results of pair search, load control of a half packet of data, control of the operating mode and information, and outputs 39 ... 48 of the start control, first and second information, data search control signal, recording permission for the next half-packet of data, recording permission for the next data packet, interrupt code, control, transmission control result, single sign operand. The input-output block 2 contains a control input 49, the first, second and third information inputs 50, 51 and 52, respectively, and the first and second outputs 53 and 54.

 Block 3 data sampling contains inputs 55 ... 60, respectively, of the search argument, memory reset, the first and second information, permissions to record the result and control the operation mode, and outputs 61 ... 66, respectively, memory overflow, sign of memory overflow, data, sign of data readiness and the first and second search results. The node 12 of the data memory contains inputs 67 ... 72 of read control, write control, data address, initial setup, data and data reception control, and outputs 73 ... 75 of a sign of memory overflow, data and a sign of data availability, respectively. The associative address selection node 13 contains inputs 76 ... 80 of the search argument, memory reset, data retrieval control, argument record control, operation mode control, and memory overflow outputs 81 ... 84 and 85-1, 85-2, write control, reading controls, data addresses and the first and second search results, respectively.

 Block 5 of the formation of command packets contains inputs 86 ... 95 of the initial installation, the second operand, the sign of a single operand, the write permission of the first operand, the write permission of the second operand, the sign of readiness of the external packet, for entering the data packet, the first operand, command and strobe and exit 96 signs of package readiness, a group of information outputs 97, respectively. The synchronization inputs of the processor 1, input / output unit 2, data sample unit 3, command memory unit 4, command packet generation unit 5 and command loading switch 6 are connected to the device synchronization input 98.

 Unit 4 of the command memory contains inputs 99 ... 104 information, reading control, write control, sign transmit command words, control the reception of the command word and bits of the command word and outputs 105 ... 107 sign of the end of the record command word, information and sign of readiness, respectively . The first information input 108 of the switch 6 command download is the address input 14 of the device. The control input 109 of the switch 6 is connected to the input 21 of the control mode of the device, the second information input 110 of the switch 6 is connected to the second output 54 of the input / output unit 2, and the output of the switch 6 is connected to the information input 99 of the unit 4 of the command memory.

 Block 7 of the input registers (figure 2) contains, respectively, the first, second, third, fourth and fifth buffer registers 111, 112, 113, 114 and 115 receive command packets, information input 116-1, control input 116-2 and information outputs 117 -1 ... 117-5.

 ALU 8 is made similarly to the device according to ed. USSR N 1367012, class G 06 F 7/36, 1985, and contains respectively an information input connected to the first information output 117-1 of block 7. The control input of the ALU is connected to the output 139-1 of block 9 of the firmware control. The information, first and second control outputs of the ALU are connected to the first information output 40 and output 45 of the interrupt code of processor 1 and input 138-2 of block 9.

 Block 9 firmware control (figure 3) contains the first, second and third elements OR 118, 119 and 120, the first, second and third elements AND 121, 122 and 123, the first, second, third, fourth and fifth triggers 124, 125, 126, 127 and 128, the fourth, fifth, sixth, seventh and eighth elements AND 129, 130, 131, 132 and 133, the element HE 134, the fourth and fifth elements OR 135 and 136 and the ninth element AND 137, inputs 138-1. ..138-9 and outputs 139-1 ... 139-8.

 The node 12 of the data memory (figure 4) contains, respectively, the first and second buffer registers 140 and 141, a group of LSI memory 142-1 ... 142- (N + 1) direct access type KR132RU6, the first and second shift registers 143 and 144, the first, second and third elements OR 145, 146 and 147, the trigger 148 and the element NOT 149. The information inputs of the first buffer register 140 are connected to the data input 72 of the data memory node 12, and the outputs of the LSI memory 142-1 ... 142- (N +1) - with the output of 74 data node 12 data memory.

 The node 13 associative sample addresses (figure 5) contains respectively a group of associative storage elements 150-1 ... 150-K, the first and second elements OR 151 and 152, a group of elements OR 153-1 ... 153-K, switch 154 , the first and second priority encoders 155 and 156, the decoder 157, the AND element 158, the third and fourth OR elements 159 and 160, the HE element 161. Each i-th element from the group of OR elements 150-1 ... 150-K contains information inputs 162-i, 163-i, 164-i and 165-i of the first, second, third and fourth digits, inputs 166-i and 167-i write permissions and read permissions, input 168-i reset and the first. . .6th category of outputs 169-i ... 174-i. The first, second, third and fourth elements OR 151, 152, 159 and 160 have inputs 175-1 ... 175-K, 176-1 ... 176-K, 177-1 ... 177-K and 178- 1 ... 178-K, respectively. The decoder 157 has outputs 179-1 ... 179-K, each i-th of which is connected to the corresponding i-th input 163-i of the recording permission of the associative storage element 150-i. The group of inputs 180-1 ... 180-K of the first priority encoder 155 and the group of control inputs 181-1 ... 181-K of the switch 154 are connected to the outputs of the corresponding elements OR 153-1 ... 153-K. Inputs 181-1 ... 182-K bits of the address code of the switch 154 are connected to the outputs 173-1 ... 173-K of the address code of the number of corresponding associative storage elements 150-1. . .150-K, and the inputs 183-1 ... 183-K of the And element 158 and the inputs 184-1 ... 184-K of the second priority encoder 156 are connected to the outputs 174-1 ... 174-K of the overflow sign of the corresponding associative storage elements 150-1 ... 150-K.

 Each associative storage element 150-i (Fig. 6) contains the first and second buffer registers 185 and 186, a matrix 187 of fxm associative storage microelements 188-1 ... 188- (fxm), a decoder 189, a switch 190, a priority encoder 191 , the first and second elements are NOT 192 and 193, the shift register 194, the first to sixth elements And 195 ... 200, the group of elements And 201-1. . . 201-m, the seventh and eighth elements AND 202 and 203, the first and fourth elements OR 204 ... 207, the first and second triggers 208 and 209 and the trigger group 210-1 ... 210-m. The inputs 211-1 ... 211-f of the register 185 are connected to the corresponding input 164-i of the bits of the command number, the input 212 of the control of the register 185 is connected to the output of the OR element 206. Each pair of paraphase outputs 213-1, 214-1 ... 213 -f, 214-f of the first buffer register 185 and line inputs 215-1. . .215-m records are connected to the corresponding microelements 188-1 ... 188- (fxm) of the matrix 187, the outputs 216-1 ... 215-m of which are connected to the corresponding inputs of the first OR element 204 and switch 190. Outputs 217-1 . . . 217-m of the decoder 189 connected to the first inputs of the elements And 201-1 ... 201-m.

 Unit 5 formation of command packets (Fig.7) contains the first, second and third switches 218, 219 and 220, the first, second and third registers 221, 222 and 223 of the formation of the packet, the first, second and third triggers 224, 225 and 226, element And 227 and an OR element 228. The first switch 218 has first and second information inputs 229 and 230 and the first and second control inputs 231 and 232. The second switch 219 has first and second information inputs 233 and 234 and the first and second control inputs 235 and 236 The outputs of the first and second switches are connected to the information output 97 of the block 5 formir command packages. The third switch 220 contains the first, second information and control inputs 237, 238 and 239, 240 and an output 241 connected to the information input of the second register 222.

 The first information input 50 of the input-output unit 2 is connected to the first information output 40 of the processor 1. The input 18 for inputting a half-packet of device data is connected to the second information input 51 of the input-output unit 2, the control input of which 49 is connected to the input of the device mode code 19. The second information output 41 of the processor 1 is connected to the third information input 52 of the input-output unit 2, the first output 53 of which is connected to the first information input 58 of the data sampling unit 3 and the output 30 of the device result. The output 28 of the address of the next device command is connected to the input 55 of the search argument of the data sampling unit 3 and to the second output 54 of the input-output unit 2. The first information output 62 of the data sampling unit 3 is connected to the information input 38 of the processor 1, the output 43 of the recording permission of the next data packet of which is the same output 26 of the device. The output 29 of the device interrupt code is connected to the same output 45 of the processor 1, the output 44 of which enables recording the next data packet is the same output 27 of the device. The control output 46 of the processor 1 is connected to the input 59 of the permission to write the result of the block 3 data sampling. The input 31 of the sign of readiness of the data packet of the processor 1 is connected to the output 96 of the sign of readiness of the packet of the block 5 of the formation of command packets, the group of information outputs 97 of which is connected to the input 32 of the processor 1, the input 33 of which allows downloading the data packet of the same input 92 of the device and is connected to the input 91 signs of readiness of the external package of block 5 of the formation of command packets. The input 92 for entering the data packet of block 5 is the same input 23 of the device. The device operation mode control input 21 is connected to the control input 109 of the command loading switch 6, the operation mode control input 60 of the data sample unit 3 and the same input 37 of the processor 1. The output of the processor data search control signal 42 is connected to the first information input 57 of the data sample unit 3, the input 56 of the memory reset which is connected to the same input 20 of the device. The address input 14 of the device is connected to the first information input 108 of the command loading switch 6, the output of which is connected to the information input 99 of the command memory 4. Information output 106 and output 107 of the sign of readiness of block 4 are connected respectively to inputs 94 and 95 of the command and strobe, respectively, of block 5 of the formation of command packets. The input 93 of the first operand of block 5 is connected to the output 53 of the block 2 input-output. The first and second inputs 34 and 35 of the search results of the processor 1 are connected respectively to the outputs 65 and 66 of the same data block 3, the output 63 of the data and the output 64 of the sign of readiness of the data of which are connected respectively to the input 87 of the second operand and the write permission 90 of the second operand of block 5 formation of command packages. The input 88 of the single operand flag and the write permission input 89 of the first operand of block 5 are connected respectively to the output 48 of the single operand flag and the output 47 of the processor result transmission control, the start control output of which 39 is connected to the input 86 of the initial installation of the command packet forming unit 5 and to the input 100 reading control unit 4 memory commands. The recording control input 101 of block 4 is the input of the same name 15 of the device, the command word information input 17 and the command word recording permission input 16 of which are connected respectively to the command word bit input 104 and the command word input control 103 of the command memory unit 4. The input 103 of the reception control word of the block 4 is connected to the input 102 of the sign of the transmission of the command word of block 4 of the command memory.

 The device provides the execution of the program received at the input 23 from an external control computer system (not shown in the figures), and the output of the processing results at the output 30. Initialization of work starts from the moment the starter packet is fed to input 92 and the control signal is passed to input 91 of block 5 of packet formation commands and input 33 of the processor 1. At the same time, the input of the OR element 119 receives the signal of the readiness of the download package to the input 138-1 of block 9 and further, and a reception signal is generated at its output, which is input to the input 116-2 of block 7 of the input x registers. At the outputs 117-1. . . 117-5 block 7 of the input registers the code is generated corresponding to the functional bit fields of the command packet (Fig. 8).

 At the same time, the “Start” signal is generated at the output 139-1 of block 9, which is input to the ALU 8 control input and output 39 of processor 1, from where it goes to the inputs 100 and 86 of the command memory block 4 and the command packet generation block 5, respectively. From the output 40 of the processor 1, the discharge signal of the command number code code is supplied through the input / output unit 2 to the input 55 of the data sampling unit 3 and the input 110 of the switch 6, the output of which, in the absence of a control signal at the input 109, is fed to the input 100 of the command memory 4.

 If there is a logical “1” signal at inputs 117-3 and 117-4 of block 7, corresponding to the presence of 2K (two-input command), output 139-7 of block 9 generates a pair search control signal (URPP) that coincides in time with the signal " Start". The latter enters the input 57 of block 3 of the data sample, initiating its launch.

 Thus, when the “Start” signal is generated in the device, three functional devices are launched in parallel: processor 1, data sampling block 3 and command memory block 4, and also zeroing of command packet generation block 5.

 In node 13, the URPP signal from input 57 is supplied to the inputs 167-1 ... 167-K of the group of associative storage elements 150-1 ... 150-K and through the OR element 206 a control signal is generated for the buffer register 185, according to which the code of the search argument is accepted (bits of the command number). The shift register 194 is started, and the triggers 208, 209 are set to zero. The phase code from the outputs 213-1 ... 213-f and 214-1. . . 214-f of the register 185 is supplied respectively to the bit inputs plus and minus of the matrix 187.

If there is a coincidence of the values of the bits of the code from the outputs of the register 185 and the code stored in the j-th row of the matrix 187 of the i-th element of the group (j = 1. .M, ai = 1 ... K), then on the corresponding output 216- j of the group of outputs of matrix 187, a signal of a comparison indicator is generated, which is fed to the j-th input of the OR element 204 and the j-th input of the group of inputs of the switch 190. From the output of the OR element 204, the signal goes to the second input of the AND element 195 and to the input of the element NOT 192, moreover, the first input of the element And 195 receives a signal from the first output of the shift register 194. Moreover, the output of the element And 195 a signal is generated that goes to the first input of the trigger 208, to the first input of the OR element 205 and to the first control input of the switch 190. At the output of the trigger 208, a logical "1" signal is set, which is fed to the third output 171 of the i-th element (CPM comparison sign signal _i ), and to the first input of the And 199 element, the second input of which receives a signal from the second output of the shift register 194. At the output of the And 199 element, a PRRT _i signal is generated - a read indicator, which is output 170 of the i-th element of the group.

 At the jth output of the group of outputs of the switch 190, a logical “1” signal is generated, which corresponds to the jth row of the matrix 187, where the arguments coincided, which is transmitted to the priority encoder 191, which generates a code corresponding to the storage address of the number in the BIS memory group of node 12. This code from the output of register 186 goes to the output 173-i of the i-th element of the group.

Signals RSTT _i , CPM _i and the address code are generated only in that element of the group where the argument coincided at the output of register 185 with the argument stored in the jth row of matrix 187. The outputs of all elements of the group according to the signals RRTT _i and CPM _i are combined respectively OR elements 152 and 159, from the outputs of which to the outputs 82 and 85-1, respectively, the signals OPRCHT and SR (signal code result of the comparison of arguments) are received. In this case, the OCRCH signal is supplied from the output 82 to the input of the node 12, and the CP signal, through the output 85-1 of block 3, goes to the input 35 of the processor 1.

The bits of the address code from the output of the register 186 through the output 173 of the element are supplied to the corresponding input 182-i of the switch 154, the input 181-i of which receives a control signal from the output of the element OR 153-i, the first input of which receives the signal of the argument of non-comparison argument (НСРМ) from the output 172-i, and to the second input - the signal CPM _i c output 171-i group of elements.

If there is a CPM _i signal at the output of the ith element (it is assumed that there is only one paired operand), the НСРМ ₁ ... НСРМ _К signals are not generated, since their formation circuit is blocked by a signal to block recording of the zero level from the output of the element NOT 161, which arrives at input 165-i of each element of the group, and from it to the third input of element And 198. At the output of switch 154, the lower bits of the address code are formed, which are output 84, which also receives the high-order code generated at the output of the priority encoder 155, in the input dah 180-1 ... 180-K which contains signals from the outputs of the group of elements OR 153-1 ... 153-K.

 From the output 84 of the node 13, the bits of the address code go to the input of the node 12 of the data memory and then to the information input of the register 141, the control input of which receives a signal from the output of the OR element 146, the first input of which receives the signal ECHR from the output 82. At the output register 141 sets the address code, which is fed to the address input of the group BIS ZU 142-1 ... 142- (N + 1).

 From the output of the trigger 148, a logical "1" signal is supplied to the first input of the write-read control, and to the second input, the signal from the output of the shift register 143 of the UPRCHT signal for the time required for the operation of the LSI memory. At the same time, after a time determined by the operation of the BIS memory, a code of a number with the PL flag (the place of the operand in the packet) is generated at its outputs, and at the second output of register 143, an IF (number transfer) signal corresponding to it in time is received, which are respectively transmitted to outputs 63 and 64 of the block 3. The IF signal is fed to the second input of the OR element 228 and to the control input 239 of the switch 220, to the information input 238 of which the digits of the number code (second operand) with the PL flag from the input 87 of block 5 are received. As a result, the register 222 is received second operand code selected th unit of the 12 data memory into the match command codes numbers relating to the expected results ALU 8. Simultaneously, the installation in a single state of the trigger 225.

 At the information output of the command memory block 4 by the “Start” signal, the bits of the control word code are generated, which are transmitted to the register 221 of block 5 by the PKS signal (transmission of the command word) from the output of the command memory block 4 with the simultaneous installation of the trigger 224 into a single state.

 At the end of the ALU 8 operation, bits of the result code are formed at output 40, and at the other output, a logical “1” signal is supplied to input 138-2 of block 9. At the same time, output 139-4 of block 9 generates a signal UZPRG 1 (control write to the first register of the packet). At the output 53 of block 2, a number code is generated that corresponds to the result at the output 40 of processor 1, together with a sign of the submarines that enter the input 87 of block 5.

 The signal УЗПРГ 1 is fed to the first input of the trigger 226 and the control input of the register 223, as a result of which the output of the trigger 226 is set to a logical signal "1", and the output of the register 223 is the code of the first operand with the flag PL. At the same time, at the output of the And 227 element, a PRPK signal is generated, which determines the presence of the next command packet, ready for processing in processor 1.

 The code bits of the functional groups of the packet from the outputs of the registers 221-223 go to the first multi-bit information input 229 of the switch 218, the first control input 231 of which receives a signal from the output of the element And 227. From the output of the switch 218, the code bits of the first and second operands are respectively sent to the first and the second multi-bit information inputs 233 and 234 of the switch 219, and the categories of signs of the submarines of the first and second operands are supplied to its first and second control inputs 235 and 236. Moreover, at the first and second outputs of the switch 219 bits are formed respectively of the right and left operands of the packet, which are output at the output 97 of block 5. The next finished packet is received for execution.

When, when comparing the code of the input argument with the codes stored in the matrices of elements 150-1 ... 150-K, equality of codes is not detected (i.e., none of the elements of the group generates a signal CPM _i ), the output of element And 196 is formed the signal corresponding to the fact of the discrepancy of the arguments, and the trigger 209 is set to a single state. At the same time, an address code is generated at the output of the register 186 corresponding to the signals at the inputs of the switch 190 that correspond to the state of the group of triggers 210-1 ... 210-m that determine the level matrix filling s 187, and at the output of the element And 198 of the i-th element of the group, a unit level is established, determined by the condition for the coincidence of single signals at its inputs. In this case, a single level from the output of the trigger 209 is received at one input of the And 198 element, and a single level from the input of the 165th element corresponding to the signal at the output of the HE 161 element (determined by the absence of the CP signal from the output of the OR element 159 at its input) ) At the third input of the And element 198 of the i-th element of the group, a write permission signal is supplied to the element corresponding to the output 179-i of the decoder 157 and determining the number of the least unfilled element. The code at the input of the decoder is generated by the encoder 156 from the corresponding signal filling elements at the inputs 184-1 ... 184-K.

 Thus, the unit level at the output of the element And 198 and at the output 172-i appears only in the junior unfilled element.

Upon receipt of the output НСРМ _i at the second control output of the node 13, the НСР signal is generated, which is fed to the input 35 of the processor 1. At the same time, the output control signal half-packet is generated at the output 139-9 of block 9, which is input to the input 57 of block 3 , and in node 12, the number is received from the output 53 of block 2 to the register 140, and in node 13, a signal of a recording characteristic is generated at the output of the AND element 203 of the i-th element of the group. At the same time, at the output of the OR element 207 of the i-th element of the group, a signal of the recording characteristic of the PRZP _{i is} generated, which is fed to the first inputs of the elements AND 201-1 ... 201-m and to the output 169-i of the element. The address generated at the output of the register 186 and corresponding to the free row of the matrix 187 is fed to the input of the decoder 189, at the output 217-j of which the signal for writing the argument RZPA _j is generated, which is fed to the second input of the corresponding element And 201-j, the output of which is the signal arriving at the input 215-j of the recording lines of the matrix, which corresponds to writing the input argument to the j-th line with the simultaneous installation of the trigger state 210-j into a single state.

The output signal PRZP _i formed at the output 169-i is fed to the input 175-i of the OR element 151, the output of which (in the form of the signal UPRZP) is fed to the second control input of the data memory unit 12, the second information input of which is supplied by the bits of the code the output of the switch 154 and the priority encoder 155. In this case, the signals at the inputs 180-1 ... 180-K of the encoder 155 and at the control inputs 181-1 ... 181-K of the switch 154 are determined by the conditions for generating the signal НСРМ _i at the output 172-i storage element of the group.

 The signal UPRZP arrives at the second input of the OR element 146, at the second input of the trigger 148 and at the input of the shift register 144. At the same time, bits of the address are received to the register 141 and transferred to the address input of the BIS ZU 142-1 group. . . 142- (N + 1), setting the trigger 148 to zero and generating at the output of the element 149 a zero control pulse signal in accordance with the delay determined by the first output of the shift register 144, as a result of which the code bits of the number are recorded from register 140 in the LSI Memory 142-1 ... 142- (N + 1). Formed at the second output of the shift register 144, the KNZP signal (the end of the recording) is fed through the output 62 of block 3 to the input 38 of processor 1, as a result of which the trigger 128 is set to a single state (via the And 130 element), which corresponds to the formation of a signal at the output of block 9 request a packet, which is output 27. This signal from the external control system receives bits of the code of the download package and a signal indicating the readiness of the download package PRPKZ. Through the switches 218, 219, the functional groups of the bits of the packet arrive at the input 32 of the processor 1, and at its input the signal PRPKZ.

 When the command to which the result of the current calculations relates has a 1K sign, i.e., it is a single-input, the UPRP signal is not generated and block 3 does not work. Upon completion of ALU 8 operation, the PRGR signal according to condition 1K-1 is sent to block 9, where the signal of the single operand PR1OP signal is generated at the output of element And 131, which, through the output of block 9, goes to input 86 of block 5, where zeros are recorded in register 222 through the switch 220 and the simultaneous installation in a single state of the trigger 225.

 Simultaneously with the output of the AND element 131, the signal PR1OP through the OR element 135 is sent to the output 139-9 of block 9 in the form of a signal УЗПРГ1, as a result of which the ALU result is received on the packet forming register 223. The reception of the command word on the register 221 occurs similarly to the above.

=

где Т_i - время работы одного узла;
Т_ППК1 - период следования пакетов при последовательной работе узлов;
Т_ППК2 - период следования пакетов при параллельной работе узлов.Thus, the introduction of additional nodes allows you to increase the performance of the device by reducing the period of succession of ready-made command packages for execution in ALU 8, which is achieved by organizing the parallel formation of functional bit groups included in the command package. Moreover, the repetition period of the finished package does not exceed the maximum working time of any functional node max T _i . The degree of reduction of the period of the packets depends on the ratio of the operating times of the functional devices involved in the formation of the team package, and can be represented as
M =

=

where T _i is the operating time of one node;
T _PPK1 - the period of packets following the sequential operation of the nodes;
T _PPK2 - the period of the packets during parallel operation of the nodes.

 Dummy tests showed the possibility of industrial use of the proposed device.

Claims (3)

 1. DEVICE FOR PROCESSING INFORMATION, comprising a processor, an input-output unit, a data sampling unit, an instruction memory unit, wherein the first information input of the input-output unit is connected to the first information output of the processor, the input for inputting a half-packet of device data is connected to the second information input of the unit input-output, the control input of which is connected to the input of the device mode code, the second information output of the processor is connected to the third information input of the input-output unit, the first output of which is connected to the first the information input of the data sampling unit and the output of the result of the device, the output of the address of the next command of which is connected to the input of the search argument of the data sampling unit and to the second output of the input-output block, the information output of the data sampling unit is connected to the information input of the processor, the write permission output of the next data packet of which is the device output of the same name, the interrupt code output of which is connected to the processor output of the same name, the write permission output of the next data packet of which is is the device output of the same name, the control output of the processor is connected to the input of the recording permission of the result of the data sampling unit, the inputs of the processor synchronization, input / output unit, the data sampling unit and the command memory block are connected to the device synchronization input, characterized in that a packet forming unit is introduced into it commands and a command loading switch, and the input of the sign of readiness of the processor data packet is connected to the output of the sign of readiness of the packet of the command packet forming block, the group of information in the moves of which are connected to the processor command input, the data packet download permission input of which is the device’s input of the same name and connected to the readiness sign of the external package of the command packet forming unit, the input of which data packet is the input of the same device input, the operation mode control input of which is connected to the input control switch loading commands to the control input of the operating mode of the data sampling unit and to the processor input of the same name, the output of which controls the search for data connected to the first information input of the data sampling unit, the memory reset input of which is connected to the device input of the same name, the address input of which is connected to the first information input of the command loading switch, the output of which is connected to the information input of the command memory block, the information output and which of the readiness indicator are connected respectively, with the inputs of the command and the strobe of the block forming the packet of commands, the input of the first operand of which is connected to the output of the input-output block, the first and second inputs are cut processor search results are connected respectively to the outputs of the data sampling unit of the same name, the data output and the output of the data ready indicator are connected respectively to the input of the second operand and the write enable input of the second operand of the instruction packet forming unit, the single operand attribute input and the write enable input of the first operand are connected respectively with the output of the sign of a single operand and the output of the control transfer of the result of the processor, the output of the start control of which is connected to the input to the initial installation, blocks for forming a command package and to a read control input of a command memory block, the write control input of which is the device input of the same name, the command word information input and the command word write permission input of which are connected respectively to the input of the bits of the command word and the input of the command word reception control blocks the command memory, the input of the control reception of the command word of which is connected to the input of the sign of the transmission of the command word of the command memory unit, the second information the input of the command loading switch is connected to the second output of the input-output unit, the memory overflow output of the data sampling unit is the output of the device memory overflow sign, and the synchronization inputs of the command packet generation unit and the command loading switch are connected to the device synchronization input, to the output of the end of command recording words of which the same output of the command memory block is connected.  2. The device according to claim 1, characterized in that the command packet generation unit comprises three switches, three packet generation registers, three triggers, an AND element, and an OR element, the first information input of the first switch being connected bitwise to the outputs of the packet forming registers, the first control the input of the first switch is connected to the output of the AND element and the output of the sign of readiness of the package of the command packet forming unit, the group of information outputs of which is connected to the outputs of the first and second switches, the inputs of the second the first switch is connected to the output of the first switch, the input of the initial installation of the command packet generation unit is connected to the installation inputs in the “O” triggers, the outputs of which are connected respectively to the inputs of the And element, the second information and control inputs of the first switch are respectively the input for entering the data packet and the input sign of readiness of the external packet of the instruction packet forming block, the write enable input of the second operand of which is connected to the first input of the OR element and the first control input switch, the output of which is connected to the information input of the second register, the read-write input of which is connected to the output of the OR element, which is connected to the installation input in "1" of the second trigger, the write enable input of the first operand of the command packet forming unit is connected to the installation input in " 1 "of the third trigger and the read-write input of the third register, the information input of which is connected to the input of the first operand of the command packet forming unit, the input of the sign of the single operand of which is connected to the second input OR element and the second control input of the third switch, the first and second information inputs of which are connected respectively to the logical zero input of the command packet forming unit and to the input of the second operand of the command packet forming unit, the gate input of which is connected to the installation input in “1” of the first trigger and the read-write input of the first register, and the information input of the first register is connected to the command input of the command packet forming unit.  3. The device according to claim 1, characterized in that the data sampling unit contains a data memory node and an associative address selection node, wherein the associative address selection node contains a group of associative storage elements, four OR elements, a group of OR elements, a switch, two priority encoders, a decoder, an AND element, and an NOT element, the information input of the first category and the reset input of each storage element being connected respectively to the control inputs for operating mode and memory reset of the associative access node owls, the recording and reading permission inputs of each storage element are connected respectively to the inputs of controlling the recording of the argument and the data search of the associative address selection node, the information inputs of the second category of associative storage elements are connected to the corresponding outputs of the decoder, the information inputs of the third and fourth bits of associative storage elements are respectively input argument search node associative selection of addresses and to the output of the element NOT, the first and second bits of the outputs as sociative storage elements are connected respectively to the inputs of the first and second OR elements, the outputs of which are respectively the write control output and the reading control output of the associative address selection node, the third and fourth bits of the outputs of associative storage elements are connected respectively to the inputs of the third and fourth OR elements and the first and second the inputs of the corresponding elements OR groups whose outputs are connected to the corresponding inputs of the first priority encoder and control the input inputs of the switch, the information inputs of which are connected bitwise to the fifth output bits of the corresponding associative storage elements, the sixth output bits of which are connected respectively to the inputs of the second priority encoder and the And element, the output of which is the memory overflow output of the associative address selection node, the output of the second priority encoder is connected to the input of the decoder, the input of the element is NOT - with the output of the third OR element, which is the first output of the search result for the associative node explicit address selection, the second output of the search result of which is connected to the output of the fourth OR element, the outputs of the switch and the first priority encoder are connected to the output of the data address of the associative address selection node, while the first information input of the data selection block is connected to the input of the initial installation of the data memory node and input control search data node associative selection of addresses, the second information input of the block data selection is connected to the data input of the data memory node, the input permission record the data access block tata - to the input control input control node of the data memory node and to the input control recording the argument of the associative address selection node, the operation mode control input of which is the input of the data selection block of the same name, the inputs of the search and reset memory arguments of which are connected to the inputs of the associative sample node of the same name addresses, memory overflow output, the first and second outputs of the search result of the associative address selection node are the outputs of the data sampling unit of the same name, the control output for by writing, the read control output and the output of the data address of the associative address selection node are connected to the inputs of the data memory node of the same name, the output of the memory overflow sign, the data output and the output of the data readiness sign of which are the outputs of the data selection block of the same name.

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