RU2003233C1 - Device for error determination in pseudorandom test signal - Google Patents

Abstract

Use in telecommunication technology, in particular in devices for extracting errors from a digital test signal in the form of a pseudo-random sequence Summary of the invention, a device for extracting errors from a pseudo-random test signal contains an input switch, a pseudo-random sequence generator (PSP), a comparator unit, an output switch, a clock generator, an input signal analyzer , blocks of registration and signals of interruptions of communication and slippage The device provides increased e reliability of isolating errors. 2 silt

Description

The invention relates to telecommunications, in particular to devices for extracting errors from a digital test signal in the form of a pseudorandom sequence (PRP), as well as for detecting digital signal slippage (synchronization disruption) and communication interruptions.

An object of the invention is to increase the reliability of error detection.

Figures 1 and 2 show structural electrical circuits of two embodiments of a device for extracting errors from a pseudo-random execution signal.

A device for isolating errors from a pseudo-random test signal contains an input switch 1, a pseudo-random sequence generator (PSP) 2, a comparator unit 3, an output switch 4, a clock driver 5, an input signal analyzer 6, a recording unit of 7 interruption signals, and a recording unit of 8 signals slippage.

The SRP generator 2 in parallel code according to the first embodiment of the device (Fig. 1) is made in the form of two (at q 2) or several (q 2) parallel circuits, each of which contains a chain of D-triggers 2.1 connected in series, at certain points which in the break of the chain includes one or more adders 2. 3 modulo two, the second inputs of which are connected to the outputs of the corresponding D-flip-flops 2.1. The number of adders 2.3 and the points of connection of its inputs are calculated by the form of the generating (generating) polynomial.

The input of the first D-flip-flop 2.1 in the chain is, respectively, the signal input of the SRP generator 2, the corresponding output of which is the output of the last D-flip-flop. In addition, an adder 2.2 modulo two, which acts as an error corrector in the transmitted signal, and its second input is the corresponding block correction input, is included in the gap of each chain. The switch-on point of this adder in the chain must necessarily be closer to the branch input than; point of connection of the nearest vanishing point of the adder 2.3. The combination of the synchronization inputs of 6-flip-flops 2.1 is the synchronization input of the block.

The comparator unit 3 is made in the form of two or more circuits, each of which contains a series / o connected adder 3.1 modulo two and

D-triggers 3.2 and 3.3. Moreover, the first and second inputs of the adder are the corresponding inputs of the first and second groups of inputs, the output of the D-trigger 3.2 is the corresponding signal output, and the output of the D-trigger 3.3 is the corresponding output of the block correction. The installation input of this trigger is the corresponding control input of the block, the synchronization input of which is the combined synchronization inputs of the D-flip-flops 3.2, 3.3. The analyzer 6 of the input signal is made in the form of two or more parallel circuits, the structure of which is similar

5 the structure of the branches of generator 2 of the SRP (only the adder 2.2 is absent modulo two) .In addition, the difference between each circuit from the generator-1 torz 2 is that the output of the latter in the chain of the D-flip-flop 6.1 through

0 adder 6.3 modulo two is connected to the control input of the counter 6.4 and the installation input of the D-flip-flop 6.5, the outputs of which are connected respectively to the first and second inputs of element 6.6 OR-NOT, the output

5 which is the corresponding output of the block.

The second input of adder 6.3 is connected to the input of another specific (calculated) circuit. In addition, the input of the first D-trigger

0 6.1 in one of the circuits is connected to the first input of the adder 6.7 modulo two, the second input of which is connected to the output of the same trigger or to the output of the second D-trigger of this circuit (the latter only with odd q and some conditions that will be described below ) The output of adder 6.7 is an additional output of the block. The combined synchronization inputs of D-flip-flops 6.1, 6.5 counter 6.4 of all circuits

0 are the block synchronization input.

The interruption signal recording unit 7 contains a counter 7.1, the synchronization input of which is the synchronization input of the unit, and the control input is the second

5 input block. The counter output is connected to the unit input to the single state of the RS flip-flop 7.2. The zero input of the trigger is the first input, and its output is the output of the block.

The 0 registration block 8 of the slip signals contains an inverter 8.1, the input of which is the first input of the block, and the output is connected to the zero input of the D-flip-flop 8.2. The information input and trigger synchronization input, respectively, are the first and synchronization inputs of the block. The inverse output of the trigger is connected to its control input, and the direct output is the slip output of the block.

In the second embodiment of the device (Fig. 2), the SRP generator 2 in the parallel block is made in the form of a block, with one signal and one correcting input. Therefore, the comparator unit 3, unlike the first embodiment, has a D-trigger 3.3 in only one circuit and the unit has only one corrective output and one control input.

In turn, the analyzer of the incoming signal has only one main output. It contains, unlike the first embodiment of the device, only one branch, similar to one of the branches of the device according to the first embodiment, and has only two signal inputs.

The SRP generator 2 is made in the form of a chain of series-connected D-flip-flops 2.1 and adders 2.2, 2.3 modulo two, included at certain points in the break of this chain. The input of the first D-flip-flop 2.1 in this chain is a signal input, the output of the last D-flip-flop 2.1 is the corresponding output, and the second input of the adder 2.2 is the generator correction input. The second input of adder 2,3 is connected to the output of the corresponding D-trigger 2.1.

The SRP generator 2 also contains one (at q 2) or several (at q 2) additional chains, sequentially in a certain order of connected adders 2.4 and D-triggers 2.5. The number of two-input adders 2.4 modulo two depends on the number of terms in the polynomial, which is multiplied by the sequence Si (81 is the corresponding sequence at the input of the SRP 2 generator) to obtain the sequence $ 2.

In this case, when using the prototype generatrix polynomial, we have S2 Si (D5 + D) and only one adder 2.4 and D-trigger 2.5 in an additional chain are needed. With a three-membered polynomial (factor for Si), two adders 2.4 and two D-flip-flops 2.5 and so on are needed. An increase in the number of D-flip-flops 2.5 is necessary in order to exclude the case of direct communication by adders 2.4, since this inclusion reduces the speed of the device.

The inputs of the first adder in the additional chain 2.4 and the second inputs of the subsequent adders 2.4 are connected to the outputs of the corresponding D-flip-flops 2.1. The output of the latter in the additional circuit of the D-flip-flop 2.5 is the corresponding output of the SRP generator 2. The combined clock inputs of D-flip-flop 2.1 and 2.5 are the block clock input.

The registration units 7 and 8 of the interruption and slipping signals can be performed in the same way as in the first embodiment of the device.

At the input of the logical unit setting, D-flip-flop 6.5 asynchronously with each error pulse (logical unit) is set to a single state regardless of the logical level of the signal at the control input. And in the absence of errors, synchronously (by the front of the clock pulse) at the D input, it either returns to the zero state if there is a logical unit at the control input, or remains in the previous state if there is a logical zero at the control input. A similar logic has a D-trigger 8.2.

Counter 6.4 is set synchronously (by the front of the clock pulse) to the initial state with a logic zero level at the output in the presence of an error pulse at the control input. If there are no errors at the control input, the counter is allowed to count clock pulses. The logic of the counter 7.1 is similar.

The described device operates as follows.

The test signal in the form of an M-sequence from the input of the device is fed to the inputs of the input switch 1 and the shaper 5 clock frequency. In the latter, the clock frequency is extracted from the test signal and q low-frequency sequences are formed uniformly shifted within the low-frequency clock interval, the value of which in q rzz exceeds the clock interval of the input signal. These sequences must be synchronous and in phase with the input signal. In this particular case, at q 2, the clock sequences are this direct and inverse sequence in the form of a meander at a half-cycle frequency.

Using these clock sequences in the input switch 1, the input high-speed SRP is partitioned into q low-speed streams by sampling 8 each stream of each q-ro element of the input sequence with a shift in the start of sampling for each stream by one element of the original sequence relative to the previous stream.

Calculations show that with such a partition of the initial sequence into q streams, each sequence of S-i-ro flows at the output of input switch 1 can be expressed through the previous

sequences (in particular, when q 2 through one previous Si-i) by multiplying them by a certain polynomial,

In this case, when using the prototype forming polynomial and splitting into two streams, it will have

S2 - Si (D5 + D7) and Si 82 (D6 + D8).

In accordance with these relations, the branches of the SRP generator 2 are made, and on the adders 3.1, the corresponding sequences are compared (Fig.). At the beginning of the operation, asynchronous sequences are generated at the output of the PSP generator 2 with respect to the corresponding sequences at the outputs of the input switch 1. This is due to the fact that initially an arbitrary code is generated in the branches of the PSP generator 2. As a result, errors are generated at the outputs of adders 3.1 even in the absence of errors in the incoming signal.

Similarly, the branches of the analyzer 6 of the input signal work and for the same reason, at the beginning of the operation, there will be errors at the outputs of the adders 6.3. With these errors, the D-flip-flops 6.5 are set to the single state, the counter 6.4 to the initial state with the level of the logical unit at the output. This output signal of the counters cannot be changed before filling in error-free sequences of D-flip-flops 6.1, since in this case the interval between two adjacent errors in each branch is always less than the counter capacity 6.4. Therefore, at the output of each element 6.6 OR there will be a logic zero level despite the fact that in the interval between two errors the D-trigger 6.5 in any branch can be set to the zero state.

Thus, from the outputs of the analyzer 6 of the input signal to the control inputs of block 3 of the comparators logic zero levels are received, allowing the passage in each branch of errors from adders 3.1 through O-flip-flops 3.2 and 3 3 to the inputs of adders 2.2, where each incoming symbol is inverted a signal that does not coincide in the current clock interval with the symbol of the reference sequence. Therefore, the generator 2 generates sequences with the same phase shift relative to the incoming ones.

This mode of operation of the device will continue until the D-flip-flops 6.1 are filled with an error-free segment of the incoming sequence. After that, at the outputs of adders 6.3, there are no errors and upon the arrival of the first symbol with a logic level at the input of the corresponding analyzer circuit 6, the corresponding D-trigger 6.5 is set to zero. The output of the corresponding counter 6.4 is also set to logic zero if the interval with no errors in the incoming signal is longer than the counter filling time. In this case, at the outputs of the analyzer 6 there will be levels of a logical unit prohibiting the correction of the incoming signal in adders 2.2. Consequently, the sequences from the input

switch 1, passage through them unchanged, is filled with D-flip-flops 2.1. After filling them with an error-free segment of the incoming sequence at the outputs of the generator 2, in-phase sequences are formed with sequences at the outputs of the input switch 1 and the process of correctly isolating errors from the incoming sequence begins. Every error in the incoming signal

is also allocated at the output of adder 6.3 in the corresponding signal in the corresponding circuit. It sets the logic zero level at the corresponding output of analyzer 6. This zero allows correction of the erroneous symbol in generator 2, thereby preserving the synchronism of generator 2 in the presence of errors in the incoming signal.

In this mode of operation of the device at

there is an error pulse at the second input of the slip signal registration unit, at its first input there will be a logic zero level, which, through inverter 8.1, keeps the D-flip-flop 8.2 at the R-input in the zero state. Therefore, slippage is the logical zero level at the output. In the presence of slippage (disturbance in phase of the incoming and reference sequences), the process

restore synchronization described above. Therefore, there will definitely be a moment when the level of the logical unit will be at the first input of block 8 (the D-flip-flops 6.1 of the corresponding circuit are filled with an error-free sequence and the corresponding counter 6 4 is full), and the errors at the second input due to the asynchronous nature of the reference signal sequences in the corresponding Perva branch

Of these errors, D-flip-flop 8.2 is brought to a single state and the last one remains in this state due to blocking by a logical zero from its inverse output. Thus, the transition from a logical zero to unity at the output, slippage of the device signals that there has been slippage,

Communication interruption in transmission systems can manifest itself in various ways. In the first case, it is a signal that does not have transitions (edges), and this can be either a logical zero or a logical unit. In the second case, such a signal occurs only at the beginning of the break, and in the rest of the break due to the action of the AGC, a random sequence of pulses due to noise appears. In addition, in some transmission systems, during a break, a signal is transmitted in the form of alternating null and single symbols.

In all these cases, at the output of counter 7.1, a logic unit level appears, setting trigger 7.2 to a state with a logic unit level at the output. This is due to the fact that regardless of the level of the signal at the input of the device (zero, one, or their alternation), the output of the adder 6.7 will necessarily have a logical zero level and the counter 7.1 will count to overflow. It should be noted only that in the latter case, so that the output of the adder 6.7 had a logical zero (with an odd number of threads), the second input of the adder 6.7 should be connected to the output of the second in the chain of the D-trigger 6.1.

Thus, the unit for recording 7 interruption signals captures an interruption, the beginning of which is determined by the presence for a certain time of a zero signal level at the additional output of the analyzer 6, and the end - by the level of a logical unit at the corresponding main output of the same unit, because the duration of the interruption at this output will necessarily be the level of logical zero. Indeed, when the connection is interrupted in the form of zero or one, the corresponding input of the analyzer 6 also has a zero or one level, therefore, after filling the D-flip-flops 6.1 with the corresponding circuit with this signal, the output of the adder 6.3 also has a zero or one level. Obviously, if there is a logical unit at the output of the adder 6.3, the logical zero level will necessarily be at the output of the OR-NOT 6.6 element. If there is a logical zero at the output of adder 6.3, the output of the OR-NOT 6.6 element will also have a logical zero level, since when filling D-flip-flops 6.1 with another signal, after the start of the break, the D-flip-flop 6.5 will surely be set to a single state and the whole interruption will remain in this state due to the prohibition of its setting to the zero state by a logical zero at its control input.

When the communication is interrupted in the form of a random sequence of pulses, a logical zero at the output of the OR-NOT 6.6 element will be supported by a logical unit from the output of counter 6.4, since in this case the error tracking interval at the output of adder 6.3 is less than the filling time of counter 6.4.

Similarly to the above, a logical zero will be maintained at the output of the OR-NOT 6.6 element during interruption of communication in the form of alternating zero and single characters.

When communication is interrupted in any form in the PSP generator 2, the phase is preserved in the sequences formed at its outputs, since the logical zeros affecting the control inputs of the comparator unit 3 allow filling in the O-triggers 2.1 included after the adders 2.2 signals of the desired structure. Thus, even when the connection is interrupted, the correct selection of errors occurs.

The selection of errors in the block of comparators 3 is removed from the outputs of the D-flip-flops 3.2 and fed to the inputs of the output comparator 4, where they are combined using clock sequences into a single high-speed stream, which is sent to the device error output.

The essence of the second embodiment of the device (figure 2) is similar to the above. The difference is that since the structure of the SRP generator 2 in the parallel code is designed so that each subsequent sequence at its outputs is formed not on the basis of the previous one, as in the first embodiment, but on the basis of one sequence, for example, Si, taken as the reference one, this leads to both a simplification of the internal structure of the blocks (for example, only one branch in the block 6 for processing the incoming signal, etc.), as well as a reduction in the number of links between them.

When using the prototype forming polynomial and splitting the incoming sequence into two streams, the generator has the structure (Fig. 2) corresponding to the following relations:

Si-SiD0 Si (Du + D15):

82 Si D

.n-1

- 1.

Si (D5 D7).

(56) USSR Copyright Certificate EJs 1037431, cl. H 04 L 1/20. 1982.

11200323312

Claims (1)

1. DEVICE ISOLATION DEVICE - input switch and is an input LATER FROM VALID 1/1 EXPERIMENT-, a test signal of the device, an OUTPUT SIGNAL, containing after-, Dami Slip and Breaks, which are connected to the input communication are outputs blocks of mountains, a generator of pseudo-random registration of slippage signals and sequences (SRP). Comparison breaks unit. uroa and output switch, control u-2 The device according to claim 1, characterized in whose input inputs and IQ control inputs are so that the input signal analyzer of the output switch is connected between complete in the form of q parallel circuits (where q are their own and with the corresponding outputs 1,2,3, ..), each of which consists of formed a clock frequency, one of which is therefore connected to the detecting block of which is connected to the inputs of the error wife, counter and OR element - synchronization of the main memory block and block 15 HE- to the other input of which are comparators, the other inputs of which are the output of the D-trigger, installation in which, with corresponding outputs, is connected to the output of the detectable input communicator unit, which is distinguished by errors, an information input which, in order to increase the reliability of which is connected to the control input of error division, an analyzer 20 of the D-flip-flop is introduced, moreover the information input of the input signal and the registration blocks of the sig-block for detecting errors of the 1st circuit of slippage and interruption connections are connected to another information input (i + zi, while the outputs of the input switch 1) of the circuit, the information input of the block - connected to the corresponding inputs of the external error errors of the qth circuit is connected to the analyzer of the input signal, the outputs of which are connected to the other error input of the first circuit by the other information input of the block of the main circuit, and the information inputs of the unit of comparators one of the inputs of which is connected to the corresponding bit of the block by detectable inputs of the q-th circuit error detection unit of the q-th circuit are connected to the inputs of the communication and the signal registration unit by the adders with modulo two, and there are slippage, the second inputs of which the information inputs of the blocks of the detected connections, respectively, with the addition of errors of g circuits, are the information output of the analyzer of the input signal signals of the analyzer of the input la and c. the corresponding output of the signal block 35, the synchronization input of which is comparators, the outputs of the correction signals are interconnected synchronously connected to the corresponding resonating inputs of the detection blocks by the inputs of the SRP generator, and the inputs of the sync errors, counters and D-flip-flops g circuits, lowering the input analyzer the signal and the outputs and additional output of the signal registration signal slippage analyzer blocks 40 of the input signal are correlations and communication breaks are connected between the outputs of the elements OR - Row E is: i c sootootsgvuyu1tsimi outputs q-output circuits and an adder for modulo d shaper clock frequency input Ko va. / Lice proscale cceeoos Vj M I