RU185051U1 - FPGA ETHERNET POWER SLIN SLAVE - Google Patents

Abstract

The utility model relates to the field of real-time industrial communication systems, namely, to a Ethernet POWERLINK network slave based on a programmable logic integrated circuit (FPGA), which includes an interface module to a physical layer microcircuit whose input / output is connected to a common data channel, to which the cyclic data exchange module and the asynchronous data exchange module are connected, which is connected to the base dictionary module, which is connected to the object dictionary memory, which is also connected to the module klicheskogo data exchange. The utility model reduces the requirements for the logical capacity of the applied FPGA and the ability to implement the device without additional memory chips.

Description

The utility model relates to the field of industrial real-time communication systems and can be used in various fields of science and industry to create control devices, distributed input / output systems and electric drives.

From the prior art, a POWERLINK Ethernet network slave device based on a programmable logic integrated circuit (FPGA) is constructed using the openPOWERLnsfK protocol stack [electronic resource: openpowerlink.sourceforge.net/web/]. Such a device contains an Altera Nios II or Xilinx MicroBlaze software processor, a module responsible for the initial processing of an Ethernet packet, filtering and buffering them, an interface module to an external processor, and a module for direct control of discrete inputs / outputs combined using a common data bus. In addition to FPGAs, this device requires 2 MB of external static memory and 32 KB of non-volatile memory.

The disadvantages of this device are the high requirements for the logical capacity of the applied FPGA and the need to use external memory chips.

The proposed utility model is aimed at solving the technical problem of eliminating this drawback.

The technical result achieved in this case is to reduce the requirements for the logical capacity of the applied FPGA and the possibility of implementing the device without additional memory chips.

The technical result is achieved in that the FPGA-based Ethernet POWERLINK network slave device includes an interface module to a physical layer microcircuit, the input / output of which is connected to a common data channel, to which a cyclic data exchange module and an asynchronous data exchange module are connected, which is connected to module of the basic dictionary, which is connected to the memory of the object dictionary, which is also connected to the module of cyclic data exchange.

These features of the utility model are significant and the combination of these features is sufficient to obtain the desired technical result.

The utility model is illustrated by the following drawing.

In FIG. 1 shows a block diagram of the claimed utility model. It contains an interface module to a physical layer 1 microchip, a common data channel 2, a cyclic data exchange module 3, an asynchronous data exchange module 4, a basic dictionary module 5, and an object dictionary 6 memory.

The device operates as follows. The interface module to the physical layer 1 microcircuit reads data from the physical layer microcircuit via the MII or RMII interface, groups bytes from them, which it transfers to a common data channel 2, to which the cyclic data exchange module 3 and the asynchronous data exchange module 4 are connected. in the common data channel 2, in order to avoid collisions during regular exchange, time division is used. In this case, in the event of collisions as a result of an emergency, priority is given to the data of the cyclic data exchange module 3. The interface module to the physical layer 1 chip reads the data recorded by the cyclic data exchange module 3 and the asynchronous data exchange module 4 into the common data channel 2, and transmits them via the MII or RMII interface to the physical layer chip. The cyclic data exchange module 3 and the asynchronous data exchange module 4 "on the fly" process the data received in the common data channel 2 and form, based on these input interfaces of each module, outgoing packets that are recorded in the common channel data 2, thereby exchanging information.

The cyclic data exchange module 3 processes the SoC, PReq, SoA packets according to the IEEE 61158 standard, as well as the formation of the PRes and ASnd packets according to the IEEE 61158 standard. The processing of the SoA packets and the formation of the ASnd packets is carried out by the cyclic data exchange module 3 only within the framework of the information exchange help the NMT team and answers to them according to the IEEE 61158 standard. Asynchronous data exchange module 4 carries out information exchange in the asynchronous phase of the Ethenet POWERLINK cycle via SDO via ASnd protocol according to IEEE 61158. Upon receipt In the PReq package, the cyclic data exchange module 3 extracts the Process Data Object from it and transfers it byte-by-bit through the input / output interface to an external processor or other core in the FPGA. When generating the PRes package, the cyclic data exchange module 3 forms the Process Data Object included in it based on the data received through the input / output interface from an external processor or other core in the FPGA. When forming ASnd packets, the cyclic data exchange module 3 uses the data read from the memory of the object dictionary 6. When organizing the information exchange, the asynchronous data exchange module 4 transfers the data received via the SDO via Asnd protocol to the base dictionary module 5, and the data necessary for generating outgoing SDO packages, receives from the base dictionary module 5. The base dictionary module 5 performs the formation of addresses and controls the reading and writing from the memory of the object dictionary 6. The memory of the object dictionary 6 represents a static dual-port memory itself, one port of which is intended for writing and reading connected to the base dictionary module 5, and the second port, which is read-only, is connected to the cyclic data exchange module 3. Together, the base dictionary module 5 and the memory of the object dictionary 6 are implemented the mandatory part of the object dictionary of the Ethernet POWERLINK slave device according to the IEEE 61158 standard. When receiving requests from the asynchronous data exchange module 4 to read data from the task-oriented part of the dictionary, the module is basic a dictionary 5 relays module asynchronous data 4 data received via input / output interface to external processor or other kernel as part of the FPGA. When receiving requests from the asynchronous data exchange module 4 to write data to a task-oriented part of the dictionary, the basic dictionary module 5 bytes relayes the data received from the asynchronous data exchange module 4 through the input / output interface to an external processor or other core in the FPGA.

The efficiency of the utility model was tested on the layout, which clearly demonstrated the receipt of the required technical result. The proposed device was implemented using a programmable logic integrated circuit Altera EP4CE15F17I7, operating at a clock frequency of 50 MHz. This unit has been tested for compliance with the Ethernet POWERLINK standard. Testing was carried out according to the EPSG DS310 standard. The test results showed full compliance of the network exchange between the utility model and the host devices with the Ethernet POWERLINK standard. For implementation, the utility model required 1870 logical FPGA cells, while the well-known analog based on the openPOWERLINK protocol stack version 2.5.2 on the same FPGA chip required 6786 logical cells, as well as additional use of a 2MB static memory chip.

Thus, the use of the utility model allowed us to reduce the requirements for the logical capacity of the applied FPGA by more than 3.5 times, as well as implement the device without the use of an additional static memory chip, which indicates the achievement of the claimed technical result.

Claims (1)

A POWERLINK Ethernet slave based on a programmable logic integrated circuit (FPGA), which includes an interface module to a physical-level microcircuit whose input / output is connected to a common data channel to which a cyclic data exchange module and asynchronous data exchange module are connected, which is connected to the base dictionary module, which is connected to the object dictionary memory, which is also connected to the cyclic data exchange module.

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