RU1837349C - Remote measuring system using information compression - Google Patents

Description

The invention relates to information in measuring technology and may find application in various automated systems for collecting, processing and transmitting telemetric information.

The device is designed to increase the accuracy of signal recovery by

etc

dark side with high dynamics;: e

te / the process being measured with a one-dimensional reduction of the information volume in the telemetry system.

The aim of the invention is to increase accuracy with high dynamics of the gel-meterable process and increase

KO „

compression ratios.

In FIG. 1 shows a functional diagram of the proposed system; Fig. 2 illustrates the structure of a transmission control unit 3; KZ fig.Z - structure of the information compression unit 9; Fig. 4 shows the structure of an information recovery unit 15; Figure 5 shows the arrangement of the buffer memory of block 12.

The telemetry system (Fig. 1) contains on the transmitting side a switch 1, an analog-to-digital converter 2, a transmission control unit 3, a divider 4, a buffer memory control element 5, a key block G, a synchronizer 7, an And 8 element, an information compression unit 9 , delay element 10, channel address encoding unit 11, buffer memory block 12, at the receiving side

00

s

sl

with

Јx

Yu

frame marker allocation lock 13, logical unit 14, information recovery unit 15, buffer memory unit 16, digital-to-analog converter (DAC) 17, resonator 18, OR element 19, address register 20, delay element 21, switch .22.

The transmission control unit 3 comprises a counter 23, an encoder 24, a decoder 25, a read-only memory unit 26. block .27 of AND elements, comparison element 28, OR element 29, the output of which is the first output of block 3, the first, second and synchronizing inputs of which are connected respectively to the first group of inputs of block 27, to the inputs of the encoder 24. the input of the counter 33, the outputs of which through the decoder 25 connected to the first inputs of block 26, the second input of which is connected to the input of the counter 23, and the outputs through the first group of inputs of the element 28, its first, second outputs - with the inputs of the element OR 29, the outputs of the encoder 24 through the second group of inputs of the block 26. his exits, second gru pu inputs his third element 28. The output connected to the second output unit 3 (Figure 2).

The information compression unit 9 (Fig. 3) contains a register 30, a generator 31, a divider 32, an AND 33 element, the first input of which is connected to the second input of the register 30 and is the control input of block 9, and the second input is to the output of the generator 31. the first input of block 9 is connected to the first input of register 30, the output, the third input of which is connected respectively to the first, second inputs of the divider 32, the output of which is the output of block 9, the output of element 33 is connected to the third input of register 30.

The information recovery unit 15 (Fig. 4) contains an I / I 34 element, the output of which is connected to the information input of the register 35, the outputs of which through a decoder 36 are connected to the outputs of the block 15, the first input of which is connected to the first input of the And 34 element and the trigger single input 38, the input of which through the delay element 37 is connected to the direct output of the trigger 38 and the input of which the write register is the second input of the block 15, the third input of which is connected to the second input of the And 34 element.

The principle of operation of the device is as follows,

In the initial state, on the transmitting side, the divider 4 is set to the position corresponding to the minimum division coefficient, there are no signals at the outputs of the elements 5, block 11, the synchronizer continuously generates pulses, the chroniser 18 is continuously working on the receiving side, and there are no outputs at the outputs of the block 14, 15, 20 -. there are signals.

For ease of description of the operation of the device

Suppose that the input of switch 1 at each moment of time is connected to one sensor, which produces a continuous analog signal. Under the control of synchronized, pulsed pulses from the second output of the synchronizer 7, the latter control the switch 1 through the divider 4 by connecting the corresponding sensor to the input of the ADC 2, which, in accordance with the amplitude of the input signal, set the synchronized pulse from the second output of the synchronizer 7 emits a binary code combination, weight. which corresponds to the amplitude of the input signal, and produces it in

0 parallel view simultaneously to block 3 and to the information inputs of block b keys.

Block 3, on the basis of comparing the model of the telemetry process with its implementation5 at a given time, makes a conclusion about the reliability of the sample, its information content and the advisability of entering buffer memory in block 12 and at the same time controls the operation of block 6.

.0 The structure of block 3 is shown in FIG. Block 3 as a result of analysis and ongoing processing of the received code combination gives an enable signal (prohibition) from the first (second) output, which

5 controls the output of a code combination to block 9 through block 6.

Synchronized pulses are fed to the synchronizing input of block 3 (counter input 23) connected to the second input of block 26

0 from the second output of the synchronizer 7, to the second, which use the inputs of the encoder 24, - information about filling the block 12 of the buffer memory, to the first - the next measurement in the form of a code combination with ADC 2, which from the output of the latter goes to the first inputs block 27 of AND elements, where depending on the state of the outputs of the encoder 24 or passes without changing to the second inputs of element 28 for subsequent comparisons under the influence of inhibit signals for lower bits the weight of the measurement falling on the first inputs of the element is reduced 28, which is equivalent to a threshold change

5 informativeness to form significant samples.

Thus, the encoder 24 and the block of And elements 27, depending on the filling of the block 12 of the buffer memory, additionally control the sampling step, which increases the number of stan 1s, the less free memory remains in block 12. Otherwise, when the latter is full, it may eo to go uncontrollably lost countdown. This rubble is all the more unpleasant because, in the principle of principle, all the samples that have passed the processing are not redundant.

A code is supplied to the first inputs of the elements 28, which, due to the fact that it is tied to the clock through the clock pulses supplied to the input of the counter 23 and to the second input; the soda of block 26 from the second output of the synchronizer 7, is essentially averaged - by a physical model of the measured process, created on the basis of the available a priori data stored in block 26. The resolution of the interrogation is determined by the bit size and, in general, by the state of the outputs of the counter 23, the state of which is determined by the address through the decoder 25 we say hey from block 26 of the code combination.

The result of the comparison in element 28 through the OR element 29 (,) in the form of a signal N in (. | Is given to the first output of block 3, and in the form of a signal N () to the second output.

The code combination set earlier at the first inputs of block 6 passes to compression block 9 if there is a signal N at the first common input of block 6. In block 9, data is reversibly compressed. For 1 compression, a signature analysis apparatus is used. The compression operation is based on the division of polynomials in the space of discrete fields with two possible elements. The sequence of binary data supplied to the inputs of the information compression unit 9 is represented as a polynomial of the corresponding degree. So, for example, the sequence I I I I I I I is written:

(p (x) x7 + xb + x5 + x4 + x3 + x2 + x 1 + x °

To obtain a polynomial signature

x) it is necessary to divide p (x) into multiple p (x) of a lesser degree, which can be

9 tsp

interpreted as

(p (x) gdr d (x) is the integral part of the division,

p (x) is the divisor,

S (x) is the signature (remainder of the division).

Having transferred, in the general case, the integer part d (x) and the signature S (x), we can compress the data, so if

p (x) - I I I I I II I

ir (x) 1 I I I I,

then you need to pass three elements

9(:

veins:

) TOnS (x) 1.

The compression ratio in this case is Ks-MVh / Mykh 8/3 2-2 / 3.

where NBX is the number of binary units per in. : Arrangement to squeeze,

, oh - the number of binary units at its output.

5 By artificially securing the position of the polynomial for the parameters being polled so that the division result during normal operation of the polled sensors is always greater than unity, we can assume that at 0 cj (x) 1, the emergency is from the transmitting side. And based on the intended use of the signature analysis apparatus, at the same time, it is possible to control the compression apparatus itself and draw a conclusion about its equality.

The described algorithm can be implemented according to known dividing schemes using an additional register and generator (Fig. 3). In block 9, the data in register 30 is entered along the leading edge of the pulse supplied to the control input. The same pulse coming from the second output of the synchronizer 7 forms a temporary gate for the generator 31, which generates frequency pulses much higher than the frequency of the synchronizer 7.

At the same time, the channel frequency pulses from the first output of the synchronizer 7 are set to the input of the element And 8 and

0 input of the delay element 10. In the absence of information about the anomalous nature of the sample (inverse input of the AND element 8), the channel frequency pulse is fed to the first (information) input of block 11, which is a bit shift register. Thus, in the low-order bit of block 11, symbol 1 corresponding to this channel is fixed. The same channel frequency pulse, passage through element 10

0 delay, shifts the contents of block 11, releasing the least significant bit to receive the next kakal character.

After the arrival of the channel pulses in the described block 11 is recorded

5 is a complete positional code of the channel address, which is read by the pulse of the polling frequency from the output of the divider 4 into the buffer memory (block 12), whose functions include sending messages to the communication line at a uniform speed. Element 5 is a decoder m, depending on the amount of remaining free memory in block 12, It generates control signals in divider 4 to change the division ratio

5 and to block 3 for forming an information threshold for the next measurement.

On the receiving side, the full telemetric signal simultaneously enters the marker selection block 13 and the third input of block 14. In block 13, which operates, for example, according to the principle of pulse selectors by their duration, the frame marker signal is extracted from the full telemetry frame, which enters the chroniser 18 and chronicles his work. With the arrival of each signal of the frame marker, the chronizer 18 generates at its third output a gating pulse with a duration equal to the duration of the generalized positional code of the channel addresses, which is fed to the first input of block 14, the second input of which receives clock pulses from the second output of the chronizer 18. Block 14 by the third output implements the function:

Z B- A,

where A is the state of the first (information) input of block 14,

B is the state of the second input of block 14,

2 - state of the third output of block 14,

The second output implements the function:

X B A. where X is the state of the second output of block 14.

On the first output it implements the function:

Y B - C, where C is the state of the first bypass of block 14;

Y is the state of the first output of block 14.

At the second output of block 14, & a register of 20 characters of the positional address code, and clock pulses through the OR element 19 are fed to the shifting input of the register 20, causing the address code characters to advance to the end of the register. After writing the address code to the register 20 at the gate (second) output of the chronizer 18, the control pulse ceases to act and block 14 then ensures that the telemetry information words pass through the recovery block 15 to block 16 and pass to its third output.

After the gating pulse ceases to act on the first input of block 14, the latter ensures the elimination of false ejection of bits of the address code from register 20 through the OR element 19, and also reveals the path of the written information words to the register 20 due to the implementation of its previously described functions. From this moment, the shift of the generalized positional address code, previously entered into the register 20, is carried out by channel pulses from the chronizer 18, coming through the OR element 19. As a result of the shift, the address code bit signals are sequentially ejected from the register 20 and fed to the second control input of block 16 through the delay element 21. The presence of 1 in the corresponding section of the generalized positional address code

determines that the information code of this channel takes place in the telemetry frame, pushing it out of register 20 is identified as a read pulse

for block 16. As a result of its action, the information code of the corresponding channel is sent to the DAC 17 and then in the form of an analog signal using the switch 22 is sent to the desired channel. The initialization of the DAC 17 and the switching of the switch 22 is carried out by channel pulses from the first output of the chronizer 18, ahead of the read pulses by the delay time in

elements 19, 21 and register 20. If the corresponding channel is not ejected from register 20 and does not carry an information code in the frame, a read pulse is not output to block 16. In that

In the case of the DAC 17 and the switch 22, the channel impulse from the chronizer 18 is idle. Thus, the reception and stretching of a compressed telemetric frame occurs, which allows using a cyclic

switching unambiguously dilute the reconstructed information in analog form through the corresponding channels.

Since block 15 restores the result after dividing by a constant value

(used by the polynomial), then the initial state can be identified using a circuit based on a conventional decoder (Fig. 4). In the presence of a gating pulse at the first input, information in

in the form of a sequential code combination, it passes through element 24 to the information input of register 35 and is recorded in the last by clock pulses. On the trailing edge of the gating pulse

trigger 38, which generates a read signal, is activated, and from the code combination register 35, it is supplied in parallel to the inputs of decoder 36. Simultaneously with the direct output of trigger 38, a single signal through delay element 37 resets trigger 38 to state O, thus forming a short a pulse for issuing information from the register 35. From the output of the decoder 36 code combination falls on

block inputs 16.

Thus, with high dynamics of the telemetry process, an increase in the accuracy of signal recovery at the receiving side is achieved by changing the information threshold for the next sample, which additionally takes into account the amount of remaining free memory on the transmitting side. This is equivalent to eliminating the defect.

j pulses (e.g., when the I block 12 of the buffer memory overflows). In this case, due to the use of the arina-I signature analysis during data compression, information exchange in the telemetry system is also significantly reduced.

Claims (3)

The formula is as follows. 1. A telemetry system with information compression, containing a switch on the transmitting side, the information inputs of which are information inputs of the system's transmitting side, the output is connected to the input of an analog-to-digital converter, a synchronizer, the first input of which is through an element the delay is connected to the first input of the channel address encoding unit and directly to the direct input of the And element, the output of which is connected to the second input of the channel address encoding unit, the output of which is connected to the input of the buffer memory unit, the second input of which is connected to the output of the information compression unit, the control input of which is connected to the second output of the synchronizer, the first output of the buffer memory unit is connected to the communication channel, on the receiving side, the frame marker extraction unit, the input of which is connected with a communication channel, the output is connected to the input of the chronizer, the first output of which is connected to the clock inputs of the digital-to-analog converter, switch, and the first input of the OR element. the output of which is connected to the first input of the address register, the second output of the chronizer is connected to the first control input of the buffer memory unit, the group outputs of which are connected via digital-to-analog converter to the information inputs of the switch, the outputs of which are outputs of the receiving side of the system, characterized in that, in order to increase accuracy with high dynamics of the telemetry process and increase the compression ratio, a key block, a buffer memory control element, bl ok transmission control and a divider, the output of which is connected to the control inputs of the analog-to-digital converter, switch and the third input of the coding block of the channel address, the second output of the sync-ionizer is connected to the first input of the healer and to the synchronizing input of the transfer control elok, the first output which is connected to the first input of the keys, the second output is with its second input and the inverse input of the element And, the output of the analog-to-digital converter is connected 5 with the first input of the transmission control unit and information inputs of the key block, the output of which is connected to the input of the information compression unit, the second output of the buffer memory unit is connected to the second inputs of the divider and transmission control unit via the buffer memory control element, on the receiving side, the logic block , a delay element and an information recovery unit, the first inputs of which and 5 logical units are connected to the third output of the chroniser, the second output of which is connected to the second inputs of the logical unit and the information recovery unit, the group outputs of which are connected to the group inputs of the buffer memory unit, the second control input of which is connected via the delay element to the output of the address register , the first output of the logical unit is connected to the second input of the OR element, 5, the second input of the address register is connected to the second output of the logical unit, the third output of which is connected to the third input of the information recovery unit, the third input of the logical unit is combined with the input 0 frame marker allocation block. 2. The system according to claim 1, with the fact that the information compression unit contains a register, a divider, an element And a pulse generator, the output of which is connected to the first input of the element And the second input of which and the first the input of the register is combined and is the control input of the block, the second input of the register is the input of the block, the output is connected to the first input of the divider, 0 whose second input and the control input of the register are combined and connected to the output of the AND element, the output of the divider is the output of the block. 3. The system according to claim 1, with the exception of 5, that the information recovery unit contains a register, a decoder, a trigger, a delay element and an element 11, the first and second inputs of which are the first and third inputs of the block, the output is connected to 0 by the information input of the register, the first input of which is the second input of the block, the group outputs are connected to the inputs of the decoder, the outputs of which are the output of the block, the first input of the trigger is connected to the first input of the And element, the output is connected to the second input of the register and through the delay element its second entrance. JAN & OSHE & 0MEL (/ 1 /  tfotowopaddu ebciesi J / 35 (pЈ / & 3 .Ј 32 p # p. 4 pv.5