RU1810987C - Digital transverse filter - Google Patents

Abstract

Usage: radio engineering for filtering signals defined by a digital code in limited bandwidth communication channels. The inventive digital transverse filter contains information input 1, shift register 2, multipliers 3-1, ..., 3-p by weights, adder l, clock generator 5 containing input 6 of the setting frequency, driver 7 pulses , a band-pass filter 8 and a comparator 9, and an output of 10. 6 ill.

Description

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The invention relates to radio engineering and can be used to filter signals specified by a digital code in limited bandwidth communication channels.

The purpose of the invention is to reduce intersymbol interference.

In FIG. 1 is an electrical block diagram of a digital transverse filter; in FIG. 2-6 diagrams explaining his work.

The digital transverse filter contains information input 1, shift register 2, weighting factors 3-1 ... 3-p, adder 4, clock pulse generator 5, which contains input 6 of the setting frequency, driver 7 pulses, bandpass filter 8 and comparator 9 and exit 10.

The digital transverse filter operates as follows.

The clock signal is fed to input b (Fig. 2. a). At the output of the pulse shaper 7, leading edges of the clock pulses are allocated (Fig. 2Bb). At the output of the bandpass filter 8, a sinusoidal signal of one of the higher harmonics (Fig. 2, c) contained in the output signal of the pulse shaper 7 is extracted. At the output of the comparator 9, a new clock frequency is generated (Fig. 2d), several times higher than the clock frequency supplied to input 6. As a result, the digital signal advances along shift register 2 at a speed K times greater than the speed of the input information signal . Moreover, for the bit length of the input information, it is possible to obtain additional weighted values of the signal, which make it possible to approximate the envelope of the form as accurately as possible.The coefficient of increase in the clock frequency K is equal to K 2 (n + 1), where n 1, 2, 3, ... etc. The recommended value is n 1. In this case, the clock frequency will increase four times (K 2 (1 + 1). The number of bit intervals of the shift register 2 is B 1 + 2 m, where m 1, 2, 3, ..., etc. The recommended value is t 2. In this case, the number of bit intervals of the shift register 2 will be equal to five (B 1 + 2 + 2). The total length of the shift register 2 will be equal to d SCR.

For the correct choice of the polarity and weight coefficients of 3-1, .. 3-p multipliers, we can consider the reaction to a positive edge of the input information signal (Fig. 3), where At is the duration of the clock interval. If the selectivity condition is met, the output signal should be as shown in FIG. 4. Consider the signal in the AF area, which corresponds to the duration of five clock intervals. We divide each of the AB, B-C, CD, DE, and EF sections into intervals equal to At / K (in our case, four parts) and We take the amplitude sampling on each interval of At / 4 duration (Fig. 5).

The polarity and approximate values of the weights obtained in FIG. 5 are shown in the table. More accurate values of the weighting coefficients are obtained by practical implementation of the filter by their selection.

As can be seen from the table, when implementing the filter, two rules must be satisfied: the weighting coefficients of the bit intervals, pairwise symmetric with respect to the central bit interval C-D,

must be mutually inverse. In our case, the weights of the D-E bit interval are inverse to the B-C bit interval, and the weights of the E-F bit interval are inverse to the A-B bit interval.

The sum of the weights of each bit interval (except for the C-D interval) must always be zero. In this case, the response of the filter to a single pulse

shown in FIG. 6.

Claims (1)

The claims A digital transverse filter containing an adder, a shift register, the outputs of which through their respective weighting factors are connected to an adder, the output of which is the output of a digital transversal filter, as well as a clock generator, the output of which is connected to the clock input of the shift register, the information input of which is the information input of a digital transverse filter, characterized in that, in order to reduce intersymbol interference, the clock generator is tunable with an increase in clock frequency K 2 (n + 1) relative to the clock frequency of the information signal, the length of the shift register is d K B, where B 1 + 2p is the number of bit intervals of the shift register, weight, multiplier coefficients by weight coefficients in pairs symmetric and mutually inverse with respect to the central bit interval, and the sum of the weighting coefficients of each bit interval, except the central, is zero. , fo % t / ,