RU1784989C - Computer and periphery line conjugating device - Google Patents

Abstract

The invention relates to the field of computing and can be used to exchange information between subscribers. The aim of the invention is to reduce hardware costs and expand the functionality of the device by ensuring the adaptation of the transmission speed of the communication lines between the subscribers between the subscribers. The goal is achieved in that the device contains a block of channel transceivers, a block for decrypting addresses and commands, an interrupt block, linear amplifier unit, transceiver unit, line status register, readiness polling multiplexer and clock generator, the exchange rate control unit is introduced , a state signal switching unit and a channel transmitter unit. 8 ill.

Description

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The invention relates to the field of computer technology and can be used in computer networks to exchange information between subscribers.,

Known devices for interfacing with a communication line comprising a channel amplifier unit, an address and command decryption unit, a command and status register unit, a priority unit, a synchronization unit, an interrupt vector generating unit, a linear amplifier unit, a transceiver unit, a mode selection unit and a direct access signal generation unit.

The disadvantage of this device is the high hardware costs,

Closest to this essentially technical solution is a device for interfacing with communication lines, comprising a channel amplifier unit, an address and command decryption unit, a unit

registers of commands and states, priority block, block for specifying interrupt vectors, block of linear amplifiers, block for receiving and transmitting, register for enabling interrupts, and a readiness polling multiplexer.

The disadvantage of this device is the high hardware costs and limited functionality, eliminating the possibility of operational changes in the exchange rate on the communication line.

The aim of the invention is to reduce hardware costs and expand the functionality of the device by providing adaptation of the transmission speed of the communication lines when exchanging information between subscribers.

This goal is achieved in that in the device containing the channel transceiver unit, the decryption unit

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addresses and commands, interrupt block, linear amplifier block, transceiver block, line status register, readiness polling multiplexer and clock generator, the groups of clock inputs and the first output groups of the command and address decryption block and the interrupt block are connected to the corresponding groups of inputs and outputs of the device for connecting control buses to the computer, the group of address inputs of the readiness multiplexer is connected to the second group of outputs of the address decryption unit and commands, the first group of the formation inputs / outputs of the channel transceiver unit is a group of inputs / outputs of the device for connecting to the address and information buses of the computer, and the second group of information inputs and outputs is connected to the group of information inputs and outputs of the transceiver unit, the group of information inputs a block for decoding addresses and commands and a group of outputs of a readiness multiplexer, the first group of information inputs of which is connected to a group of request inputs of an interrupt unit and a group of readiness outputs for a read unit IMO transmissions, a group of address inputs connected to a third group of outputs of a block for decrypting addresses and commands, groups of information-control inputs and outputs of a block of linear amplifiers are corresponding groups of inputs and outputs of a device for connecting to the corresponding groups of information and control outputs and inputs of communication lines, a group of information inputs and outputs and a group of readiness outputs of a block of linear amplifiers are connected respectively to groups of information outputs and inputs and a group of inputs of the transceiver unit, the group of inverted outputs of the line status register is connected to the group of inputs of the linear amplifier unit mode, and the information input and the group of sync inputs are respectively connected to the second group of information inputs and outputs of the channel transceiver unit and the fourth group of outputs of the decryption unit addresses and commands, the first information input connected to the first output of the interrupt unit, and the output - to the enable input of the channel transceiver unit, a group of information inputs which connected to the second group of outputs of the interrupt unit, a speed control unit, a status signal switching unit and a channel transmitter unit are introduced, the group of information input-outputs of the speed control unit and the group of information inputs of the interrupt unit and the output of the status signal switching unit are connected to the second a group of information inputs / outputs of the channel transceiver unit, the sample input of which is the input of the device for connecting to the computer control bus, and the output is connected to the second information input of the address and command decryption unit, the fifth output group of which is connected to the enable inputs of the channel transmitter unit, the state signal switching unit, and the interrupt unit, the second group of outputs connected to the second group of information inputs of the readiness multiplexer, group

the address inputs of the interrupt block is connected to the fourth group of outputs of the address and command decryption block, the sixth group of outputs of which is connected to the group of inputs of the speed control block mode, the clock input and output connected to the output of the clock pulse generator and the clock input of the transceiver block, the group of signal outputs whose errors and the group of direct outputs of the line status register are connected respectively to the first and second groups of information inputs of the state signal switching unit , a group of outputs connected to a group of information inputs of a channel transmitter unit, a group of outputs of which is a group of outputs of a device for connecting to an address-information computer bus, the information input of a state signal switching unit is connected to a second group of outputs of an address decoding unit and commands, a group of readiness inputs block of linear amplifiers is connected to the group of readiness outputs of the receive-1 transmission unit, the reset input of which is connected to the second output of the interrupt unit and the reset inputs of the reg country of the states of the lines and the speed control unit.

In FIG. 1 shows a block diagram of a device; in FIG. 2-8 are functional diagrams of a channel amplifier unit, an address and instruction decryption unit, an interrupt unit, an exchange rate control unit, a transmission / reception unit, a status signal switching unit, a readiness polling multiplexer, and a linear amplifier unit.

The device comprises (see Fig. 1) a block 1 of channel transceivers, a block 2 of deciphering addresses and commands, a block 3 of interrupt EEE, a block of 4 speed control

exchange unit, transceiver unit 5, register 6 status lines, unit 7 switching state signals, multiplexer 8 polling readiness generator 9 clock pulses, block 10 linear amplifiers and block 11 channel transmitters.

In FIG. 1 also shows groups of 12 outputs and inputs for communication with terminal equipment of communication lines, computer bus 13, information bus 14 of the internal bus of the device, and interconnect communication lines 15-35 of the device.

Block 1 of the channel transceivers serves to communicate the device with the information buses 13.1 of the main computer and contains (see FIG. 2) a node 36 of bus drivers, a device 37 address device, a device 38 interrupt vector codes, a matching resistor 39, a positive field bus 40 rnosti. As bus formers node 36 can be used, for example, bus formers type 559IP8.

Unit 2 for decrypting addresses and commands is intended for deciphering the addresses of device units and commands that are issued to the device via bus 13. Block 2 contains (see Fig. 3} register 41, input amplifiers 42, elements And 43 and 44, output amplifier 45, delay element 46, read-only memory nodes (ROM) 47, terminating resistor assembly 49, termination resistors 50.

Interrupt block 3 is used to determine the priorities of incoming requests and synchronize communication in the computer interrupt mode. Block 3 contains (see Fig. 4) the first flip-flop 51, interrupt processing units 52-54, made, for example, on the BIS 559BH1, a read-only memory (ROM) unit 55, a switch 56, OR elements 57-60, limiting resistors 61 and 62.2, second trigger 63.

The exchange rate control unit 4 is designed to receive and store device exchange speed parameters and generate the corresponding clock frequencies. Block 4 in the example shown in FIG. 5, comprises a node 64 for setting the initial exchange rate, counters 65 and 66, a division register 67, a multiplexer 68, and a channel amplifier unit 69.

The transceiver unit 5 is designed for parallel-serial conversion during transmission and serial-parallel conversion when receiving from a communication channel (line), synchronizing the processes of reception and transmission, detecting format errors and synchronization during exchange. Block 5 contains (see Fig. 6)

nodes 70 and 71 reversibly convert parallel code to serial. made, for example, on BIS581BA1, and elements And 72 and 73.

5 Block 7 switching state signals

it is intended for switching error signals and the status of lines on buses 13 and contains (see Fig. 7) a switch 74 and an OR element 75 and a channel transmitter 76.

0 Block 11 contains channel transmitters 77.

 The block 10 of linear amplifiers for each channel, for example, with the interface C2t contains (see Fig. 8) a group of input amplifiers

5 78, converting the bipolar signals of the joint C2 (e.g., circuits 106 and 104) into TTL levels of logic elements of block 5, and a group of output amplifiers 79. performing the inverse level conversion,

0 for example, for circuits 103 and 105 of junction C2.

The device operates as follows.

The device exchanges data between computers and communication lines in the mode

5 interruptions or in the readiness scan mode specified by the computer program by writing to the internal registers of nodes 52, 53, 54 (see Fig. 4) the corresponding information.

0 The computer processor in a standard way sets the interrupt enable flag in the internal register of node 52 to the active state (53, 54). Since the transmitter of the node 70 (71) is ready for transmission,

5, a single signal of its readiness on line 26.2 (26.4) in the presence of a high-level PREV.PD1 (PIT.PP2) signal is sent to node 52 (53), which generates a low level signal on the line

0 13.9 as the TPR signal of the processor interrupt request.

The processor, by issuing interrupt enable signals (PPR) and input (ENTER) on line 13.6 and 13.4, starts blocks 52 (53). the signals from the outputs of which, through the elements of IL AND 57-60, specify the interrupt vector code. Through a chain of elements 45,46, a sequence of signals is triggered to provide the interrupt vector code to the buses 13

0 generated by block 36 by the code on lines 16. Next, the processor provides data bytes to the device for transmission to line 12. For this, the processor, referring to the data register of node 70 (71), issues to buses 13

5, in the information part of the cycle, the OUTPUT of data bytes is entered into the transmitter data register by the signal in line 20.1 formed by block 48.

The further transmission of this byte, the node 70 (71) carries out independently, and after transmitting it to the line, it again sets the signal on the line 26.2 to receive the next byte from the processor, etc. This process is repeated until the computer processor resets the interrupt enable sign in the register of node 52 (53).

Information from the communication line in the interrupt mode is carried out in the following sequence. By setting the acceptance interruption sign in the node 52 (53) register, the computer program allows the processor to be interrupted after receiving a byte of data from line 12. At the time the byte is received from line 30.1, node 70 generates a signal on line 26.1, which starts the processor interrupt procedure, which is performed similar to that described above. When the processor reads the contents of the receiver data register of the node 70 (71), the contents of the error register of the node 70 (71) can be read on bits 12-15 of bus 13 through the channel transmitter unit 11 (Fig. 7). Upon receipt of the next bytes from line 12, processor interrupts will be triggered by a signal on line 26.1 until the receipt of the interrupt on receipt in the internal register of node 52 (53) is cleared.

The device provides the ability to interrupt the processor upon the occurrence of some event F. Event code F is pre-programmed in ROM 55. For each code, two interrupt vectors can be generated that are generated in node 36 by the signals at the output of node 54 (see FIG. 4).

The interrupt on event Ф occurs as follows. Prior to reading the data byte received from line 12 from node 70 (71), the processor through block 2 supplies a signal to line 20.3 (20.4) that opens the receive buffer register of node 70 (71) to send the read byte to bus 14. At the same time, block 2 generates line 22.2, the read signal arriving at the ROM 55. The signal on the line 22.2 opens the ROM 55, decrypts the value of the data code on the bus 14 and generates an interrupt request signal, Kq Which through the switch 56 is received and fixed on the triggers 51 and 63 With non-zero values of these signals at the outputs of flip-flops 51 and 63, node 54 s ormiruet TPD signal an interrupt request on the line 13.9, which will be served by a computer processor. The TPR signals received from nodes 52-54 are serviced in priority order, determined by the physical connection of the nodes between lines 13.6.

The device allows you to change the exchange rate along lines 12.

This function is implemented as follows. Before turning on the device, at node 64, the initial exchange rate is set. After the device is turned on, a clock frequency is issued that determines the speed of the receivers and transmitters of block 5. The clock frequency in line 28 is generated by dividing the reference frequency of the generator 9 obtained via line 27. To change the speed, it is necessary to write in the division register 67 the corresponding constant defining division ratio. Writing and reading to register 67 is performed by the processor in a standard manner. When accessing register 67 for writing, block 2 generates a signal in line 18.2, and when accessing for reading, in line 18.1.

The mechanism by which the processor decides whether to change the exchange rate may be different. For example, if the processor determines that a large number of received messages arrive with errors and, as a result, a decrease in the exchange rate is required, then in the next message or in a special service message, it can set a command to reduce the exchange rate. This command triggers event Φ on the opposite side or is decrypted by some other agreed-upon appropriate exchange protocol. When reacting to this command, the opposite side will either immediately change the constant in its register 67, or make such a change after exchanging some service messages.

Claims (1)

SUMMARY OF THE INVENTION A device for interfacing computers with communication lines, comprising a channel transceiver block, an address and command decryption block, an interrupt block, a linear amplifier block, a transceiver block, a line status register, a readiness polling multiplexer, and a clock generator, synchronization groups the inputs and the first groups of outputs of the address and command decryption unit and the interrupt block are the corresponding input and output groups of the device for connecting to the computer control buses, the address group x inputs of the readiness multiplexer is connected to the second group of outputs of the address and command decryption unit, the first group of information inputs and outputs of the channel transceiver unit is the group of inputs and outputs of the device for connecting to the address and information buses of the computer, and the second group of information inputs and outputs is connected to a group of information inputs and outputs of a transceiver block, a group of information inputs of a block of addresses and commands decoder, and a group of outputs of a readiness survey multiplexer, the first the group of information inputs of which is connected to the group of request inputs of the interrupt unit and the group of readiness outputs of the transceiver unit, the group of address inputs connected to the third group of outputs of the address and command decryption unit, the group of information-control inputs and outputs of the linear amplifier block are the corresponding groups of inputs and outputs devices for connecting to the respective groups of information and control outputs and inputs of communication lines, groups of information inputs and outputs and a group of outputs in the readiness of the block of linear amplifiers, they are connected respectively to the groups of information outputs and inputs and the group of readiness inputs of the block of the transceiver, the group of inverse outputs of the line status register is connected to the group of inputs of the mode mode of the block of linear amplifiers, and the information input and the group of clocks respectively to the second group - formation inputs and outputs of the channel transceiver unit and the fourth group of outputs of the address and command decryption unit, the first information input connected to the first output ode to the interrupt unit, and the output to the enable input of the channel transceiver unit, the group of information inputs of which is connected to the second group of outputs of the interrupt unit, characterized in that, in order to reduce the hardware costs of the device and expand its functionality by providing adaptation of the transmission speed over communication lines during the exchange of information between subscribers, a speed control unit, a status signal switching unit and a channel transmitter unit are introduced into it, the group of information the communication inputs and outputs of the exchange rate control unit and the group of informational 5 inputs of the interrupt unit and the output of the status signal switching unit are connected to the second group of information inputs and outputs of the channel transceiver unit, sampling input of which 0 is the input of the device for connecting to the control bus of the computer, and the output is connected to the second information input of the block for decrypting addresses and commands, the fifth group of outputs of which is connected to the inputs of the resolution of the channel transmitter block, the switching block status signals and interrupt unit, the second group of outputs connected to the second group of information inputs of the multiplexer 0 readiness readiness, the group of address inputs of the interrupt block is connected to the fourth group of outputs of the block of address and command decryption, the sixth group of outputs of which is connected to the group of inputs of the 5th mode of the exchange rate control unit, the clock input and output of the clock pulse generator and the clock input of the block connected respectively transceiver, group of signal outputs 0 errors of which and the group of direct outputs of the line status register are connected, respectively, by the first and second groups of information inputs of the state signal switching unit, by the group of outputs 5 connected to the group of information inputs of the channel transmitter unit, the output group of which is the group of outputs of the device for connecting to the address - computer information bus, 0 the information input of the state signal switching unit is connected to the second group of outputs of the address and command decryption unit, the readiness input group of the linear amplifier unit is connected to the group 5 readiness outputs of the transceiver block, the reset input of which is connected to the second output of the interrupt block and the reset inputs of the line status register and the speed control unit v Ј1 -T x -L 6; TH & W t m f-tf jtftfti to fi t m "I J , I ha from 00 O) hso g- 68617811 d, 1  MM 7